/**
*   @ file    Calypso_Resource.m
*   @ version 1.0.0
*
*   @ brief   AUTOSAR Port - Resource for this platform
*   @ details Resource for this platform
*/
/*==================================================================================================
*   Project              : AUTOSAR 4.2 MCAL
*   Platform             : PA
*   Peripheral           : SIUL2
*   Dependencies         : none
*
*   Autosar Version      : 4.2.2
*   Autosar Revision     : ASR_REL_4_2_REV_0002
*   Autosar Conf.Variant :
*   SW Version           : 1.0.0
*   Build Version        : MPC574XG_MCAL_1_0_0_RTM_ASR_REL_4_2_REV_0002_20170217
*
*   (c) Copyright 2006-2016 Freescale Semiconductor, Inc. 
*       Copyright 2017 NXP
*   All Rights Reserved.
==================================================================================================*/
[!IF "not(var:defined('PORT_RESOURCE_M'))"!]
[!VAR "PORT_RESOURCE_M"="'true'"!]
[!VAR "PinMap"!]
EMIOS0_E0UC_0_X_OUT_PORT0;1:[!//
CGM_CLKOUT0_PORT0;2:[!//
EMIOS0_E0UC_13_H_OUT_PORT0;3:[!//
WKPU_WKPU_19_PORT0;9:[!//
EMIOS0_E0UC_0_X_IN_PORT0;11:[!//
EMIOS0_E0UC_13_H_IN_PORT0;12:[!//
EMIOS0_E0UC_0_X_IN_OUT_PORT0;17:[!//
EMIOS0_E0UC_13_H_IN_OUT_PORT0;19:[!//
FlexCAN_1_RX_PORT0;13:[!//
EMIOS0_E0UC_1_G_OUT_PORT1;1:[!//
WKPU_WKPU_2_PORT1;9:[!//
WKPU_NMI_0_PORT1;9:[!//
EMIOS0_E0UC_1_G_IN_PORT1;11:[!//
FlexCAN_3_RX_PORT1;12:[!//
EMIOS0_E0UC_1_G_IN_OUT_PORT1;17:[!//
EMIOS0_E0UC_2_G_OUT_PORT2;1:[!//
ADC_0_ADC0_MA_2_PORT2;3:[!//
WKPU_WKPU_3_PORT2;9:[!//
EMIOS0_E0UC_2_G_IN_PORT2;11:[!//
EMIOS0_E0UC_2_G_IN_OUT_PORT2;17:[!//
EMIOS0_E0UC_3_G_OUT_PORT3;1:[!//
LIN_5_LIN5TX_PORT3;2:[!//
DSPI_1_dCS4_PORT3;3:[!//
ADC_1_ADC1_S_0_PORT3;10:[!//
EMIOS0_E0UC_3_G_IN_PORT3;11:[!//
SIUL2_EIRQ0_PORT3;12:[!//
ENET0_MII_0_RX_CLK_PORT3;13:[!//
EMIOS0_E0UC_3_G_IN_OUT_PORT3;17:[!//
EMIOS0_E0UC_4_G_OUT_PORT4;1:[!//
DSPI_1_dCS0_PORT4;2:[!//
EMIOS0_E0UC_24_X_OUT_PORT4;3:[!//
WKPU_WKPU_9_PORT4;9:[!//
CMP1_CMP1_13_PORT4;10:[!//
EMIOS0_E0UC_4_G_IN_PORT4;11:[!//
LIN_5_LIN5RX_PORT4;12:[!//
DSPI_1_dSS_PORT4;13:[!//
EMIOS0_E0UC_24_X_IN_PORT4;14:[!//
EMIOS0_E0UC_4_G_IN_OUT_PORT4;17:[!//
EMIOS0_E0UC_24_X_IN_OUT_PORT4;19:[!//
EMIOS0_E0UC_5_G_OUT_PORT5;1:[!//
LIN_4_LIN4TX_PORT5;2:[!//
EMIOS0_E0UC_5_G_IN_PORT5;11:[!//
EMIOS0_E0UC_5_G_IN_OUT_PORT5;17:[!//
EMIOS0_E0UC_6_G_OUT_PORT6;1:[!//
DSPI_1_dCS1_PORT6;2:[!//
EMIOS0_E0UC_6_G_IN_PORT6;11:[!//
SIUL2_EIRQ1_PORT6;12:[!//
LIN_4_LIN4RX_PORT6;13:[!//
EMIOS0_E0UC_6_G_IN_OUT_PORT6;17:[!//
EMIOS0_E0UC_7_G_OUT_PORT7;1:[!//
LIN_3_LIN3TX_PORT7;2:[!//
ADC_1_ADC1_S_8_PORT7;10:[!//
EMIOS0_E0UC_7_G_IN_PORT7;11:[!//
SIUL2_EIRQ2_PORT7;12:[!//
ENET0_MII_0_RXD_2_PORT7;13:[!//
EMIOS0_E0UC_7_G_IN_OUT_PORT7;17:[!//
EMIOS0_E0UC_8_X_OUT_PORT8;1:[!//
EMIOS0_E0UC_14_H_OUT_PORT8;2:[!//
ADC_1_ADC1_S_9_PORT8;10:[!//
EMIOS0_E0UC_8_X_IN_PORT8;11:[!//
EMIOS0_E0UC_14_H_IN_PORT8;12:[!//
SIUL2_EIRQ3_PORT8;13:[!//
LIN_3_LIN3RX_PORT8;14:[!//
ENET0_MII_RMII_0_RXD_1_PORT8;15:[!//
EMIOS0_E0UC_8_X_IN_OUT_PORT8;17:[!//
EMIOS0_E0UC_14_H_IN_OUT_PORT8;18:[!//
EMIOS0_E0UC_9_H_OUT_PORT9;1:[!//
DSPI_1_dCS2_PORT9;2:[!//
ADC_1_ADC1_S_10_PORT9;10:[!//
EMIOS0_E0UC_9_H_IN_PORT9;11:[!//
ENET0_MII_RMII_0_RXD_0_PORT9;12:[!//
EMIOS0_E0UC_9_H_IN_OUT_PORT9;17:[!//
EMIOS0_E0UC_10_H_OUT_PORT10;1:[!//
IIC_0_SDA0_OUT_PORT10;2:[!//
LIN_2_LIN2TX_PORT10;3:[!//
ADC_1_ADC1_S_11_PORT10;10:[!//
EMIOS0_E0UC_10_H_IN_PORT10;11:[!//
IIC_0_SDA0_IN_PORT10;12:[!//
DSPI_1_dSIN_PORT10;13:[!//
ENET0_MII_0_COL_PORT10;14:[!//
EMIOS0_E0UC_10_H_IN_OUT_PORT10;17:[!//
IIC_0_SDA0_IN_OUT_PORT10;18:[!//
EMIOS0_E0UC_11_H_OUT_PORT11;1:[!//
IIC_0_SCL0_OUT_PORT11;2:[!//
ADC_1_ADC1_S_12_PORT11;10:[!//
EMIOS0_E0UC_11_H_IN_PORT11;11:[!//
SIUL2_EIRQ16_PORT11;12:[!//
LIN_2_LIN2RX_PORT11;13:[!//
IIC_0_SCL0_IN_PORT11;14:[!//
ENET0_MII_RMII_0_RX_ER_PORT11;15:[!//
EMIOS0_E0UC_11_H_IN_OUT_PORT11;17:[!//
IIC_0_SCL0_IN_OUT_PORT11;18:[!//
EMIOS0_E0UC_28_Y_OUT_PORT12;1:[!//
DSPI_1_dCS3_PORT12;2:[!//
EMIOS0_E0UC_26_Y_OUT_PORT12;3:[!//
CMP1_CMP1_15_PORT12;10:[!//
EMIOS0_E0UC_28_Y_IN_PORT12;11:[!//
SIUL2_EIRQ17_PORT12;12:[!//
DSPI_0_dSIN_PORT12;13:[!//
EMIOS0_E0UC_26_Y_IN_PORT12;14:[!//
GLITCH_FILTER0_INP_PORT12;15:[!//
EMIOS0_E0UC_28_Y_IN_OUT_PORT12;17:[!//
EMIOS0_E0UC_26_Y_IN_OUT_PORT12;19:[!//
DSPI_0_dSOUT_PORT13;1:[!//
EMIOS0_E0UC_29_Y_OUT_PORT13;2:[!//
FlexCAN_0_TX_PORT13;4:[!//
EMIOS0_E0UC_25_Y_OUT_PORT13;3:[!//
CMP1_CMP1_14_PORT13;10:[!//
EMIOS0_E0UC_29_Y_IN_PORT13;11:[!//
EMIOS0_E0UC_25_Y_IN_PORT13;12:[!//
GLITCH_FILTER0_INP_PORT13;13:[!//
EMIOS0_E0UC_29_Y_IN_OUT_PORT13;18:[!//
EMIOS0_E0UC_25_Y_IN_OUT_PORT13;19:[!//
DSPI_0_dSCLK_OUT_PORT14;1:[!//
DSPI_0_dCS0_PORT14;2:[!//
EMIOS0_E0UC_0_X_OUT_PORT14;3:[!//
EMIOS0_E0UC_23_X_OUT_PORT14;4:[!//
CMP1_CMP1_12_PORT14;10:[!//
EMIOS0_E0UC_0_X_IN_PORT14;11:[!//
SIUL2_EIRQ4_PORT14;12:[!//
DSPI_0_dSCLK_IN_PORT14;13:[!//
DSPI_0_dSS_PORT14;14:[!//
EMIOS0_E0UC_23_X_IN_PORT14;15:[!//
DSPI_0_dSCLK_IN_OUT_PORT14;17:[!//
EMIOS0_E0UC_0_X_IN_OUT_PORT14;19:[!//
EMIOS0_E0UC_23_X_IN_OUT_PORT14;20:[!//
DSPI_0_dCS0_PORT15;1:[!//
DSPI_0_dSCLK_OUT_PORT15;2:[!//
EMIOS0_E0UC_1_G_OUT_PORT15;3:[!//
EMIOS0_E0UC_21_Y_OUT_PORT15;4:[!//
WKPU_WKPU_10_PORT15;9:[!//
CMP1_CMP1_10_PORT15;10:[!//
EMIOS0_E0UC_1_G_IN_PORT15;11:[!//
FlexCAN_0_RX_PORT15;12:[!//
DSPI_0_dSCLK_IN_PORT15;13:[!//
DSPI_0_dSS_PORT15;14:[!//
EMIOS0_E0UC_21_Y_IN_PORT15;15:[!//
DSPI_0_dSCLK_IN_OUT_PORT15;18:[!//
EMIOS0_E0UC_1_G_IN_OUT_PORT15;19:[!//
EMIOS0_E0UC_21_Y_IN_OUT_PORT15;20:[!//
FlexCAN_0_TX_PORT16;1:[!//
EMIOS0_E0UC_30_Y_OUT_PORT16;2:[!//
LIN_0_LIN0TX_PORT16;3:[!//
EMIOS0_E0UC_4_G_OUT_PORT16;4:[!//
CMP0_CMP0_2_PORT16;10:[!//
EMIOS0_E0UC_30_Y_IN_PORT16;11:[!//
EMIOS0_E0UC_4_G_IN_PORT16;12:[!//
GLITCH_FILTER1_INP_PORT16;13:[!//
EMIOS0_E0UC_30_Y_IN_OUT_PORT16;18:[!//
EMIOS0_E0UC_4_G_IN_OUT_PORT16;20:[!//
EMIOS0_E0UC_31_Y_OUT_PORT17;1:[!//
EMIOS0_E0UC_5_G_OUT_PORT17;2:[!//
WKPU_WKPU_4_PORT17;9:[!//
CMP0_CMP0_3_PORT17;10:[!//
EMIOS0_E0UC_31_Y_IN_PORT17;11:[!//
FlexCAN_0_RX_PORT17;12:[!//
LIN_0_LIN0RX_PORT17;13:[!//
EMIOS0_E0UC_5_G_IN_PORT17;14:[!//
GLITCH_FILTER1_INP_PORT17;15:[!//
EMIOS0_E0UC_31_Y_IN_OUT_PORT17;17:[!//
EMIOS0_E0UC_5_G_IN_OUT_PORT17;18:[!//
LIN_0_LIN0TX_PORT18;1:[!//
IIC_0_SDA0_OUT_PORT18;2:[!//
EMIOS0_E0UC_30_Y_OUT_PORT18;3:[!//
EMIOS0_E0UC_30_Y_IN_PORT18;11:[!//
IIC_0_SDA0_IN_PORT18;12:[!//
GLITCH_FILTER1_INP_PORT18;13:[!//
IIC_0_SDA0_IN_OUT_PORT18;18:[!//
EMIOS0_E0UC_30_Y_IN_OUT_PORT18;19:[!//
EMIOS0_E0UC_31_Y_OUT_PORT19;1:[!//
IIC_0_SCL0_OUT_PORT19;2:[!//
EMIOS0_E0UC_8_X_OUT_PORT19;3:[!//
WKPU_WKPU_11_PORT19;9:[!//
EMIOS0_E0UC_31_Y_IN_PORT19;11:[!//
LIN_0_LIN0RX_PORT19;12:[!//
IIC_0_SCL0_IN_PORT19;13:[!//
EMIOS0_E0UC_8_X_IN_PORT19;14:[!//
GLITCH_FILTER1_INP_PORT19;15:[!//
EMIOS0_E0UC_31_Y_IN_OUT_PORT19;17:[!//
IIC_0_SCL0_IN_OUT_PORT19;18:[!//
EMIOS0_E0UC_8_X_IN_OUT_PORT19;19:[!//
ADC_1_ADC1_P_0_PORT20;10:[!//
ADC_1_ADC1_P_1_PORT21;10:[!//
ADC_1_ADC1_P_2_PORT22;10:[!//
ADC_1_ADC1_P_3_PORT23;10:[!//
ADC_0_ADC0_S_0_PORT24;10:[!//
WKPU_WKPU_25_PORT24;9:[!//
XOSC_OSC32K_XTAL_PORT24;9:[!//
ADC_0_ADC0_S_1_PORT25;10:[!//
WKPU_WKPU_26_PORT25;9:[!//
XOSC_OSC32K_EXTAL_PORT25;9:[!//
DSPI_1_dSOUT_PORT26;1:[!//
FlexCAN_3_TX_PORT26;2:[!//
CMP2_CMP2_O_PORT26;3:[!//
SAI0_SAI0_SYNC_OUT_PORT26;4:[!//
EMIOS0_E0UC_29_Y_OUT_PORT26;5:[!//
ADC_0_ADC0_S_2_PORT26;10:[!//
WKPU_WKPU_8_PORT26;9:[!//
FlexCAN_6_RX_PORT26;11:[!//
SAI0_SAI0_SYNC_IN_PORT26;12:[!//
EMIOS0_E0UC_29_Y_IN_PORT26;13:[!//
SAI0_SAI0_SYNC_IN_OUT_PORT26;20:[!//
EMIOS0_E0UC_29_Y_IN_OUT_PORT26;21:[!//
EMIOS0_E0UC_3_G_OUT_PORT27;1:[!//
DSPI_0_dCS0_PORT27;2:[!//
ADC_0_ADC0_S_3_PORT27;10:[!//
EMIOS0_E0UC_3_G_IN_PORT27;11:[!//
DSPI_0_dSS_PORT27;12:[!//
EMIOS0_E0UC_3_G_IN_OUT_PORT27;17:[!//
EMIOS0_E0UC_4_G_OUT_PORT28;1:[!//
DSPI_0_dCS1_PORT28;2:[!//
HSM_DO1_PORT28;3:[!//
ADC_0_ADC0_X_0_PORT28;10:[!//
EMIOS0_E0UC_4_G_IN_PORT28;11:[!//
EMIOS0_E0UC_4_G_IN_OUT_PORT28;17:[!//
EMIOS0_E0UC_5_G_OUT_PORT29;1:[!//
DSPI_0_dCS2_PORT29;2:[!//
ADC_0_ADC0_X_1_PORT29;10:[!//
EMIOS0_E0UC_5_G_IN_PORT29;11:[!//
EMIOS0_E0UC_5_G_IN_OUT_PORT29;17:[!//
EMIOS0_E0UC_6_G_OUT_PORT30;1:[!//
DSPI_0_dCS3_PORT30;2:[!//
FlexRay_FR_DBG_1_PORT30;3:[!//
ADC_0_ADC0_X_2_PORT30;10:[!//
EMIOS0_E0UC_6_G_IN_PORT30;11:[!//
EMIOS0_E0UC_6_G_IN_OUT_PORT30;17:[!//
EMIOS0_E0UC_7_G_OUT_PORT31;1:[!//
DSPI_0_dCS4_PORT31;2:[!//
ADC_0_ADC0_X_3_PORT31;10:[!//
EMIOS0_E0UC_7_G_IN_PORT31;11:[!//
EMIOS0_E0UC_7_G_IN_OUT_PORT31;17:[!//
DCI_TDI_PORT32;1:[!//
DCI_TDO_PORT33;1:[!//
DSPI_1_dSCLK_OUT_PORT34;1:[!//
FlexCAN_4_TX_PORT34;2:[!//
SSCM_SSCM_DBG_0_PORT34;4:[!//
SIUL2_EIRQ5_PORT34;11:[!//
DSPI_1_dSCLK_IN_PORT34;12:[!//
DSPI_1_dSCLK_IN_OUT_PORT34;17:[!//
DSPI_1_dCS0_PORT35;1:[!//
ADC_0_ADC0_MA_0_PORT35;2:[!//
SSCM_SSCM_DBG_1_PORT35;4:[!//
SIUL2_EIRQ6_PORT35;11:[!//
FlexCAN_1_RX_PORT35;12:[!//
FlexCAN_4_RX_PORT35;13:[!//
DSPI_1_dSS_PORT35;14:[!//
EMIOS1_E1UC_31_Y_OUT_PORT36;1:[!//
FlexRay_FR_B_TX_EN_PORT36;2:[!//
SSCM_SSCM_DBG_2_PORT36;5:[!//
EMIOS1_E1UC_31_Y_IN_PORT36;11:[!//
SIUL2_EIRQ18_PORT36;12:[!//
FlexCAN_3_RX_PORT36;13:[!//
DSPI_1_dSIN_PORT36;14:[!//
GLITCH_FILTER3_INP_PORT36;15:[!//
EMIOS1_E1UC_31_Y_IN_OUT_PORT36;17:[!//
DSPI_1_dSOUT_PORT37;1:[!//
FlexCAN_3_TX_PORT37;2:[!//
FlexRay_FR_A_TX_PORT37;4:[!//
SSCM_SSCM_DBG_3_PORT37;7:[!//
SIUL2_EIRQ7_PORT37;11:[!//
LIN_1_LIN1TX_PORT38;1:[!//
EMIOS1_E1UC_28_Y_OUT_PORT38;2:[!//
SSCM_SSCM_DBG_4_PORT38;4:[!//
EMIOS0_E0UC_17_Y_OUT_PORT38;3:[!//
CMP0_CMP0_7_PORT38;10:[!//
EMIOS1_E1UC_28_Y_IN_PORT38;11:[!//
EMIOS0_E0UC_17_Y_IN_PORT38;12:[!//
GLITCH_FILTER2_INP_PORT38;13:[!//
EMIOS1_E1UC_28_Y_IN_OUT_PORT38;18:[!//
EMIOS0_E0UC_17_Y_IN_OUT_PORT38;19:[!//
EMIOS1_E1UC_29_Y_OUT_PORT39;1:[!//
CMP1_CMP1_O_PORT39;2:[!//
SSCM_SSCM_DBG_5_PORT39;4:[!//
EMIOS0_E0UC_18_Y_OUT_PORT39;3:[!//
WKPU_WKPU_12_PORT39;9:[!//
EMIOS1_E1UC_29_Y_IN_PORT39;11:[!//
LIN_1_LIN1RX_PORT39;12:[!//
EMIOS0_E0UC_18_Y_IN_PORT39;13:[!//
GLITCH_FILTER2_INP_PORT39;14:[!//
EMIOS1_E1UC_29_Y_IN_OUT_PORT39;17:[!//
EMIOS0_E0UC_18_Y_IN_OUT_PORT39;19:[!//
LIN_2_LIN2TX_PORT40;1:[!//
EMIOS0_E0UC_3_G_OUT_PORT40;2:[!//
SSCM_SSCM_DBG_6_PORT40;4:[!//
EMIOS0_E0UC_3_G_IN_PORT40;11:[!//
EMIOS0_E0UC_3_G_IN_OUT_PORT40;18:[!//
EMIOS0_E0UC_7_G_OUT_PORT41;1:[!//
SSCM_SSCM_DBG_7_PORT41;3:[!//
WKPU_WKPU_13_PORT41;9:[!//
EMIOS0_E0UC_7_G_IN_PORT41;11:[!//
LIN_2_LIN2RX_PORT41;12:[!//
EMIOS0_E0UC_7_G_IN_OUT_PORT41;17:[!//
FlexCAN_1_TX_PORT42;1:[!//
FlexCAN_4_TX_PORT42;2:[!//
ADC_0_ADC0_MA_1_PORT42;3:[!//
CMP0_CMP0_O_PORT42;4:[!//
LIN_6_LIN6TX_PORT42;6:[!//
ADC_0_ADC0_MA_2_PORT43;1:[!//
EMIOS0_E0UC_1_G_OUT_PORT43;2:[!//
WKPU_WKPU_5_PORT43;9:[!//
FlexCAN_1_RX_PORT43;11:[!//
FlexCAN_4_RX_PORT43;12:[!//
EMIOS0_E0UC_1_G_IN_PORT43;13:[!//
EMIOS0_E0UC_1_G_IN_OUT_PORT43;18:[!//
EMIOS0_E0UC_12_H_OUT_PORT44;1:[!//
FlexRay_FR_DBG_0_PORT44;2:[!//
EMIOS0_E0UC_12_H_IN_PORT44;11:[!//
SIUL2_EIRQ19_PORT44;12:[!//
DSPI_2_dSIN_PORT44;13:[!//
EMIOS0_E0UC_12_H_IN_OUT_PORT44;17:[!//
EMIOS0_E0UC_13_H_OUT_PORT45;1:[!//
DSPI_2_dSOUT_PORT45;2:[!//
FlexRay_FR_DBG_1_PORT45;3:[!//
EMIOS0_E0UC_13_H_IN_PORT45;11:[!//
EMIOS0_E0UC_13_H_IN_OUT_PORT45;17:[!//
EMIOS0_E0UC_14_H_OUT_PORT46;1:[!//
DSPI_2_dSCLK_OUT_PORT46;2:[!//
FlexRay_FR_DBG_2_PORT46;4:[!//
FlexCAN_4_TX_PORT46;5:[!//
EMIOS0_E0UC_14_H_IN_PORT46;11:[!//
SIUL2_EIRQ8_PORT46;12:[!//
DSPI_2_dSCLK_IN_PORT46;13:[!//
EMIOS0_E0UC_14_H_IN_OUT_PORT46;17:[!//
DSPI_2_dSCLK_IN_OUT_PORT46;18:[!//
EMIOS0_E0UC_15_H_OUT_PORT47;1:[!//
DSPI_2_dCS0_PORT47;2:[!//
FlexRay_FR_DBG_3_PORT47;4:[!//
EMIOS0_E0UC_15_H_IN_PORT47;11:[!//
SIUL2_EIRQ20_PORT47;12:[!//
DSPI_2_dSS_PORT47;13:[!//
FlexCAN_4_RX_PORT47;14:[!//
EMIOS0_E0UC_15_H_IN_OUT_PORT47;17:[!//
ADC_1_ADC1_P_4_PORT48;10:[!//
WKPU_WKPU_27_PORT48;9:[!//
ADC_1_ADC1_P_5_PORT49;10:[!//
WKPU_WKPU_28_PORT49;9:[!//
ADC_1_ADC1_P_6_PORT50;10:[!//
ADC_1_ADC1_P_7_PORT51;10:[!//
ADC_1_ADC1_P_8_PORT52;10:[!//
ADC_1_ADC1_P_9_PORT53;10:[!//
ADC_1_ADC1_P_10_PORT54;10:[!//
ADC_1_ADC1_P_11_PORT55;10:[!//
ADC_1_ADC1_P_12_PORT56;10:[!//
ADC_1_ADC1_P_13_PORT57;10:[!//
ADC_1_ADC1_P_14_PORT58;10:[!//
ADC_1_ADC1_P_15_PORT59;10:[!//
DSPI_0_dCS5_PORT60;1:[!//
EMIOS0_E0UC_24_X_OUT_PORT60;2:[!//
HSM_DO0_PORT60;3:[!//
ADC_0_ADC0_S_4_PORT60;10:[!//
EMIOS0_E0UC_24_X_IN_PORT60;11:[!//
EMIOS0_E0UC_24_X_IN_OUT_PORT60;18:[!//
DSPI_1_dCS0_PORT61;1:[!//
EMIOS0_E0UC_25_Y_OUT_PORT61;2:[!//
ENET0_ENET0_TMR0_OUT_PORT61;3:[!//
ADC_0_ADC0_S_5_PORT61;10:[!//
EMIOS0_E0UC_25_Y_IN_PORT61;11:[!//
DSPI_1_dSS_PORT61;12:[!//
ENET0_ENET0_TMR0_IN_PORT61;13:[!//
EMIOS0_E0UC_25_Y_IN_OUT_PORT61;18:[!//
ENET0_ENET0_TMR0_IN_OUT_PORT61;19:[!//
DSPI_1_dCS1_PORT62;1:[!//
EMIOS0_E0UC_26_Y_OUT_PORT62;2:[!//
FlexRay_FR_DBG_0_PORT62;3:[!//
ADC_0_ADC0_S_6_PORT62;10:[!//
EMIOS0_E0UC_26_Y_IN_PORT62;11:[!//
EMIOS0_E0UC_26_Y_IN_OUT_PORT62;18:[!//
DSPI_1_dCS2_PORT63;1:[!//
EMIOS0_E0UC_27_Y_OUT_PORT63;2:[!//
FlexRay_FR_DBG_1_PORT63;3:[!//
ADC_0_ADC0_S_7_PORT63;10:[!//
EMIOS0_E0UC_27_Y_IN_PORT63;11:[!//
EMIOS0_E0UC_27_Y_IN_OUT_PORT63;18:[!//
EMIOS0_E0UC_16_X_OUT_PORT64;1:[!//
IIC_1_SCL1_OUT_PORT64;2:[!//
WKPU_WKPU_6_PORT64;9:[!//
EMIOS0_E0UC_16_X_IN_PORT64;11:[!//
FlexCAN_5_RX_PORT64;12:[!//
LIN_11_LIN11RX_PORT64;13:[!//
IIC_1_SCL1_IN_PORT64;14:[!//
EMIOS0_E0UC_16_X_IN_OUT_PORT64;17:[!//
IIC_1_SCL1_IN_OUT_PORT64;18:[!//
EMIOS0_E0UC_17_Y_OUT_PORT65;1:[!//
FlexCAN_5_TX_PORT65;2:[!//
IIC_1_SDA1_OUT_PORT65;3:[!//
EMIOS0_E0UC_17_Y_IN_PORT65;11:[!//
IIC_1_SDA1_IN_PORT65;12:[!//
EMIOS0_E0UC_17_Y_IN_OUT_PORT65;17:[!//
IIC_1_SDA1_IN_OUT_PORT65;19:[!//
EMIOS0_E0UC_18_Y_OUT_PORT66;1:[!//
FlexRay_FR_A_TX_EN_PORT66;2:[!//
EMIOS0_E0UC_18_Y_IN_PORT66;11:[!//
SIUL2_EIRQ21_PORT66;12:[!//
DSPI_1_dSIN_PORT66;13:[!//
EMIOS0_E0UC_18_Y_IN_OUT_PORT66;17:[!//
EMIOS0_E0UC_19_Y_OUT_PORT67;1:[!//
DSPI_1_dSOUT_PORT67;2:[!//
WKPU_WKPU_29_PORT67;9:[!//
EMIOS0_E0UC_19_Y_IN_PORT67;11:[!//
FlexRay_FR_A_RX_PORT67;12:[!//
EMIOS0_E0UC_19_Y_IN_OUT_PORT67;17:[!//
EMIOS0_E0UC_20_Y_OUT_PORT68;1:[!//
DSPI_1_dSCLK_OUT_PORT68;2:[!//
FlexRay_FR_B_TX_PORT68;3:[!//
EMIOS0_E0UC_20_Y_IN_PORT68;11:[!//
SIUL2_EIRQ9_PORT68;12:[!//
DSPI_1_dSCLK_IN_PORT68;13:[!//
EMIOS0_E0UC_20_Y_IN_OUT_PORT68;17:[!//
DSPI_1_dSCLK_IN_OUT_PORT68;18:[!//
EMIOS0_E0UC_21_Y_OUT_PORT69;1:[!//
DSPI_1_dCS0_PORT69;2:[!//
ADC_0_ADC0_MA_2_PORT69;3:[!//
WKPU_WKPU_30_PORT69;9:[!//
EMIOS0_E0UC_21_Y_IN_PORT69;11:[!//
FlexRay_FR_B_RX_PORT69;12:[!//
DSPI_1_dSS_PORT69;13:[!//
EMIOS0_E0UC_21_Y_IN_OUT_PORT69;17:[!//
EMIOS0_E0UC_22_X_OUT_PORT70;1:[!//
DSPI_0_dCS3_PORT70;2:[!//
ADC_0_ADC0_MA_1_PORT70;3:[!//
ADC_1_ADC1_MA_1_PORT70;4:[!//
EMIOS0_E0UC_22_X_IN_PORT70;11:[!//
SIUL2_EIRQ22_PORT70;12:[!//
EMIOS0_E0UC_22_X_IN_OUT_PORT70;17:[!//
EMIOS0_E0UC_23_X_OUT_PORT71;1:[!//
DSPI_0_dCS2_PORT71;2:[!//
ADC_0_ADC0_MA_0_PORT71;3:[!//
ADC_1_ADC1_MA_0_PORT71;4:[!//
EMIOS0_E0UC_23_X_IN_PORT71;11:[!//
SIUL2_EIRQ23_PORT71;12:[!//
EMIOS0_E0UC_23_X_IN_OUT_PORT71;17:[!//
FlexCAN_2_TX_PORT72;1:[!//
EMIOS0_E0UC_22_X_OUT_PORT72;2:[!//
FlexCAN_3_TX_PORT72;3:[!//
IIC_2_SDA2_OUT_PORT72;4:[!//
LIN_6_LIN6TX_PORT72;5:[!//
EMIOS0_E0UC_22_X_IN_PORT72;11:[!//
IIC_2_SDA2_IN_PORT72;12:[!//
EMIOS0_E0UC_22_X_IN_OUT_PORT72;18:[!//
IIC_2_SDA2_IN_OUT_PORT72;20:[!//
EMIOS0_E0UC_23_X_OUT_PORT73;1:[!//
IIC_2_SCL2_OUT_PORT73;2:[!//
WKPU_WKPU_7_PORT73;9:[!//
EMIOS0_E0UC_23_X_IN_PORT73;11:[!//
FlexCAN_2_RX_PORT73;12:[!//
FlexCAN_3_RX_PORT73;13:[!//
IIC_2_SCL2_IN_PORT73;14:[!//
EMIOS0_E0UC_23_X_IN_OUT_PORT73;17:[!//
IIC_2_SCL2_IN_OUT_PORT73;18:[!//
LIN_3_LIN3TX_PORT74;1:[!//
DSPI_1_dCS3_PORT74;2:[!//
EMIOS1_E1UC_30_Y_OUT_PORT74;3:[!//
IIC_3_SDA3_OUT_PORT74;4:[!//
EMIOS1_E1UC_30_Y_IN_PORT74;11:[!//
SIUL2_EIRQ10_PORT74;12:[!//
IIC_3_SDA3_IN_PORT74;13:[!//
GLITCH_FILTER3_INP_PORT74;14:[!//
EMIOS1_E1UC_30_Y_IN_OUT_PORT74;19:[!//
IIC_3_SDA3_IN_OUT_PORT74;20:[!//
EMIOS0_E0UC_24_X_OUT_PORT75;1:[!//
DSPI_1_dCS4_PORT75;2:[!//
CGM_CLKOUT1_PORT75;3:[!//
IIC_3_SCL3_OUT_PORT75;4:[!//
WKPU_WKPU_14_PORT75;9:[!//
EMIOS0_E0UC_24_X_IN_PORT75;11:[!//
LIN_3_LIN3RX_PORT75;12:[!//
IIC_3_SCL3_IN_PORT75;13:[!//
EMIOS0_E0UC_24_X_IN_OUT_PORT75;17:[!//
IIC_3_SCL3_IN_OUT_PORT75;20:[!//
EMIOS1_E1UC_19_Y_OUT_PORT76;1:[!//
ADC_1_ADC1_S_13_PORT76;10:[!//
EMIOS1_E1UC_19_Y_IN_PORT76;11:[!//
SIUL2_EIRQ11_PORT76;12:[!//
DSPI_2_dSIN_PORT76;13:[!//
ENET0_MII_0_CRS_PORT76;14:[!//
EMIOS1_E1UC_19_Y_IN_OUT_PORT76;17:[!//
DSPI_2_dSOUT_PORT77;1:[!//
EMIOS1_E1UC_20_Y_OUT_PORT77;2:[!//
ADC_1_ADC1_X_3_PORT77;10:[!//
EMIOS1_E1UC_20_Y_IN_PORT77;11:[!//
ENET0_MII_0_RXD_3_PORT77;12:[!//
EMIOS1_E1UC_20_Y_IN_OUT_PORT77;18:[!//
DSPI_2_dSCLK_OUT_PORT78;1:[!//
EMIOS1_E1UC_21_Y_OUT_PORT78;2:[!//
EMIOS1_E1UC_21_Y_IN_PORT78;11:[!//
SIUL2_EIRQ12_PORT78;12:[!//
DSPI_2_dSCLK_IN_PORT78;13:[!//
DSPI_2_dSCLK_IN_OUT_PORT78;17:[!//
EMIOS1_E1UC_21_Y_IN_OUT_PORT78;18:[!//
DSPI_2_dCS0_PORT79;1:[!//
EMIOS1_E1UC_22_X_OUT_PORT79;2:[!//
SPI_2_SCLK_2_OUT_PORT79;3:[!//
EMIOS1_E1UC_22_X_IN_PORT79;11:[!//
DSPI_2_dSS_PORT79;12:[!//
SPI_2_SCLK_2_IN_PORT79;13:[!//
EMIOS1_E1UC_22_X_IN_OUT_PORT79;18:[!//
SPI_2_SCLK_2_IN_OUT_PORT79;19:[!//
EMIOS0_E0UC_10_H_OUT_PORT80;1:[!//
DSPI_1_dCS3_PORT80;2:[!//
FlexCAN_6_TX_PORT80;4:[!//
ADC_0_ADC0_S_8_PORT80;10:[!//
CMP2_CMP2_16_PORT80;10:[!//
SAI0_SAI0_MCLK_OUT_PORT80;7:[!//
EMIOS0_E0UC_10_H_IN_PORT80;11:[!//
SAI0_SAI0_MCLK_IN_PORT80;12:[!//
EMIOS0_E0UC_10_H_IN_OUT_PORT80;17:[!//
SAI0_SAI0_MCLK_IN_OUT_PORT80;23:[!//
EMIOS0_E0UC_11_H_OUT_PORT81;1:[!//
DSPI_1_dCS4_PORT81;2:[!//
SPI_0_CS3_0_PORT81;3:[!//
SAI0_SAI0_BCLK_OUT_PORT81;4:[!//
ADC_0_ADC0_S_9_PORT81;10:[!//
CMP2_CMP2_17_PORT81;10:[!//
EMIOS0_E0UC_11_H_IN_PORT81;11:[!//
SAI0_SAI0_BCLK_IN_PORT81;12:[!//
EMIOS0_E0UC_11_H_IN_OUT_PORT81;17:[!//
SAI0_SAI0_BCLK_IN_OUT_PORT81;20:[!//
EMIOS0_E0UC_12_H_OUT_PORT82;1:[!//
DSPI_2_dCS0_PORT82;2:[!//
SAI0_SAI0_D3_OUT_PORT82;4:[!//
ADC_0_ADC0_S_10_PORT82;10:[!//
CMP2_CMP2_18_PORT82;10:[!//
EMIOS0_E0UC_12_H_IN_PORT82;11:[!//
DSPI_2_dSS_PORT82;12:[!//
SAI0_SAI0_D3_IN_PORT82;13:[!//
GLITCH_FILTER0_INP_PORT82;14:[!//
EMIOS0_E0UC_12_H_IN_OUT_PORT82;17:[!//
SAI0_SAI0_D3_IN_OUT_PORT82;20:[!//
EMIOS0_E0UC_13_H_OUT_PORT83;1:[!//
DSPI_2_dCS1_PORT83;2:[!//
SAI0_SAI0_D2_OUT_PORT83;4:[!//
ADC_0_ADC0_S_11_PORT83;10:[!//
CMP2_CMP2_19_PORT83;10:[!//
EMIOS0_E0UC_13_H_IN_PORT83;11:[!//
SAI0_SAI0_D2_IN_PORT83;12:[!//
GLITCH_FILTER1_INP_PORT83;13:[!//
EMIOS0_E0UC_13_H_IN_OUT_PORT83;17:[!//
SAI0_SAI0_D2_IN_OUT_PORT83;20:[!//
EMIOS0_E0UC_14_H_OUT_PORT84;1:[!//
DSPI_2_dCS2_PORT84;2:[!//
SAI0_SAI0_D1_OUT_PORT84;4:[!//
ADC_0_ADC0_S_12_PORT84;10:[!//
CMP2_CMP2_20_PORT84;10:[!//
EMIOS0_E0UC_14_H_IN_PORT84;11:[!//
SAI0_SAI0_D1_IN_PORT84;12:[!//
GLITCH_FILTER2_INP_PORT84;13:[!//
EMIOS0_E0UC_14_H_IN_OUT_PORT84;17:[!//
SAI0_SAI0_D1_IN_OUT_PORT84;20:[!//
EMIOS0_E0UC_22_X_OUT_PORT85;1:[!//
DSPI_2_dCS3_PORT85;2:[!//
SPI_0_CS2_0_PORT85;3:[!//
SAI0_SAI0_D0_OUT_PORT85;4:[!//
ADC_0_ADC0_S_13_PORT85;10:[!//
CMP2_CMP2_21_PORT85;10:[!//
EMIOS0_E0UC_22_X_IN_PORT85;11:[!//
SAI0_SAI0_D0_IN_PORT85;12:[!//
GLITCH_FILTER3_INP_PORT85;13:[!//
EMIOS0_E0UC_22_X_IN_OUT_PORT85;17:[!//
SAI0_SAI0_D0_IN_OUT_PORT85;20:[!//
EMIOS0_E0UC_23_X_OUT_PORT86;1:[!//
DSPI_1_dCS1_PORT86;2:[!//
SAI1_SAI1_SYNC_OUT_PORT86;4:[!//
EMIOS0_E0UC_30_Y_OUT_PORT86;5:[!//
ADC_0_ADC0_S_14_PORT86;10:[!//
CMP2_CMP2_22_PORT86;10:[!//
EMIOS0_E0UC_23_X_IN_PORT86;11:[!//
SAI1_SAI1_SYNC_IN_PORT86;12:[!//
EMIOS0_E0UC_30_Y_IN_PORT86;13:[!//
EMIOS0_E0UC_23_X_IN_OUT_PORT86;17:[!//
SAI1_SAI1_SYNC_IN_OUT_PORT86;20:[!//
EMIOS0_E0UC_30_Y_IN_OUT_PORT86;21:[!//
SPI_0_SCLK_0_OUT_PORT87;1:[!//
DSPI_1_dCS2_PORT87;2:[!//
ADC_0_ADC0_S_15_PORT87;10:[!//
CMP2_CMP2_23_PORT87;10:[!//
SAI1_SAI1_MCLK_OUT_PORT87;6:[!//
SPI_0_SCLK_0_IN_PORT87;11:[!//
SAI1_SAI1_MCLK_IN_PORT87;12:[!//
SPI_0_SCLK_0_IN_OUT_PORT87;17:[!//
SAI1_SAI1_MCLK_IN_OUT_PORT87;22:[!//
FlexCAN_3_TX_PORT88;1:[!//
DSPI_0_dCS4_PORT88;2:[!//
FlexCAN_2_TX_PORT88;3:[!//
EMIOS0_E0UC_15_H_OUT_PORT88;4:[!//
CMP0_CMP0_5_PORT88;10:[!//
EMIOS0_E0UC_15_H_IN_PORT88;11:[!//
EMIOS0_E0UC_15_H_IN_OUT_PORT88;20:[!//
EMIOS1_E1UC_1_H_OUT_PORT89;1:[!//
DSPI_0_dCS5_PORT89;2:[!//
EMIOS0_E0UC_14_H_OUT_PORT89;3:[!//
WKPU_WKPU_22_PORT89;9:[!//
CMP0_CMP0_4_PORT89;10:[!//
EMIOS1_E1UC_1_H_IN_PORT89;11:[!//
FlexCAN_2_RX_PORT89;12:[!//
FlexCAN_3_RX_PORT89;13:[!//
EMIOS0_E0UC_14_H_IN_PORT89;14:[!//
EMIOS1_E1UC_1_H_IN_OUT_PORT89;17:[!//
EMIOS0_E0UC_14_H_IN_OUT_PORT89;19:[!//
DSPI_0_dCS1_PORT90;1:[!//
LIN_4_LIN4TX_PORT90;2:[!//
EMIOS1_E1UC_2_H_OUT_PORT90;3:[!//
FCCU_EOUT0_OUT_PORT90;5:[!//
FCCU_EOUT0_IN_PORT90;9:[!//
FCCU_EOUT0_IN_OUT_PORT90;21:[!//
EMIOS0_E0UC_19_Y_OUT_PORT90;4:[!//
CMP1_CMP1_8_PORT90;10:[!//
EMIOS1_E1UC_2_H_IN_PORT90;11:[!//
EMIOS0_E0UC_19_Y_IN_PORT90;12:[!//
EMIOS1_E1UC_2_H_IN_OUT_PORT90;19:[!//
EMIOS0_E0UC_19_Y_IN_OUT_PORT90;20:[!//
DSPI_0_dCS2_PORT91;1:[!//
EMIOS1_E1UC_3_H_OUT_PORT91;2:[!//
EMIOS0_E0UC_20_Y_OUT_PORT91;3:[!//
WKPU_WKPU_15_PORT91;9:[!//
CMP1_CMP1_9_PORT91;10:[!//
EMIOS1_E1UC_3_H_IN_PORT91;11:[!//
LIN_4_LIN4RX_PORT91;12:[!//
EMIOS0_E0UC_20_Y_IN_PORT91;13:[!//
EMIOS1_E1UC_3_H_IN_OUT_PORT91;18:[!//
EMIOS0_E0UC_20_Y_IN_OUT_PORT91;19:[!//
EMIOS1_E1UC_25_Y_OUT_PORT92;1:[!//
LIN_5_LIN5TX_PORT92;2:[!//
FCCU_EOUT1_OUT_PORT92;4:[!//
FCCU_EOUT1_IN_PORT92;9:[!//
FCCU_EOUT1_IN_OUT_PORT92;20:[!//
EMIOS0_E0UC_16_X_OUT_PORT92;3:[!//
CMP0_CMP0_6_PORT92;10:[!//
EMIOS1_E1UC_25_Y_IN_PORT92;11:[!//
EMIOS0_E0UC_16_X_IN_PORT92;12:[!//
EMIOS1_E1UC_25_Y_IN_OUT_PORT92;17:[!//
EMIOS0_E0UC_16_X_IN_OUT_PORT92;19:[!//
EMIOS1_E1UC_26_Y_OUT_PORT93;1:[!//
EMIOS0_E0UC_22_X_OUT_PORT93;2:[!//
WKPU_WKPU_16_PORT93;9:[!//
CMP1_CMP1_11_PORT93;10:[!//
EMIOS1_E1UC_26_Y_IN_PORT93;11:[!//
LIN_5_LIN5RX_PORT93;12:[!//
EMIOS0_E0UC_22_X_IN_PORT93;13:[!//
EMIOS1_E1UC_26_Y_IN_OUT_PORT93;17:[!//
EMIOS0_E0UC_22_X_IN_OUT_PORT93;18:[!//
FlexCAN_4_TX_PORT94;1:[!//
EMIOS1_E1UC_27_Y_OUT_PORT94;2:[!//
FlexCAN_1_TX_PORT94;3:[!//
ENET0_MII_RMII_0_MDIO_OUT_PORT94;4:[!//
ADC_1_ADC1_X_2_PORT94;10:[!//
EMIOS1_E1UC_27_Y_IN_PORT94;11:[!//
ENET0_MII_RMII_0_MDIO_IN_PORT94;12:[!//
EMIOS1_E1UC_27_Y_IN_OUT_PORT94;18:[!//
ENET0_MII_RMII_0_MDIO_IN_OUT_PORT94;20:[!//
EMIOS1_E1UC_4_H_OUT_PORT95;1:[!//
ADC_1_ADC1_X_1_PORT95;10:[!//
EMIOS1_E1UC_4_H_IN_PORT95;11:[!//
SIUL2_EIRQ13_PORT95;12:[!//
FlexCAN_1_RX_PORT95;13:[!//
FlexCAN_4_RX_PORT95;14:[!//
ENET0_MII_RMII_0_RX_DV_PORT95;15:[!//
EMIOS1_E1UC_4_H_IN_OUT_PORT95;17:[!//
FlexCAN_5_TX_PORT96;1:[!//
EMIOS1_E1UC_23_X_OUT_PORT96;2:[!//
ENET0_MII_RMII_0_MDC_PORT96;3:[!//
ADC_1_ADC1_X_0_PORT96;10:[!//
EMIOS1_E1UC_23_X_IN_PORT96;11:[!//
EMIOS1_E1UC_23_X_IN_OUT_PORT96;18:[!//
EMIOS1_E1UC_24_X_OUT_PORT97;1:[!//
ENET0_MII_RMII_0_TX_CLK_OUT_PORT97;2:[!//
ADC_1_ADC1_S_7_PORT97;10:[!//
EMIOS1_E1UC_24_X_IN_PORT97;11:[!//
SIUL2_EIRQ14_PORT97;12:[!//
FlexCAN_5_RX_PORT97;13:[!//
ENET0_MII_RMII_0_TX_CLK_IN_PORT97;14:[!//
EMIOS1_E1UC_24_X_IN_OUT_PORT97;17:[!//
ENET0_MII_RMII_0_TX_CLK_IN_OUT_PORT97;18:[!//
EMIOS1_E1UC_11_H_OUT_PORT98;1:[!//
DSPI_3_dSOUT_PORT98;2:[!//
FlexCAN_7_TX_PORT98;3:[!//
LIN_11_LIN11TX_PORT98;4:[!//
EMIOS1_E1UC_11_H_IN_PORT98;11:[!//
EMIOS1_E1UC_11_H_IN_OUT_PORT98;17:[!//
EMIOS1_E1UC_12_H_OUT_PORT99;1:[!//
DSPI_3_dCS0_PORT99;2:[!//
WKPU_WKPU_17_PORT99;9:[!//
EMIOS1_E1UC_12_H_IN_PORT99;11:[!//
FlexCAN_7_RX_PORT99;12:[!//
DSPI_3_dSS_PORT99;13:[!//
EMIOS1_E1UC_12_H_IN_OUT_PORT99;17:[!//
EMIOS1_E1UC_13_H_OUT_PORT100;1:[!//
DSPI_3_dSCLK_OUT_PORT100;2:[!//
LIN_10_LIN10TX_PORT100;3:[!//
EMIOS1_E1UC_13_H_IN_PORT100;11:[!//
DSPI_3_dSCLK_IN_PORT100;12:[!//
EMIOS1_E1UC_13_H_IN_OUT_PORT100;17:[!//
DSPI_3_dSCLK_IN_OUT_PORT100;18:[!//
EMIOS1_E1UC_14_H_OUT_PORT101;1:[!//
EMIOS0_E0UC_2_G_OUT_PORT101;2:[!//
WKPU_WKPU_18_PORT101;9:[!//
EMIOS1_E1UC_14_H_IN_PORT101;11:[!//
LIN_10_LIN10RX_PORT101;12:[!//
DSPI_3_dSIN_PORT101;13:[!//
EMIOS0_E0UC_2_G_IN_PORT101;14:[!//
EMIOS1_E1UC_14_H_IN_OUT_PORT101;17:[!//
EMIOS0_E0UC_2_G_IN_OUT_PORT101;18:[!//
EMIOS1_E1UC_15_H_OUT_PORT102;1:[!//
LIN_6_LIN6TX_PORT102;2:[!//
CGM_CLKOUT1_PORT102;3:[!//
EMIOS0_E0UC_3_G_OUT_PORT102;4:[!//
CMP0_CMP0_1_PORT102;10:[!//
PMCDIG_EXTREGC_PORT102;8:[!//
EMIOS1_E1UC_15_H_IN_PORT102;11:[!//
EMIOS0_E0UC_3_G_IN_PORT102;12:[!//
EMIOS1_E1UC_15_H_IN_OUT_PORT102;17:[!//
EMIOS0_E0UC_3_G_IN_OUT_PORT102;20:[!//
EMIOS1_E1UC_16_X_OUT_PORT103;1:[!//
EMIOS1_E1UC_30_Y_OUT_PORT103;2:[!//
CGM_CLKOUT0_PORT103;3:[!//
WKPU_WKPU_20_PORT103;9:[!//
CMP0_CMP0_0_PORT103;10:[!//
EMIOS1_E1UC_16_X_IN_PORT103;11:[!//
EMIOS1_E1UC_30_Y_IN_PORT103;12:[!//
LIN_6_LIN6RX_PORT103;13:[!//
GLITCH_FILTER3_INP_PORT103;14:[!//
EMIOS1_E1UC_16_X_IN_OUT_PORT103;17:[!//
EMIOS1_E1UC_30_Y_IN_OUT_PORT103;18:[!//
EMIOS1_E1UC_17_Y_OUT_PORT104;1:[!//
LIN_7_LIN7TX_PORT104;2:[!//
DSPI_2_dCS0_PORT104;3:[!//
FlexCAN_7_TX_PORT104;4:[!//
EMIOS1_E1UC_17_Y_IN_PORT104;11:[!//
SIUL2_EIRQ15_PORT104;12:[!//
DSPI_2_dSS_PORT104;13:[!//
EMIOS1_E1UC_17_Y_IN_OUT_PORT104;17:[!//
EMIOS1_E1UC_18_Y_OUT_PORT105;1:[!//
DSPI_2_dSCLK_OUT_PORT105;2:[!//
EMIOS0_E0UC_0_X_OUT_PORT105;3:[!//
WKPU_WKPU_21_PORT105;9:[!//
EMIOS1_E1UC_18_Y_IN_PORT105;11:[!//
FlexCAN_7_RX_PORT105;12:[!//
LIN_7_LIN7RX_PORT105;13:[!//
DSPI_2_dSCLK_IN_PORT105;14:[!//
EMIOS0_E0UC_0_X_IN_PORT105;15:[!//
EMIOS1_E1UC_18_Y_IN_OUT_PORT105;17:[!//
DSPI_2_dSCLK_IN_OUT_PORT105;18:[!//
EMIOS0_E0UC_0_X_IN_OUT_PORT105;19:[!//
EMIOS0_E0UC_24_X_OUT_PORT106;1:[!//
EMIOS1_E1UC_31_Y_OUT_PORT106;2:[!//
EMIOS0_E0UC_24_X_IN_PORT106;11:[!//
EMIOS1_E1UC_31_Y_IN_PORT106;12:[!//
SPI_0_SIN_0_PORT106;13:[!//
GLITCH_FILTER3_INP_PORT106;14:[!//
EMIOS0_E0UC_24_X_IN_OUT_PORT106;17:[!//
EMIOS1_E1UC_31_Y_IN_OUT_PORT106;18:[!//
EMIOS0_E0UC_25_Y_OUT_PORT107;1:[!//
SPI_0_CS0_0_PORT107;2:[!//
SPI_2_CS0_2_PORT107;3:[!//
EMIOS0_E0UC_25_Y_IN_PORT107;11:[!//
SPI_0_SS_0_PORT107;12:[!//
SPI_2_SS_2_PORT107;13:[!//
EMIOS0_E0UC_25_Y_IN_OUT_PORT107;17:[!//
EMIOS0_E0UC_26_Y_OUT_PORT108;1:[!//
SPI_0_SOUT_0_PORT108;2:[!//
ENET0_MII_0_TXD_2_PORT108;4:[!//
ADC_1_ADC1_S_2_PORT108;10:[!//
EMIOS0_E0UC_26_Y_IN_PORT108;11:[!//
EMIOS0_E0UC_26_Y_IN_OUT_PORT108;17:[!//
EMIOS0_E0UC_27_Y_OUT_PORT109;1:[!//
SPI_0_SCLK_0_OUT_PORT109;2:[!//
ENET0_MII_0_TXD_3_PORT109;4:[!//
ADC_1_ADC1_S_1_PORT109;10:[!//
EMIOS0_E0UC_27_Y_IN_PORT109;11:[!//
SPI_0_SCLK_0_IN_PORT109;12:[!//
EMIOS0_E0UC_27_Y_IN_OUT_PORT109;17:[!//
SPI_0_SCLK_0_IN_OUT_PORT109;18:[!//
EMIOS1_E1UC_0_X_OUT_PORT110;1:[!//
LIN_8_LIN8TX_PORT110;2:[!//
EMIOS1_E1UC_0_X_IN_PORT110;11:[!//
SPI_2_SIN_2_PORT110;12:[!//
EMIOS1_E1UC_0_X_IN_OUT_PORT110;17:[!//
EMIOS1_E1UC_1_H_OUT_PORT111;1:[!//
SPI_2_SOUT_2_PORT111;2:[!//
EMIOS1_E1UC_1_H_IN_PORT111;11:[!//
LIN_8_LIN8RX_PORT111;12:[!//
EMIOS1_E1UC_1_H_IN_OUT_PORT111;17:[!//
EMIOS1_E1UC_2_H_OUT_PORT112;1:[!//
ENET0_MII_RMII_0_TXD_1_PORT112;3:[!//
ADC_1_ADC1_S_3_PORT112;10:[!//
EMIOS1_E1UC_2_H_IN_PORT112;11:[!//
DSPI_1_dSIN_PORT112;12:[!//
EMIOS1_E1UC_2_H_IN_OUT_PORT112;17:[!//
EMIOS1_E1UC_3_H_OUT_PORT113;1:[!//
DSPI_1_dSOUT_PORT113;2:[!//
ENET0_MII_RMII_0_TXD_0_PORT113;4:[!//
ADC_1_ADC1_S_4_PORT113;10:[!//
EMIOS1_E1UC_3_H_IN_PORT113;11:[!//
EMIOS1_E1UC_3_H_IN_OUT_PORT113;17:[!//
EMIOS1_E1UC_4_H_OUT_PORT114;1:[!//
DSPI_1_dSCLK_OUT_PORT114;2:[!//
ENET0_MII_RMII_0_TX_EN_PORT114;4:[!//
ADC_1_ADC1_S_5_PORT114;10:[!//
EMIOS1_E1UC_4_H_IN_PORT114;11:[!//
DSPI_1_dSCLK_IN_PORT114;12:[!//
EMIOS1_E1UC_4_H_IN_OUT_PORT114;17:[!//
DSPI_1_dSCLK_IN_OUT_PORT114;18:[!//
EMIOS1_E1UC_5_H_OUT_PORT115;1:[!//
DSPI_1_dCS0_PORT115;2:[!//
ENET0_MII_0_TX_ER_PORT115;3:[!//
ADC_1_ADC1_S_6_PORT115;10:[!//
EMIOS1_E1UC_5_H_IN_PORT115;11:[!//
DSPI_1_dSS_PORT115;12:[!//
EMIOS1_E1UC_5_H_IN_OUT_PORT115;17:[!//
EMIOS1_E1UC_6_H_OUT_PORT116;1:[!//
SPI_3_SOUT_3_PORT116;2:[!//
IIC_3_SCL3_OUT_PORT116;3:[!//
EMIOS1_E1UC_6_H_IN_PORT116;11:[!//
IIC_3_SCL3_IN_PORT116;12:[!//
EMIOS1_E1UC_6_H_IN_OUT_PORT116;17:[!//
IIC_3_SCL3_IN_OUT_PORT116;19:[!//
EMIOS1_E1UC_7_H_OUT_PORT117;1:[!//
IIC_3_SDA3_OUT_PORT117;2:[!//
EMIOS1_E1UC_7_H_IN_PORT117;11:[!//
IIC_3_SDA3_IN_PORT117;12:[!//
SPI_3_SIN_3_PORT117;13:[!//
EMIOS1_E1UC_7_H_IN_OUT_PORT117;17:[!//
IIC_3_SDA3_IN_OUT_PORT117;18:[!//
EMIOS1_E1UC_8_X_OUT_PORT118;1:[!//
SPI_3_SCLK_3_OUT_PORT118;2:[!//
ADC_0_ADC0_MA_2_PORT118;3:[!//
ADC_1_ADC1_MA_2_PORT118;4:[!//
EMIOS1_E1UC_8_X_IN_PORT118;11:[!//
SPI_3_SCLK_3_IN_PORT118;12:[!//
EMIOS1_E1UC_8_X_IN_OUT_PORT118;17:[!//
SPI_3_SCLK_3_IN_OUT_PORT118;18:[!//
EMIOS1_E1UC_9_H_OUT_PORT119;1:[!//
DSPI_2_dCS3_PORT119;2:[!//
ADC_0_ADC0_MA_1_PORT119;3:[!//
SPI_3_CS0_3_PORT119;4:[!//
ADC_1_ADC1_MA_1_PORT119;5:[!//
EMIOS1_E1UC_9_H_IN_PORT119;11:[!//
SPI_3_SS_3_PORT119;12:[!//
EMIOS1_E1UC_9_H_IN_OUT_PORT119;17:[!//
EMIOS1_E1UC_10_H_OUT_PORT120;1:[!//
DSPI_2_dCS2_PORT120;2:[!//
ADC_0_ADC0_MA_0_PORT120;3:[!//
ADC_1_ADC1_MA_0_PORT120;4:[!//
EMIOS1_E1UC_10_H_IN_PORT120;11:[!//
EMIOS1_E1UC_10_H_IN_OUT_PORT120;17:[!//
DCI_TCK_PORT121;1:[!//
DCI_TMS_OUT_PORT122;1:[!//
DCI_TMS_IN_PORT122;9:[!//
DCI_TMS_IN_OUT_PORT122;17:[!//
DSPI_3_dSOUT_PORT123;1:[!//
SPI_0_CS0_0_PORT123;2:[!//
EMIOS1_E1UC_5_H_OUT_PORT123;3:[!//
EMIOS1_E1UC_5_H_IN_PORT123;11:[!//
SPI_0_SS_0_PORT123;12:[!//
EMIOS1_E1UC_5_H_IN_OUT_PORT123;19:[!//
DSPI_3_dSCLK_OUT_PORT124;1:[!//
SPI_0_CS1_0_PORT124;2:[!//
EMIOS1_E1UC_25_Y_OUT_PORT124;3:[!//
EMIOS1_E1UC_25_Y_IN_PORT124;11:[!//
DSPI_3_dSCLK_IN_PORT124;12:[!//
DSPI_3_dSCLK_IN_OUT_PORT124;17:[!//
EMIOS1_E1UC_25_Y_IN_OUT_PORT124;19:[!//
SPI_0_SOUT_0_PORT125;1:[!//
DSPI_3_dCS0_PORT125;2:[!//
EMIOS1_E1UC_26_Y_OUT_PORT125;3:[!//
FCCU_EOUT1_OUT_PORT125;4:[!//
FCCU_EOUT1_IN_PORT125;9:[!//
FCCU_EOUT1_IN_OUT_PORT125;20:[!//
EMIOS1_E1UC_26_Y_IN_PORT125;11:[!//
DSPI_3_dSS_PORT125;12:[!//
EMIOS1_E1UC_26_Y_IN_OUT_PORT125;19:[!//
SPI_0_SCLK_0_OUT_PORT126;1:[!//
DSPI_3_dCS1_PORT126;2:[!//
EMIOS1_E1UC_27_Y_OUT_PORT126;3:[!//
EMIOS1_E1UC_27_Y_IN_PORT126;11:[!//
SPI_0_SCLK_0_IN_PORT126;12:[!//
FCCU_EIN_ERR_PORT126;13:[!//
SPI_0_SCLK_0_IN_OUT_PORT126;17:[!//
EMIOS1_E1UC_27_Y_IN_OUT_PORT126;19:[!//
SPI_1_SOUT_1_PORT127;1:[!//
EMIOS1_E1UC_17_Y_OUT_PORT127;3:[!//
FCCU_EOUT0_OUT_PORT127;4:[!//
FCCU_EOUT0_IN_PORT127;9:[!//
FCCU_EOUT0_IN_OUT_PORT127;20:[!//
EMIOS1_E1UC_17_Y_IN_PORT127;11:[!//
EMIOS1_E1UC_17_Y_IN_OUT_PORT127;19:[!//
EMIOS0_E0UC_28_Y_OUT_PORT128;1:[!//
LIN_8_LIN8TX_PORT128;2:[!//
IIC_1_SDA1_OUT_PORT128;3:[!//
EMIOS0_E0UC_28_Y_IN_PORT128;11:[!//
IIC_1_SDA1_IN_PORT128;12:[!//
GLITCH_FILTER0_INP_PORT128;13:[!//
EMIOS0_E0UC_28_Y_IN_OUT_PORT128;17:[!//
IIC_1_SDA1_IN_OUT_PORT128;19:[!//
EMIOS0_E0UC_29_Y_OUT_PORT129;1:[!//
IIC_1_SCL1_OUT_PORT129;2:[!//
WKPU_WKPU_24_PORT129;9:[!//
EMIOS0_E0UC_29_Y_IN_PORT129;11:[!//
LIN_8_LIN8RX_PORT129;12:[!//
IIC_1_SCL1_IN_PORT129;13:[!//
GLITCH_FILTER0_INP_PORT129;14:[!//
EMIOS0_E0UC_29_Y_IN_OUT_PORT129;17:[!//
IIC_1_SCL1_IN_OUT_PORT129;18:[!//
EMIOS0_E0UC_30_Y_OUT_PORT130;1:[!//
LIN_9_LIN9TX_PORT130;2:[!//
IIC_2_SDA2_OUT_PORT130;3:[!//
EMIOS0_E0UC_30_Y_IN_PORT130;11:[!//
IIC_2_SDA2_IN_PORT130;12:[!//
GLITCH_FILTER1_INP_PORT130;13:[!//
EMIOS0_E0UC_30_Y_IN_OUT_PORT130;17:[!//
IIC_2_SDA2_IN_OUT_PORT130;19:[!//
EMIOS0_E0UC_31_Y_OUT_PORT131;1:[!//
IIC_2_SCL2_OUT_PORT131;2:[!//
WKPU_WKPU_23_PORT131;9:[!//
EMIOS0_E0UC_31_Y_IN_PORT131;11:[!//
LIN_9_LIN9RX_PORT131;12:[!//
IIC_2_SCL2_IN_PORT131;13:[!//
GLITCH_FILTER1_INP_PORT131;14:[!//
EMIOS0_E0UC_31_Y_IN_OUT_PORT131;17:[!//
IIC_2_SCL2_IN_OUT_PORT131;18:[!//
EMIOS1_E1UC_28_Y_OUT_PORT132;1:[!//
SPI_0_SOUT_0_PORT132;2:[!//
EMIOS1_E1UC_28_Y_IN_PORT132;11:[!//
GLITCH_FILTER2_INP_PORT132;12:[!//
EMIOS1_E1UC_28_Y_IN_OUT_PORT132;17:[!//
EMIOS1_E1UC_29_Y_OUT_PORT133;1:[!//
SPI_0_SCLK_0_OUT_PORT133;2:[!//
SPI_1_CS2_1_PORT133;3:[!//
SPI_2_CS2_2_PORT133;4:[!//
EMIOS1_E1UC_29_Y_IN_PORT133;11:[!//
SPI_0_SCLK_0_IN_PORT133;12:[!//
GLITCH_FILTER2_INP_PORT133;13:[!//
EMIOS1_E1UC_29_Y_IN_OUT_PORT133;17:[!//
SPI_0_SCLK_0_IN_OUT_PORT133;18:[!//
EMIOS1_E1UC_30_Y_OUT_PORT134;1:[!//
SPI_0_CS0_0_PORT134;2:[!//
SPI_1_CS0_1_PORT134;3:[!//
SPI_2_CS0_2_PORT134;4:[!//
HSM_DO0_PORT134;5:[!//
EMIOS1_E1UC_30_Y_IN_PORT134;11:[!//
SPI_0_SS_0_PORT134;12:[!//
SPI_1_SS_1_PORT134;13:[!//
SPI_2_SS_2_PORT134;14:[!//
GLITCH_FILTER3_INP_PORT134;15:[!//
EMIOS1_E1UC_30_Y_IN_OUT_PORT134;17:[!//
EMIOS1_E1UC_31_Y_OUT_PORT135;1:[!//
SPI_0_CS1_0_PORT135;2:[!//
SPI_1_CS1_1_PORT135;3:[!//
SPI_2_CS1_2_PORT135;4:[!//
HSM_DO1_PORT135;5:[!//
EMIOS1_E1UC_31_Y_IN_PORT135;11:[!//
GLITCH_FILTER3_INP_PORT135;12:[!//
EMIOS1_E1UC_31_Y_IN_OUT_PORT135;17:[!//
ADC_0_ADC0_S_16_PORT136;10:[!//
ADC_0_ADC0_S_17_PORT137;10:[!//
ADC_0_ADC0_S_18_PORT138;10:[!//
ENET0_ENET0_TMR1_OUT_PORT139;2:[!//
ADC_0_ADC0_S_19_PORT139;10:[!//
DSPI_3_dSIN_PORT139;11:[!//
ENET0_ENET0_TMR1_IN_PORT139;12:[!//
ENET0_ENET0_TMR1_IN_OUT_PORT139;18:[!//
DSPI_3_dCS0_PORT140;1:[!//
DSPI_2_dCS0_PORT140;2:[!//
ADC_0_ADC0_S_20_PORT140;10:[!//
DSPI_2_dSS_PORT140;11:[!//
DSPI_3_dSS_PORT140;12:[!//
DSPI_3_dCS1_PORT141;1:[!//
DSPI_2_dCS1_PORT141;2:[!//
ADC_0_ADC0_S_21_PORT141;10:[!//
SAI2_SAI2_D0_OUT_PORT142;1:[!//
ADC_0_ADC0_S_22_PORT142;10:[!//
SPI_0_SIN_0_PORT142;11:[!//
SAI2_SAI2_D0_IN_PORT142;12:[!//
SAI2_SAI2_D0_IN_OUT_PORT142;17:[!//
SPI_0_CS0_0_PORT143;1:[!//
DSPI_2_dCS2_PORT143;2:[!//
SAI2_SAI2_MCLK_OUT_PORT143;3:[!//
ADC_0_ADC0_S_23_PORT143;10:[!//
SPI_0_SS_0_PORT143;11:[!//
SAI2_SAI2_MCLK_IN_PORT143;12:[!//
SAI2_SAI2_MCLK_IN_OUT_PORT143;19:[!//
SPI_0_CS1_0_PORT144;1:[!//
DSPI_2_dCS3_PORT144;2:[!//
SAI2_SAI2_SYNC_OUT_PORT144;3:[!//
ADC_0_ADC0_S_24_PORT144;10:[!//
SAI2_SAI2_SYNC_IN_PORT144;11:[!//
SAI2_SAI2_SYNC_IN_OUT_PORT144;19:[!//
SPI_0_SOUT_0_PORT145;1:[!//
SAI2_SAI2_BCLK_OUT_PORT145;2:[!//
ADC_0_ADC0_S_25_PORT145;10:[!//
SPI_1_SIN_1_PORT145;11:[!//
SAI2_SAI2_BCLK_IN_PORT145;12:[!//
SAI2_SAI2_BCLK_IN_OUT_PORT145;18:[!//
SPI_1_CS0_1_PORT146;1:[!//
SPI_2_CS0_2_PORT146;2:[!//
SPI_3_CS0_3_PORT146;3:[!//
SAI1_SAI1_D0_OUT_PORT146;4:[!//
ADC_0_ADC0_S_26_PORT146;10:[!//
SPI_1_SS_1_PORT146;11:[!//
SPI_2_SS_2_PORT146;12:[!//
SPI_3_SS_3_PORT146;13:[!//
SAI1_SAI1_D0_IN_PORT146;14:[!//
SAI1_SAI1_D0_IN_OUT_PORT146;20:[!//
SPI_1_CS1_1_PORT147;1:[!//
SPI_2_CS1_2_PORT147;2:[!//
SPI_3_CS1_3_PORT147;3:[!//
SAI1_SAI1_BCLK_OUT_PORT147;4:[!//
ADC_0_ADC0_S_27_PORT147;10:[!//
SAI1_SAI1_BCLK_IN_PORT147;11:[!//
SAI1_SAI1_BCLK_IN_OUT_PORT147;20:[!//
SPI_1_SCLK_1_OUT_PORT148;1:[!//
EMIOS1_E1UC_18_Y_OUT_PORT148;2:[!//
EMIOS1_E1UC_18_Y_IN_PORT148;11:[!//
SPI_1_SCLK_1_IN_PORT148;12:[!//
FCCU_EIN_ERR_PORT148;13:[!//
SPI_1_SCLK_1_IN_OUT_PORT148;17:[!//
EMIOS1_E1UC_18_Y_IN_OUT_PORT148;18:[!//
SAI2_SAI2_D0_OUT_PORT149;2:[!//
ADC_0_ADC0_S_28_PORT149;10:[!//
SAI2_SAI2_D0_IN_PORT149;11:[!//
SAI2_SAI2_D0_IN_OUT_PORT149;18:[!//
SAI2_SAI2_BCLK_OUT_PORT150;2:[!//
ADC_0_ADC0_S_29_PORT150;10:[!//
SAI2_SAI2_BCLK_IN_PORT150;11:[!//
SAI2_SAI2_BCLK_IN_OUT_PORT150;18:[!//
ADC_0_ADC0_S_30_PORT151;10:[!//
SAI2_SAI2_MCLK_OUT_PORT151;3:[!//
SAI2_SAI2_MCLK_IN_PORT151;11:[!//
SAI2_SAI2_MCLK_IN_OUT_PORT151;19:[!//
SAI2_SAI2_SYNC_OUT_PORT152;2:[!//
ADC_0_ADC0_S_31_PORT152;10:[!//
SAI2_SAI2_SYNC_IN_PORT152;11:[!//
SAI2_SAI2_SYNC_IN_OUT_PORT152;18:[!//
FlexCAN_4_TX_PORT153;2:[!//
EMIOS1_E1UC_17_Y_OUT_PORT153;3:[!//
EMIOS1_E1UC_17_Y_IN_PORT153;11:[!//
EMIOS1_E1UC_17_Y_IN_OUT_PORT153;19:[!//
EMIOS1_E1UC_16_X_OUT_PORT154;2:[!//
EMIOS1_E1UC_16_X_IN_PORT154;11:[!//
FlexCAN_4_RX_PORT154;12:[!//
EMIOS1_E1UC_16_X_IN_OUT_PORT154;18:[!//
FlexCAN_2_TX_PORT155;1:[!//
EMIOS1_E1UC_11_H_OUT_PORT155;2:[!//
EMIOS1_E1UC_11_H_IN_PORT155;11:[!//
EMIOS1_E1UC_11_H_IN_OUT_PORT155;18:[!//
EMIOS1_E1UC_10_H_OUT_PORT156;1:[!//
EMIOS1_E1UC_10_H_IN_PORT156;11:[!//
FlexCAN_2_RX_PORT156;12:[!//
EMIOS1_E1UC_10_H_IN_OUT_PORT156;17:[!//
SPI_3_CS1_3_PORT157;1:[!//
EMIOS1_E1UC_15_H_OUT_PORT157;3:[!//
WKPU_WKPU_31_PORT157;9:[!//
EMIOS1_E1UC_15_H_IN_PORT157;11:[!//
FlexCAN_1_RX_PORT157;12:[!//
FlexCAN_4_RX_PORT157;13:[!//
FlexCAN_6_RX_PORT157;14:[!//
EMIOS1_E1UC_15_H_IN_OUT_PORT157;19:[!//
FlexCAN_1_TX_PORT158;1:[!//
FlexCAN_4_TX_PORT158;2:[!//
SPI_3_CS2_3_PORT158;3:[!//
FlexCAN_6_TX_PORT158;4:[!//
EMIOS1_E1UC_14_H_OUT_PORT158;6:[!//
EMIOS1_E1UC_14_H_IN_PORT158;11:[!//
EMIOS1_E1UC_14_H_IN_OUT_PORT158;22:[!//
SPI_2_CS1_2_PORT159;1:[!//
EMIOS1_E1UC_13_H_OUT_PORT159;2:[!//
EMIOS1_E1UC_13_H_IN_PORT159;11:[!//
FlexCAN_1_RX_PORT159;12:[!//
FlexCAN_3_RX_PORT159;13:[!//
EMIOS1_E1UC_13_H_IN_OUT_PORT159;18:[!//
FlexCAN_1_TX_PORT160;1:[!//
SPI_2_CS2_2_PORT160;2:[!//
FlexCAN_3_TX_PORT160;3:[!//
EMIOS1_E1UC_12_H_OUT_PORT160;4:[!//
EMIOS1_E1UC_12_H_IN_PORT160;11:[!//
EMIOS1_E1UC_12_H_IN_OUT_PORT160;20:[!//
SPI_2_CS3_2_PORT161;1:[!//
EMIOS1_E1UC_1_H_OUT_PORT161;3:[!//
EMIOS0_E0UC_6_G_OUT_PORT161;2:[!//
EMIOS1_E1UC_1_H_IN_PORT161;11:[!//
FlexCAN_4_RX_PORT161;12:[!//
EMIOS0_E0UC_6_G_IN_PORT161;13:[!//
EMIOS1_E1UC_1_H_IN_OUT_PORT161;19:[!//
EMIOS0_E0UC_6_G_IN_OUT_PORT161;18:[!//
FlexCAN_4_TX_PORT162;1:[!//
EMIOS1_E1UC_2_H_OUT_PORT162;3:[!//
EMIOS1_E1UC_2_H_IN_PORT162;11:[!//
EMIOS1_E1UC_2_H_IN_OUT_PORT162;19:[!//
EMIOS1_E1UC_0_X_OUT_PORT163;1:[!//
EMIOS1_E1UC_3_H_OUT_PORT163;3:[!//
EMIOS1_E1UC_0_X_IN_PORT163;11:[!//
EMIOS1_E1UC_3_H_IN_PORT163;12:[!//
SIUL2_EIRQ31_PORT163;13:[!//
FlexCAN_5_RX_PORT163;14:[!//
LIN_8_LIN8RX_PORT163;15:[!//
EMIOS1_E1UC_0_X_IN_OUT_PORT163;17:[!//
EMIOS1_E1UC_3_H_IN_OUT_PORT163;19:[!//
FlexCAN_5_TX_PORT164;1:[!//
LIN_8_LIN8TX_PORT164;2:[!//
EMIOS1_E1UC_1_H_OUT_PORT164;3:[!//
EMIOS0_E0UC_9_H_OUT_PORT164;4:[!//
EMIOS1_E1UC_1_H_IN_PORT164;11:[!//
EMIOS0_E0UC_9_H_IN_PORT164;12:[!//
EMIOS1_E1UC_1_H_IN_OUT_PORT164;19:[!//
EMIOS0_E0UC_9_H_IN_OUT_PORT164;20:[!//
EMIOS1_E1UC_4_H_OUT_PORT165;2:[!//
EMIOS0_E0UC_10_H_OUT_PORT165;1:[!//
EMIOS1_E1UC_4_H_IN_PORT165;11:[!//
FlexCAN_2_RX_PORT165;12:[!//
LIN_2_LIN2RX_PORT165;13:[!//
EMIOS0_E0UC_10_H_IN_PORT165;14:[!//
EMIOS1_E1UC_4_H_IN_OUT_PORT165;18:[!//
EMIOS0_E0UC_10_H_IN_OUT_PORT165;17:[!//
FlexCAN_2_TX_PORT166;1:[!//
LIN_2_LIN2TX_PORT166;2:[!//
EMIOS1_E1UC_5_H_OUT_PORT166;4:[!//
EMIOS0_E0UC_11_H_OUT_PORT166;3:[!//
EMIOS1_E1UC_5_H_IN_PORT166;11:[!//
EMIOS0_E0UC_11_H_IN_PORT166;12:[!//
EMIOS1_E1UC_5_H_IN_OUT_PORT166;20:[!//
EMIOS0_E0UC_11_H_IN_OUT_PORT166;19:[!//
EMIOS1_E1UC_6_H_OUT_PORT167;2:[!//
EMIOS0_E0UC_12_H_OUT_PORT167;1:[!//
EMIOS1_E1UC_6_H_IN_PORT167;11:[!//
FlexCAN_3_RX_PORT167;12:[!//
LIN_3_LIN3RX_PORT167;13:[!//
EMIOS0_E0UC_12_H_IN_PORT167;14:[!//
EMIOS1_E1UC_6_H_IN_OUT_PORT167;18:[!//
EMIOS0_E0UC_12_H_IN_OUT_PORT167;17:[!//
FlexCAN_3_TX_PORT168;1:[!//
LIN_3_LIN3TX_PORT168;2:[!//
EMIOS1_E1UC_7_H_OUT_PORT168;4:[!//
EMIOS0_E0UC_13_H_OUT_PORT168;3:[!//
EMIOS1_E1UC_7_H_IN_PORT168;11:[!//
EMIOS0_E0UC_13_H_IN_PORT168;12:[!//
EMIOS1_E1UC_7_H_IN_OUT_PORT168;20:[!//
EMIOS0_E0UC_13_H_IN_OUT_PORT168;19:[!//
EMIOS1_E1UC_29_Y_OUT_PORT169;1:[!//
EMIOS1_E1UC_29_Y_IN_PORT169;11:[!//
LIN_15_LIN15RX_PORT169;12:[!//
SPI_0_SIN_0_PORT169;13:[!//
GLITCH_FILTER2_INP_PORT169;14:[!//
EMIOS1_E1UC_29_Y_IN_OUT_PORT169;17:[!//
SPI_0_SOUT_0_PORT170;1:[!//
EMIOS1_E1UC_30_Y_OUT_PORT170;2:[!//
LIN_15_LIN15TX_PORT170;3:[!//
EMIOS1_E1UC_30_Y_IN_PORT170;11:[!//
GLITCH_FILTER3_INP_PORT170;12:[!//
EMIOS1_E1UC_30_Y_IN_OUT_PORT170;18:[!//
SPI_0_SCLK_0_OUT_PORT171;1:[!//
EMIOS1_E1UC_31_Y_OUT_PORT171;2:[!//
LIN_14_LIN14TX_PORT171;3:[!//
EMIOS1_E1UC_31_Y_IN_PORT171;11:[!//
SPI_0_SCLK_0_IN_PORT171;12:[!//
GLITCH_FILTER3_INP_PORT171;13:[!//
SPI_0_SCLK_0_IN_OUT_PORT171;17:[!//
EMIOS1_E1UC_31_Y_IN_OUT_PORT171;18:[!//
SPI_0_CS0_0_PORT172;1:[!//
EMIOS0_E0UC_0_X_OUT_PORT172;2:[!//
EMIOS0_E0UC_0_X_IN_PORT172;11:[!//
LIN_14_LIN14RX_PORT172;12:[!//
SPI_0_SS_0_PORT172;13:[!//
EMIOS0_E0UC_0_X_IN_OUT_PORT172;18:[!//
SPI_2_CS3_2_PORT173;1:[!//
SPI_3_CS2_3_PORT173;2:[!//
SPI_1_SCLK_1_OUT_PORT173;3:[!//
EMIOS0_E0UC_1_G_OUT_PORT173;4:[!//
EMIOS0_E0UC_1_G_IN_PORT173;11:[!//
FlexCAN_3_RX_PORT173;12:[!//
SPI_1_SCLK_1_IN_PORT173;13:[!//
SPI_1_SCLK_1_IN_OUT_PORT173;19:[!//
EMIOS0_E0UC_1_G_IN_OUT_PORT173;20:[!//
FlexCAN_3_TX_PORT174;1:[!//
SPI_3_CS3_3_PORT174;2:[!//
SPI_1_CS0_1_PORT174;3:[!//
EMIOS0_E0UC_2_G_OUT_PORT174;4:[!//
EMIOS0_E0UC_2_G_IN_PORT174;11:[!//
SPI_1_SS_1_PORT174;12:[!//
EMIOS0_E0UC_2_G_IN_OUT_PORT174;20:[!//
SPI_0_CS2_0_PORT175;1:[!//
EMIOS0_E0UC_3_G_OUT_PORT175;2:[!//
LIN_13_LIN13TX_PORT175;3:[!//
EMIOS0_E0UC_3_G_IN_PORT175;11:[!//
SPI_1_SIN_1_PORT175;12:[!//
SPI_3_SIN_3_PORT175;13:[!//
EMIOS0_E0UC_3_G_IN_OUT_PORT175;18:[!//
SPI_1_SOUT_1_PORT176;1:[!//
SPI_3_SOUT_3_PORT176;2:[!//
SPI_0_CS3_0_PORT176;3:[!//
EMIOS0_E0UC_4_G_OUT_PORT176;4:[!//
EMIOS0_E0UC_4_G_IN_PORT176;11:[!//
LIN_13_LIN13RX_PORT176;12:[!//
EMIOS0_E0UC_4_G_IN_OUT_PORT176;20:[!//
SAI0_SAI0_D0_OUT_PORT177;1:[!//
ADC_0_ADC0_S_47_PORT177;10:[!//
SAI0_SAI0_D0_IN_PORT177;11:[!//
SAI0_SAI0_D0_IN_OUT_PORT177;17:[!//
DCI_MDO_0_PORT178;1:[!//
DCI_MDO_1_PORT179;1:[!//
DCI_MDO_2_PORT180;1:[!//
DCI_MDO_3_PORT181;1:[!//
DCI_MDO_4_PORT182;1:[!//
DCI_MDO_5_PORT183;1:[!//
DCI_EVTI_PORT184;1:[!//
DCI_MSEO0_PORT185;1:[!//
DCI_MCKO_PORT186;1:[!//
DCI_MSEO1_PORT187;1:[!//
DCI_EVTO_PORT188;1:[!//
DCI_MDO_6_PORT189;1:[!//
DCI_MDO_7_PORT190;1:[!//
DCI_MDO_8_PORT191;1:[!//
DCI_MDO_9_PORT192;1:[!//
DCI_MDO_10_PORT193;1:[!//
DCI_MDO_11_PORT194;1:[!//
SAI0_SAI0_D1_OUT_PORT195;1:[!//
ENET0_ENET0_TMR2_OUT_PORT195;2:[!//
ADC_0_ADC0_S_46_PORT195;10:[!//
SAI0_SAI0_D1_IN_PORT195;11:[!//
ENET0_ENET0_TMR2_IN_PORT195;12:[!//
SAI0_SAI0_D1_IN_OUT_PORT195;17:[!//
ENET0_ENET0_TMR2_IN_OUT_PORT195;18:[!//
SAI0_SAI0_D2_OUT_PORT196;1:[!//
ADC_0_ADC0_S_45_PORT196;10:[!//
SAI0_SAI0_D2_IN_PORT196;11:[!//
SAI0_SAI0_D2_IN_OUT_PORT196;17:[!//
SAI0_SAI0_D3_OUT_PORT197;1:[!//
DCI_TCK_ALT_PORT197;2:[!//
ADC_0_ADC0_S_44_PORT197;10:[!//
SAI0_SAI0_D3_IN_PORT197;11:[!//
SAI0_SAI0_D3_IN_OUT_PORT197;17:[!//
DCI_TDI_ALT_PORT198;2:[!//
DCI_MDO_12_PORT199;1:[!//
DCI_MDO_13_PORT200;1:[!//
DCI_MDO_14_PORT201;1:[!//
DCI_MDO_15_PORT202;1:[!//
DCI_TDO_ALT_PORT205;2:[!//
SAI0_SAI0_MCLK_OUT_PORT206;1:[!//
DCI_TMS_ALT_OUT_PORT206;2:[!//
DCI_TMS_ALT_IN_PORT206;9:[!//
DCI_TMS_ALT_IN_OUT_PORT206;18:[!//
ADC_1_ADC1_S_15_PORT206;10:[!//
SAI0_SAI0_MCLK_IN_PORT206;11:[!//
SAI0_SAI0_MCLK_IN_OUT_PORT206;17:[!//
IIC_0_SDA0_OUT_PORT224;2:[!//
LIN_12_LIN12TX_PORT224;3:[!//
IIC_0_SDA0_IN_PORT224;11:[!//
IIC_0_SDA0_IN_OUT_PORT224;18:[!//
IIC_0_SCL0_OUT_PORT225;2:[!//
LIN_12_LIN12RX_PORT225;11:[!//
IIC_0_SCL0_IN_PORT225;12:[!//
IIC_0_SCL0_IN_OUT_PORT225;18:[!//
SPI_2_CS0_2_PORT252;1:[!//
DSPI_0_dCS4_PORT252;2:[!//
EMIOS1_E1UC_24_X_OUT_PORT252;3:[!//
EMIOS1_E1UC_24_X_IN_PORT252;11:[!//
SPI_2_SS_2_PORT252;12:[!//
EMIOS1_E1UC_24_X_IN_OUT_PORT252;19:[!//
SPI_2_SOUT_2_PORT253;1:[!//
EMIOS1_E1UC_23_X_OUT_PORT253;2:[!//
EMIOS1_E1UC_23_X_IN_PORT253;11:[!//
EMIOS1_E1UC_23_X_IN_OUT_PORT253;18:[!//
SPI_2_SCLK_2_OUT_PORT254;1:[!//
EMIOS1_E1UC_22_X_OUT_PORT254;2:[!//
EMIOS1_E1UC_22_X_IN_PORT254;11:[!//
SPI_2_SCLK_2_IN_PORT254;12:[!//
SPI_2_SCLK_2_IN_OUT_PORT254;17:[!//
EMIOS1_E1UC_22_X_IN_OUT_PORT254;18:[!//
EMIOS1_E1UC_21_Y_OUT_PORT255;1:[!//
EMIOS1_E1UC_21_Y_IN_PORT255;11:[!//
SPI_2_SIN_2_PORT255;12:[!//
EMIOS1_E1UC_21_Y_IN_OUT_PORT255;17:[!//
DSPI_0_dCS1_PORT256;1:[!//
DSPI_0_dCS0_PORT257;1:[!//
DSPI_0_dSS_PORT257;11:[!//
DSPI_0_dSCLK_OUT_PORT258;1:[!//
DSPI_0_dSCLK_IN_PORT258;11:[!//
DSPI_0_dSCLK_IN_OUT_PORT258;17:[!//
DSPI_0_dSIN_PORT259;11:[!//
DSPI_0_dSOUT_PORT260;1:[!//
EMIOS1_E1UC_28_Y_OUT_PORT260;2:[!//
EMIOS1_E1UC_28_Y_IN_PORT260;11:[!//
GLITCH_FILTER2_INP_PORT260;12:[!//
EMIOS1_E1UC_28_Y_IN_OUT_PORT260;18:[!//
SPI_2_CS3_2_PORT261;1:[!//
DSPI_0_dCS3_PORT261;2:[!//
EMIOS1_E1UC_27_Y_OUT_PORT261;3:[!//
EMIOS1_E1UC_27_Y_IN_PORT261;11:[!//
EMIOS1_E1UC_27_Y_IN_OUT_PORT261;19:[!//
SPI_2_CS2_2_PORT262;1:[!//
DSPI_0_dCS2_PORT262;2:[!//
EMIOS1_E1UC_26_Y_OUT_PORT262;3:[!//
EMIOS1_E1UC_26_Y_IN_PORT262;11:[!//
EMIOS1_E1UC_26_Y_IN_OUT_PORT262;19:[!//
SPI_2_CS1_2_PORT263;1:[!//
DSPI_0_dCS5_PORT263;2:[!//
EMIOS1_E1UC_25_Y_OUT_PORT263;3:[!//
EMIOS1_E1UC_25_Y_IN_PORT263;11:[!//
EMIOS1_E1UC_25_Y_IN_OUT_PORT263;19:[!//
[!ENDVAR!]

[!VAR "PinAbstractionModes_1"!]

#define    PORT0_GPIO        (PORT_GPIO_MODE)
#define    PORT0_EMIOS0_E0UC_0_X_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT0_CGM_CLKOUT0        (PORT_ALT2_FUNC_MODE)
#define    PORT0_EMIOS0_E0UC_13_H_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT0_WKPU_WKPU_19        (PORT_ONLY_INPUT_MODE)
#define    PORT0_EMIOS0_E0UC_0_X_IN        (PORT_INPUT1_MODE)
#define    PORT0_EMIOS0_E0UC_13_H_IN        (PORT_INPUT2_MODE)
#define    PORT0_EMIOS0_E0UC_0_X_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT0_EMIOS0_E0UC_13_H_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT0_FlexCAN_1_RX        (PORT_INPUT3_MODE)
#define    PORT1_GPIO        (PORT_GPIO_MODE)
#define    PORT1_EMIOS0_E0UC_1_G_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT1_WKPU_WKPU_2        (PORT_ONLY_INPUT_MODE)
#define    PORT1_WKPU_NMI_0        (PORT_ONLY_INPUT_MODE)
#define    PORT1_EMIOS0_E0UC_1_G_IN        (PORT_INPUT1_MODE)
#define    PORT1_FlexCAN_3_RX        (PORT_INPUT2_MODE)
#define    PORT1_EMIOS0_E0UC_1_G_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT2_GPIO        (PORT_GPIO_MODE)
#define    PORT2_EMIOS0_E0UC_2_G_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT2_ADC_0_ADC0_MA_2        (PORT_ALT3_FUNC_MODE)
#define    PORT2_WKPU_WKPU_3        (PORT_ONLY_INPUT_MODE)
#define    PORT2_EMIOS0_E0UC_2_G_IN        (PORT_INPUT1_MODE)
#define    PORT2_EMIOS0_E0UC_2_G_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT3_GPIO        (PORT_GPIO_MODE)
#define    PORT3_EMIOS0_E0UC_3_G_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT3_LIN_5_LIN5TX        (PORT_ALT2_FUNC_MODE)
#define    PORT3_DSPI_1_dCS4        (PORT_ALT3_FUNC_MODE)
#define    PORT3_ADC_1_ADC1_S_0        (PORT_ANALOG_INPUT_MODE)
#define    PORT3_EMIOS0_E0UC_3_G_IN        (PORT_INPUT1_MODE)
#define    PORT3_SIUL2_EIRQ0        (PORT_INPUT2_MODE)
#define    PORT3_ENET0_MII_0_RX_CLK        (PORT_INPUT3_MODE)
#define    PORT3_EMIOS0_E0UC_3_G_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT4_GPIO        (PORT_GPIO_MODE)
#define    PORT4_EMIOS0_E0UC_4_G_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT4_DSPI_1_dCS0        (PORT_ALT2_FUNC_MODE)
#define    PORT4_EMIOS0_E0UC_24_X_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT4_WKPU_WKPU_9        (PORT_ONLY_INPUT_MODE)
#define    PORT4_CMP1_CMP1_13        (PORT_ANALOG_INPUT_MODE)
#define    PORT4_EMIOS0_E0UC_4_G_IN        (PORT_INPUT1_MODE)
#define    PORT4_LIN_5_LIN5RX        (PORT_INPUT2_MODE)
#define    PORT4_DSPI_1_dSS        (PORT_INPUT3_MODE)
#define    PORT4_EMIOS0_E0UC_24_X_IN        (PORT_INPUT4_MODE)
#define    PORT4_EMIOS0_E0UC_4_G_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT4_EMIOS0_E0UC_24_X_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT5_GPIO        (PORT_GPIO_MODE)
#define    PORT5_EMIOS0_E0UC_5_G_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT5_LIN_4_LIN4TX        (PORT_ALT2_FUNC_MODE)
#define    PORT5_EMIOS0_E0UC_5_G_IN        (PORT_INPUT1_MODE)
#define    PORT5_EMIOS0_E0UC_5_G_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT6_GPIO        (PORT_GPIO_MODE)
#define    PORT6_EMIOS0_E0UC_6_G_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT6_DSPI_1_dCS1        (PORT_ALT2_FUNC_MODE)
#define    PORT6_EMIOS0_E0UC_6_G_IN        (PORT_INPUT1_MODE)
#define    PORT6_SIUL2_EIRQ1        (PORT_INPUT2_MODE)
#define    PORT6_LIN_4_LIN4RX        (PORT_INPUT3_MODE)
#define    PORT6_EMIOS0_E0UC_6_G_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT7_GPIO        (PORT_GPIO_MODE)
#define    PORT7_EMIOS0_E0UC_7_G_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT7_LIN_3_LIN3TX        (PORT_ALT2_FUNC_MODE)
#define    PORT7_ADC_1_ADC1_S_8        (PORT_ANALOG_INPUT_MODE)
#define    PORT7_EMIOS0_E0UC_7_G_IN        (PORT_INPUT1_MODE)
#define    PORT7_SIUL2_EIRQ2        (PORT_INPUT2_MODE)
#define    PORT7_ENET0_MII_0_RXD_2        (PORT_INPUT3_MODE)
#define    PORT7_EMIOS0_E0UC_7_G_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT8_GPIO        (PORT_GPIO_MODE)
#define    PORT8_EMIOS0_E0UC_8_X_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT8_EMIOS0_E0UC_14_H_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT8_ADC_1_ADC1_S_9        (PORT_ANALOG_INPUT_MODE)
#define    PORT8_EMIOS0_E0UC_8_X_IN        (PORT_INPUT1_MODE)
#define    PORT8_EMIOS0_E0UC_14_H_IN        (PORT_INPUT2_MODE)
#define    PORT8_SIUL2_EIRQ3        (PORT_INPUT3_MODE)
#define    PORT8_LIN_3_LIN3RX        (PORT_INPUT4_MODE)
#define    PORT8_ENET0_MII_RMII_0_RXD_1        (PORT_INPUT5_MODE)
#define    PORT8_EMIOS0_E0UC_8_X_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT8_EMIOS0_E0UC_14_H_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT9_GPIO        (PORT_GPIO_MODE)
#define    PORT9_EMIOS0_E0UC_9_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT9_DSPI_1_dCS2        (PORT_ALT2_FUNC_MODE)
#define    PORT9_ADC_1_ADC1_S_10        (PORT_ANALOG_INPUT_MODE)
#define    PORT9_EMIOS0_E0UC_9_H_IN        (PORT_INPUT1_MODE)
#define    PORT9_ENET0_MII_RMII_0_RXD_0        (PORT_INPUT2_MODE)
#define    PORT9_EMIOS0_E0UC_9_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT10_GPIO        (PORT_GPIO_MODE)
#define    PORT10_EMIOS0_E0UC_10_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT10_IIC_0_SDA0_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT10_LIN_2_LIN2TX        (PORT_ALT3_FUNC_MODE)
#define    PORT10_ADC_1_ADC1_S_11        (PORT_ANALOG_INPUT_MODE)
#define    PORT10_EMIOS0_E0UC_10_H_IN        (PORT_INPUT1_MODE)
#define    PORT10_IIC_0_SDA0_IN        (PORT_INPUT2_MODE)
#define    PORT10_DSPI_1_dSIN        (PORT_INPUT3_MODE)
#define    PORT10_ENET0_MII_0_COL        (PORT_INPUT4_MODE)
#define    PORT10_EMIOS0_E0UC_10_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT10_IIC_0_SDA0_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT11_GPIO        (PORT_GPIO_MODE)
#define    PORT11_EMIOS0_E0UC_11_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT11_IIC_0_SCL0_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT11_ADC_1_ADC1_S_12        (PORT_ANALOG_INPUT_MODE)
#define    PORT11_EMIOS0_E0UC_11_H_IN        (PORT_INPUT1_MODE)
#define    PORT11_SIUL2_EIRQ16        (PORT_INPUT2_MODE)
#define    PORT11_LIN_2_LIN2RX        (PORT_INPUT3_MODE)
#define    PORT11_IIC_0_SCL0_IN        (PORT_INPUT4_MODE)
#define    PORT11_ENET0_MII_RMII_0_RX_ER        (PORT_INPUT5_MODE)
#define    PORT11_EMIOS0_E0UC_11_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT11_IIC_0_SCL0_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT12_GPIO        (PORT_GPIO_MODE)
#define    PORT12_EMIOS0_E0UC_28_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT12_DSPI_1_dCS3        (PORT_ALT2_FUNC_MODE)
#define    PORT12_EMIOS0_E0UC_26_Y_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT12_CMP1_CMP1_15        (PORT_ANALOG_INPUT_MODE)
#define    PORT12_EMIOS0_E0UC_28_Y_IN        (PORT_INPUT1_MODE)
#define    PORT12_SIUL2_EIRQ17        (PORT_INPUT2_MODE)
#define    PORT12_DSPI_0_dSIN        (PORT_INPUT3_MODE)
#define    PORT12_EMIOS0_E0UC_26_Y_IN        (PORT_INPUT4_MODE)
#define    PORT12_GLITCH_FILTER0_INP        (PORT_INPUT5_MODE)
#define    PORT12_EMIOS0_E0UC_28_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT12_EMIOS0_E0UC_26_Y_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT13_GPIO        (PORT_GPIO_MODE)
#define    PORT13_DSPI_0_dSOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT13_EMIOS0_E0UC_29_Y_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT13_FlexCAN_0_TX        (PORT_ALT4_FUNC_MODE)
#define    PORT13_EMIOS0_E0UC_25_Y_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT13_CMP1_CMP1_14        (PORT_ANALOG_INPUT_MODE)
#define    PORT13_EMIOS0_E0UC_29_Y_IN        (PORT_INPUT1_MODE)
#define    PORT13_EMIOS0_E0UC_25_Y_IN        (PORT_INPUT2_MODE)
#define    PORT13_GLITCH_FILTER0_INP        (PORT_INPUT3_MODE)
#define    PORT13_EMIOS0_E0UC_29_Y_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT13_EMIOS0_E0UC_25_Y_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT14_GPIO        (PORT_GPIO_MODE)
#define    PORT14_DSPI_0_dSCLK_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT14_DSPI_0_dCS0        (PORT_ALT2_FUNC_MODE)
#define    PORT14_EMIOS0_E0UC_0_X_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT14_EMIOS0_E0UC_23_X_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT14_CMP1_CMP1_12        (PORT_ANALOG_INPUT_MODE)
#define    PORT14_EMIOS0_E0UC_0_X_IN        (PORT_INPUT1_MODE)
#define    PORT14_SIUL2_EIRQ4        (PORT_INPUT2_MODE)
#define    PORT14_DSPI_0_dSCLK_IN        (PORT_INPUT3_MODE)
#define    PORT14_DSPI_0_dSS        (PORT_INPUT4_MODE)
#define    PORT14_EMIOS0_E0UC_23_X_IN        (PORT_INPUT5_MODE)
#define    PORT14_DSPI_0_dSCLK_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT14_EMIOS0_E0UC_0_X_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT14_EMIOS0_E0UC_23_X_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT15_GPIO        (PORT_GPIO_MODE)
#define    PORT15_DSPI_0_dCS0        (PORT_ALT1_FUNC_MODE)
#define    PORT15_DSPI_0_dSCLK_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT15_EMIOS0_E0UC_1_G_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT15_EMIOS0_E0UC_21_Y_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT15_WKPU_WKPU_10        (PORT_ONLY_INPUT_MODE)
#define    PORT15_CMP1_CMP1_10        (PORT_ANALOG_INPUT_MODE)
#define    PORT15_EMIOS0_E0UC_1_G_IN        (PORT_INPUT1_MODE)
#define    PORT15_FlexCAN_0_RX        (PORT_INPUT2_MODE)
#define    PORT15_DSPI_0_dSCLK_IN        (PORT_INPUT3_MODE)
#define    PORT15_DSPI_0_dSS        (PORT_INPUT4_MODE)
#define    PORT15_EMIOS0_E0UC_21_Y_IN        (PORT_INPUT5_MODE)
#define    PORT15_DSPI_0_dSCLK_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT15_EMIOS0_E0UC_1_G_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT15_EMIOS0_E0UC_21_Y_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT16_GPIO        (PORT_GPIO_MODE)
#define    PORT16_FlexCAN_0_TX        (PORT_ALT1_FUNC_MODE)
#define    PORT16_EMIOS0_E0UC_30_Y_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT16_LIN_0_LIN0TX        (PORT_ALT3_FUNC_MODE)
#define    PORT16_EMIOS0_E0UC_4_G_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT16_CMP0_CMP0_2        (PORT_ANALOG_INPUT_MODE)
#define    PORT16_EMIOS0_E0UC_30_Y_IN        (PORT_INPUT1_MODE)
#define    PORT16_EMIOS0_E0UC_4_G_IN        (PORT_INPUT2_MODE)
#define    PORT16_GLITCH_FILTER1_INP        (PORT_INPUT3_MODE)
#define    PORT16_EMIOS0_E0UC_30_Y_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT16_EMIOS0_E0UC_4_G_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT17_GPIO        (PORT_GPIO_MODE)
#define    PORT17_EMIOS0_E0UC_31_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT17_EMIOS0_E0UC_5_G_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT17_WKPU_WKPU_4        (PORT_ONLY_INPUT_MODE)
#define    PORT17_CMP0_CMP0_3        (PORT_ANALOG_INPUT_MODE)
#define    PORT17_EMIOS0_E0UC_31_Y_IN        (PORT_INPUT1_MODE)
#define    PORT17_FlexCAN_0_RX        (PORT_INPUT2_MODE)
#define    PORT17_LIN_0_LIN0RX        (PORT_INPUT3_MODE)
#define    PORT17_EMIOS0_E0UC_5_G_IN        (PORT_INPUT4_MODE)
#define    PORT17_GLITCH_FILTER1_INP        (PORT_INPUT5_MODE)
#define    PORT17_EMIOS0_E0UC_31_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT17_EMIOS0_E0UC_5_G_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT26_GPIO        (PORT_GPIO_MODE)
#define    PORT26_DSPI_1_dSOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT26_FlexCAN_3_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT26_CMP2_CMP2_O        (PORT_ALT3_FUNC_MODE)
#define    PORT26_SAI0_SAI0_SYNC_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT26_EMIOS0_E0UC_29_Y_OUT        (PORT_ALT5_FUNC_MODE)
#define    PORT26_ADC_0_ADC0_S_2        (PORT_ANALOG_INPUT_MODE)
#define    PORT26_WKPU_WKPU_8        (PORT_ONLY_INPUT_MODE)
#define    PORT26_FlexCAN_6_RX        (PORT_INPUT1_MODE)
#define    PORT26_SAI0_SAI0_SYNC_IN        (PORT_INPUT2_MODE)
#define    PORT26_EMIOS0_E0UC_29_Y_IN        (PORT_INPUT3_MODE)
#define    PORT26_SAI0_SAI0_SYNC_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT26_EMIOS0_E0UC_29_Y_IN_OUT        (PORT_INOUT5_MODE)
#define    PORT32_GPIO        (PORT_GPIO_MODE)
#define    PORT32_DCI_TDI        (PORT_ALT1_FUNC_MODE)
#define    PORT33_GPIO        (PORT_GPIO_MODE)
#define    PORT33_DCI_TDO        (PORT_ALT1_FUNC_MODE)
#define    PORT37_GPIO        (PORT_GPIO_MODE)
#define    PORT37_DSPI_1_dSOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT37_FlexCAN_3_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT37_FlexRay_FR_A_TX        (PORT_ALT4_FUNC_MODE)
#define    PORT37_SSCM_SSCM_DBG_3        (PORT_ALT7_FUNC_MODE)
#define    PORT37_SIUL2_EIRQ7        (PORT_INPUT1_MODE)
#define    PORT42_GPIO        (PORT_GPIO_MODE)
#define    PORT42_FlexCAN_1_TX        (PORT_ALT1_FUNC_MODE)
#define    PORT42_FlexCAN_4_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT42_ADC_0_ADC0_MA_1        (PORT_ALT3_FUNC_MODE)
#define    PORT42_CMP0_CMP0_O        (PORT_ALT4_FUNC_MODE)
#define    PORT42_LIN_6_LIN6TX        (PORT_ALT6_FUNC_MODE)
#define    PORT43_GPIO        (PORT_GPIO_MODE)
#define    PORT43_ADC_0_ADC0_MA_2        (PORT_ALT1_FUNC_MODE)
#define    PORT43_EMIOS0_E0UC_1_G_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT43_WKPU_WKPU_5        (PORT_ONLY_INPUT_MODE)
#define    PORT43_FlexCAN_1_RX        (PORT_INPUT1_MODE)
#define    PORT43_FlexCAN_4_RX        (PORT_INPUT2_MODE)
#define    PORT43_EMIOS0_E0UC_1_G_IN        (PORT_INPUT3_MODE)
#define    PORT43_EMIOS0_E0UC_1_G_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT49_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT49_ADC_1_ADC1_P_5        (PORT_ANALOG_INPUT_MODE)
#define    PORT49_WKPU_WKPU_28        (PORT_ONLY_INPUT_MODE)
#define    PORT61_GPIO        (PORT_GPIO_MODE)
#define    PORT61_DSPI_1_dCS0        (PORT_ALT1_FUNC_MODE)
#define    PORT61_EMIOS0_E0UC_25_Y_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT61_ENET0_ENET0_TMR0_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT61_ADC_0_ADC0_S_5        (PORT_ANALOG_INPUT_MODE)
#define    PORT61_EMIOS0_E0UC_25_Y_IN        (PORT_INPUT1_MODE)
#define    PORT61_DSPI_1_dSS        (PORT_INPUT2_MODE)
#define    PORT61_ENET0_ENET0_TMR0_IN        (PORT_INPUT3_MODE)
#define    PORT61_EMIOS0_E0UC_25_Y_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT61_ENET0_ENET0_TMR0_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT66_GPIO        (PORT_GPIO_MODE)
#define    PORT66_EMIOS0_E0UC_18_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT66_FlexRay_FR_A_TX_EN        (PORT_ALT2_FUNC_MODE)
#define    PORT66_EMIOS0_E0UC_18_Y_IN        (PORT_INPUT1_MODE)
#define    PORT66_SIUL2_EIRQ21        (PORT_INPUT2_MODE)
#define    PORT66_DSPI_1_dSIN        (PORT_INPUT3_MODE)
#define    PORT66_EMIOS0_E0UC_18_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT67_GPIO        (PORT_GPIO_MODE)
#define    PORT67_EMIOS0_E0UC_19_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT67_DSPI_1_dSOUT        (PORT_ALT2_FUNC_MODE)
#define    PORT67_WKPU_WKPU_29        (PORT_ONLY_INPUT_MODE)
#define    PORT67_EMIOS0_E0UC_19_Y_IN        (PORT_INPUT1_MODE)
#define    PORT67_FlexRay_FR_A_RX        (PORT_INPUT2_MODE)
#define    PORT67_EMIOS0_E0UC_19_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT72_GPIO        (PORT_GPIO_MODE)
#define    PORT72_FlexCAN_2_TX        (PORT_ALT1_FUNC_MODE)
#define    PORT72_EMIOS0_E0UC_22_X_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT72_FlexCAN_3_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT72_IIC_2_SDA2_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT72_LIN_6_LIN6TX        (PORT_ALT5_FUNC_MODE)
#define    PORT72_EMIOS0_E0UC_22_X_IN        (PORT_INPUT1_MODE)
#define    PORT72_IIC_2_SDA2_IN        (PORT_INPUT2_MODE)
#define    PORT72_EMIOS0_E0UC_22_X_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT72_IIC_2_SDA2_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT73_GPIO        (PORT_GPIO_MODE)
#define    PORT73_EMIOS0_E0UC_23_X_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT73_IIC_2_SCL2_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT73_WKPU_WKPU_7        (PORT_ONLY_INPUT_MODE)
#define    PORT73_EMIOS0_E0UC_23_X_IN        (PORT_INPUT1_MODE)
#define    PORT73_FlexCAN_2_RX        (PORT_INPUT2_MODE)
#define    PORT73_FlexCAN_3_RX        (PORT_INPUT3_MODE)
#define    PORT73_IIC_2_SCL2_IN        (PORT_INPUT4_MODE)
#define    PORT73_EMIOS0_E0UC_23_X_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT73_IIC_2_SCL2_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT77_GPIO        (PORT_GPIO_MODE)
#define    PORT77_DSPI_2_dSOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT77_EMIOS1_E1UC_20_Y_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT77_ADC_1_ADC1_X_3        (PORT_ANALOG_INPUT_MODE)
#define    PORT77_EMIOS1_E1UC_20_Y_IN        (PORT_INPUT1_MODE)
#define    PORT77_ENET0_MII_0_RXD_3        (PORT_INPUT2_MODE)
#define    PORT77_EMIOS1_E1UC_20_Y_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT79_GPIO        (PORT_GPIO_MODE)
#define    PORT79_DSPI_2_dCS0        (PORT_ALT1_FUNC_MODE)
#define    PORT79_EMIOS1_E1UC_22_X_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT79_SPI_2_SCLK_2_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT79_EMIOS1_E1UC_22_X_IN        (PORT_INPUT1_MODE)
#define    PORT79_DSPI_2_dSS        (PORT_INPUT2_MODE)
#define    PORT79_SPI_2_SCLK_2_IN        (PORT_INPUT3_MODE)
#define    PORT79_EMIOS1_E1UC_22_X_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT79_SPI_2_SCLK_2_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT80_GPIO        (PORT_GPIO_MODE)
#define    PORT80_EMIOS0_E0UC_10_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT80_DSPI_1_dCS3        (PORT_ALT2_FUNC_MODE)
#define    PORT80_FlexCAN_6_TX        (PORT_ALT4_FUNC_MODE)
#define    PORT80_ADC_0_ADC0_S_8        (PORT_ANALOG_INPUT_MODE)
#define    PORT80_CMP2_CMP2_16        (PORT_ANALOG_INPUT_MODE)
#define    PORT80_SAI0_SAI0_MCLK_OUT        (PORT_ALT7_FUNC_MODE)
#define    PORT80_EMIOS0_E0UC_10_H_IN        (PORT_INPUT1_MODE)
#define    PORT80_SAI0_SAI0_MCLK_IN        (PORT_INPUT2_MODE)
#define    PORT80_EMIOS0_E0UC_10_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT80_SAI0_SAI0_MCLK_IN_OUT        (PORT_INOUT7_MODE)
#define    PORT85_GPIO        (PORT_GPIO_MODE)
#define    PORT85_EMIOS0_E0UC_22_X_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT85_DSPI_2_dCS3        (PORT_ALT2_FUNC_MODE)
#define    PORT85_SPI_0_CS2_0        (PORT_ALT3_FUNC_MODE)
#define    PORT85_SAI0_SAI0_D0_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT85_ADC_0_ADC0_S_13        (PORT_ANALOG_INPUT_MODE)
#define    PORT85_CMP2_CMP2_21        (PORT_ANALOG_INPUT_MODE)
#define    PORT85_EMIOS0_E0UC_22_X_IN        (PORT_INPUT1_MODE)
#define    PORT85_SAI0_SAI0_D0_IN        (PORT_INPUT2_MODE)
#define    PORT85_GLITCH_FILTER3_INP        (PORT_INPUT3_MODE)
#define    PORT85_EMIOS0_E0UC_22_X_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT85_SAI0_SAI0_D0_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT88_GPIO        (PORT_GPIO_MODE)
#define    PORT88_FlexCAN_3_TX        (PORT_ALT1_FUNC_MODE)
#define    PORT88_DSPI_0_dCS4        (PORT_ALT2_FUNC_MODE)
#define    PORT88_FlexCAN_2_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT88_EMIOS0_E0UC_15_H_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT88_CMP0_CMP0_5        (PORT_ANALOG_INPUT_MODE)
#define    PORT88_EMIOS0_E0UC_15_H_IN        (PORT_INPUT1_MODE)
#define    PORT88_EMIOS0_E0UC_15_H_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT89_GPIO        (PORT_GPIO_MODE)
#define    PORT89_EMIOS1_E1UC_1_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT89_DSPI_0_dCS5        (PORT_ALT2_FUNC_MODE)
#define    PORT89_EMIOS0_E0UC_14_H_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT89_WKPU_WKPU_22        (PORT_ONLY_INPUT_MODE)
#define    PORT89_CMP0_CMP0_4        (PORT_ANALOG_INPUT_MODE)
#define    PORT89_EMIOS1_E1UC_1_H_IN        (PORT_INPUT1_MODE)
#define    PORT89_FlexCAN_2_RX        (PORT_INPUT2_MODE)
#define    PORT89_FlexCAN_3_RX        (PORT_INPUT3_MODE)
#define    PORT89_EMIOS0_E0UC_14_H_IN        (PORT_INPUT4_MODE)
#define    PORT89_EMIOS1_E1UC_1_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT89_EMIOS0_E0UC_14_H_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT90_GPIO        (PORT_GPIO_MODE)
#define    PORT90_DSPI_0_dCS1        (PORT_ALT1_FUNC_MODE)
#define    PORT90_LIN_4_LIN4TX        (PORT_ALT2_FUNC_MODE)
#define    PORT90_EMIOS1_E1UC_2_H_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT90_FCCU_EOUT0_OUT        (PORT_ALT5_FUNC_MODE)
#define    PORT90_FCCU_EOUT0_IN        (PORT_ONLY_INPUT_MODE)
#define    PORT90_FCCU_EOUT0_IN_OUT        (PORT_INOUT5_MODE)
#define    PORT90_EMIOS0_E0UC_19_Y_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT90_CMP1_CMP1_8        (PORT_ANALOG_INPUT_MODE)
#define    PORT90_EMIOS1_E1UC_2_H_IN        (PORT_INPUT1_MODE)
#define    PORT90_EMIOS0_E0UC_19_Y_IN        (PORT_INPUT2_MODE)
#define    PORT90_EMIOS1_E1UC_2_H_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT90_EMIOS0_E0UC_19_Y_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT94_GPIO        (PORT_GPIO_MODE)
#define    PORT94_FlexCAN_4_TX        (PORT_ALT1_FUNC_MODE)
#define    PORT94_EMIOS1_E1UC_27_Y_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT94_FlexCAN_1_TX        (PORT_ALT3_FUNC_MODE)
/**
* @violates @ref PORT_CFG_H_REF_1 MISRA 2004 Rule 1.4, The compiler/linker shall be checked to
*  ensure that 31 character significance and case sensitivity are supported for external ids
*/
#define    PORT94_ENET0_MII_RMII_0_MDIO_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT94_ADC_1_ADC1_X_2        (PORT_ANALOG_INPUT_MODE)
#define    PORT94_EMIOS1_E1UC_27_Y_IN        (PORT_INPUT1_MODE)
#define    PORT94_ENET0_MII_RMII_0_MDIO_IN        (PORT_INPUT2_MODE)
#define    PORT94_EMIOS1_E1UC_27_Y_IN_OUT        (PORT_INOUT2_MODE)
/**
* @violates @ref PORT_CFG_H_REF_1 MISRA 2004 Rule 1.4, The compiler/linker shall be checked to
*  ensure that 31 character significance and case sensitivity are supported for external ids
*/
#define    PORT94_ENET0_MII_RMII_0_MDIO_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT95_GPIO        (PORT_GPIO_MODE)
#define    PORT95_EMIOS1_E1UC_4_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT95_ADC_1_ADC1_X_1        (PORT_ANALOG_INPUT_MODE)
#define    PORT95_EMIOS1_E1UC_4_H_IN        (PORT_INPUT1_MODE)
#define    PORT95_SIUL2_EIRQ13        (PORT_INPUT2_MODE)
#define    PORT95_FlexCAN_1_RX        (PORT_INPUT3_MODE)
#define    PORT95_FlexCAN_4_RX        (PORT_INPUT4_MODE)
#define    PORT95_ENET0_MII_RMII_0_RX_DV        (PORT_INPUT5_MODE)
#define    PORT95_EMIOS1_E1UC_4_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT96_GPIO        (PORT_GPIO_MODE)
#define    PORT96_FlexCAN_5_TX        (PORT_ALT1_FUNC_MODE)
#define    PORT96_EMIOS1_E1UC_23_X_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT96_ENET0_MII_RMII_0_MDC        (PORT_ALT3_FUNC_MODE)
#define    PORT96_ADC_1_ADC1_X_0        (PORT_ANALOG_INPUT_MODE)
#define    PORT96_EMIOS1_E1UC_23_X_IN        (PORT_INPUT1_MODE)
#define    PORT96_EMIOS1_E1UC_23_X_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT97_GPIO        (PORT_GPIO_MODE)
#define    PORT97_EMIOS1_E1UC_24_X_OUT        (PORT_ALT1_FUNC_MODE)
/**
* @violates @ref PORT_CFG_H_REF_1 MISRA 2004 Rule 1.4, The compiler/linker shall be checked to
*  ensure that 31 character significance and case sensitivity are supported for external ids
*/
#define    PORT97_ENET0_MII_RMII_0_TX_CLK_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT97_ADC_1_ADC1_S_7        (PORT_ANALOG_INPUT_MODE)
#define    PORT97_EMIOS1_E1UC_24_X_IN        (PORT_INPUT1_MODE)
#define    PORT97_SIUL2_EIRQ14        (PORT_INPUT2_MODE)
#define    PORT97_FlexCAN_5_RX        (PORT_INPUT3_MODE)
/**
* @violates @ref PORT_CFG_H_REF_1 MISRA 2004 Rule 1.4, The compiler/linker shall be checked to
*  ensure that 31 character significance and case sensitivity are supported for external ids
*/
#define    PORT97_ENET0_MII_RMII_0_TX_CLK_IN        (PORT_INPUT4_MODE)
#define    PORT97_EMIOS1_E1UC_24_X_IN_OUT        (PORT_INOUT1_MODE)
/**
* @violates @ref PORT_CFG_H_REF_1 MISRA 2004 Rule 1.4, The compiler/linker shall be checked to
*  ensure that 31 character significance and case sensitivity are supported for external ids
*/
#define    PORT97_ENET0_MII_RMII_0_TX_CLK_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT98_GPIO        (PORT_GPIO_MODE)
#define    PORT98_EMIOS1_E1UC_11_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT98_DSPI_3_dSOUT        (PORT_ALT2_FUNC_MODE)
#define    PORT98_FlexCAN_7_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT98_LIN_11_LIN11TX        (PORT_ALT4_FUNC_MODE)
#define    PORT98_EMIOS1_E1UC_11_H_IN        (PORT_INPUT1_MODE)
#define    PORT98_EMIOS1_E1UC_11_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT99_GPIO        (PORT_GPIO_MODE)
#define    PORT99_EMIOS1_E1UC_12_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT99_DSPI_3_dCS0        (PORT_ALT2_FUNC_MODE)
#define    PORT99_WKPU_WKPU_17        (PORT_ONLY_INPUT_MODE)
#define    PORT99_EMIOS1_E1UC_12_H_IN        (PORT_INPUT1_MODE)
#define    PORT99_FlexCAN_7_RX        (PORT_INPUT2_MODE)
#define    PORT99_DSPI_3_dSS        (PORT_INPUT3_MODE)
#define    PORT99_EMIOS1_E1UC_12_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT102_GPIO        (PORT_GPIO_MODE)
#define    PORT102_EMIOS1_E1UC_15_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT102_LIN_6_LIN6TX        (PORT_ALT2_FUNC_MODE)
#define    PORT102_CGM_CLKOUT1        (PORT_ALT3_FUNC_MODE)
#define    PORT102_EMIOS0_E0UC_3_G_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT102_CMP0_CMP0_1        (PORT_ANALOG_INPUT_MODE)
#define    PORT102_PMCDIG_EXTREGC        (PORT_ONLY_OUTPUT_MODE)
#define    PORT102_EMIOS1_E1UC_15_H_IN        (PORT_INPUT1_MODE)
#define    PORT102_EMIOS0_E0UC_3_G_IN        (PORT_INPUT2_MODE)
#define    PORT102_EMIOS1_E1UC_15_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT102_EMIOS0_E0UC_3_G_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT103_GPIO        (PORT_GPIO_MODE)
#define    PORT103_EMIOS1_E1UC_16_X_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT103_EMIOS1_E1UC_30_Y_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT103_CGM_CLKOUT0        (PORT_ALT3_FUNC_MODE)
#define    PORT103_WKPU_WKPU_20        (PORT_ONLY_INPUT_MODE)
#define    PORT103_CMP0_CMP0_0        (PORT_ANALOG_INPUT_MODE)
#define    PORT103_EMIOS1_E1UC_16_X_IN        (PORT_INPUT1_MODE)
#define    PORT103_EMIOS1_E1UC_30_Y_IN        (PORT_INPUT2_MODE)
#define    PORT103_LIN_6_LIN6RX        (PORT_INPUT3_MODE)
#define    PORT103_GLITCH_FILTER3_INP        (PORT_INPUT4_MODE)
#define    PORT103_EMIOS1_E1UC_16_X_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT103_EMIOS1_E1UC_30_Y_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT107_GPIO        (PORT_GPIO_MODE)
#define    PORT107_EMIOS0_E0UC_25_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT107_SPI_0_CS0_0        (PORT_ALT2_FUNC_MODE)
#define    PORT107_SPI_2_CS0_2        (PORT_ALT3_FUNC_MODE)
#define    PORT107_EMIOS0_E0UC_25_Y_IN        (PORT_INPUT1_MODE)
#define    PORT107_SPI_0_SS_0        (PORT_INPUT2_MODE)
#define    PORT107_SPI_2_SS_2        (PORT_INPUT3_MODE)
#define    PORT107_EMIOS0_E0UC_25_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT108_GPIO        (PORT_GPIO_MODE)
#define    PORT108_EMIOS0_E0UC_26_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT108_SPI_0_SOUT_0        (PORT_ALT2_FUNC_MODE)
#define    PORT108_ENET0_MII_0_TXD_2        (PORT_ALT4_FUNC_MODE)
#define    PORT108_ADC_1_ADC1_S_2        (PORT_ANALOG_INPUT_MODE)
#define    PORT108_EMIOS0_E0UC_26_Y_IN        (PORT_INPUT1_MODE)
#define    PORT108_EMIOS0_E0UC_26_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT109_GPIO        (PORT_GPIO_MODE)
#define    PORT109_EMIOS0_E0UC_27_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT109_SPI_0_SCLK_0_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT109_ENET0_MII_0_TXD_3        (PORT_ALT4_FUNC_MODE)
#define    PORT109_ADC_1_ADC1_S_1        (PORT_ANALOG_INPUT_MODE)
#define    PORT109_EMIOS0_E0UC_27_Y_IN        (PORT_INPUT1_MODE)
#define    PORT109_SPI_0_SCLK_0_IN        (PORT_INPUT2_MODE)
#define    PORT109_EMIOS0_E0UC_27_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT109_SPI_0_SCLK_0_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT110_GPIO        (PORT_GPIO_MODE)
#define    PORT110_EMIOS1_E1UC_0_X_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT110_LIN_8_LIN8TX        (PORT_ALT2_FUNC_MODE)
#define    PORT110_EMIOS1_E1UC_0_X_IN        (PORT_INPUT1_MODE)
#define    PORT110_SPI_2_SIN_2        (PORT_INPUT2_MODE)
#define    PORT110_EMIOS1_E1UC_0_X_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT111_GPIO        (PORT_GPIO_MODE)
#define    PORT111_EMIOS1_E1UC_1_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT111_SPI_2_SOUT_2        (PORT_ALT2_FUNC_MODE)
#define    PORT111_EMIOS1_E1UC_1_H_IN        (PORT_INPUT1_MODE)
#define    PORT111_LIN_8_LIN8RX        (PORT_INPUT2_MODE)
#define    PORT111_EMIOS1_E1UC_1_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT112_GPIO        (PORT_GPIO_MODE)
#define    PORT112_EMIOS1_E1UC_2_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT112_ENET0_MII_RMII_0_TXD_1        (PORT_ALT3_FUNC_MODE)
#define    PORT112_ADC_1_ADC1_S_3        (PORT_ANALOG_INPUT_MODE)
#define    PORT112_EMIOS1_E1UC_2_H_IN        (PORT_INPUT1_MODE)
#define    PORT112_DSPI_1_dSIN        (PORT_INPUT2_MODE)
#define    PORT112_EMIOS1_E1UC_2_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT113_GPIO        (PORT_GPIO_MODE)
#define    PORT113_EMIOS1_E1UC_3_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT113_DSPI_1_dSOUT        (PORT_ALT2_FUNC_MODE)
#define    PORT113_ENET0_MII_RMII_0_TXD_0        (PORT_ALT4_FUNC_MODE)
#define    PORT113_ADC_1_ADC1_S_4        (PORT_ANALOG_INPUT_MODE)
#define    PORT113_EMIOS1_E1UC_3_H_IN        (PORT_INPUT1_MODE)
#define    PORT113_EMIOS1_E1UC_3_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT114_GPIO        (PORT_GPIO_MODE)
#define    PORT114_EMIOS1_E1UC_4_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT114_DSPI_1_dSCLK_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT114_ENET0_MII_RMII_0_TX_EN        (PORT_ALT4_FUNC_MODE)
#define    PORT114_ADC_1_ADC1_S_5        (PORT_ANALOG_INPUT_MODE)
#define    PORT114_EMIOS1_E1UC_4_H_IN        (PORT_INPUT1_MODE)
#define    PORT114_DSPI_1_dSCLK_IN        (PORT_INPUT2_MODE)
#define    PORT114_EMIOS1_E1UC_4_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT114_DSPI_1_dSCLK_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT121_GPIO        (PORT_GPIO_MODE)
#define    PORT121_DCI_TCK        (PORT_ALT1_FUNC_MODE)
#define    PORT122_GPIO        (PORT_GPIO_MODE)
#define    PORT122_DCI_TMS_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT122_DCI_TMS_IN        (PORT_ONLY_INPUT_MODE)
#define    PORT122_DCI_TMS_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT124_GPIO        (PORT_GPIO_MODE)
#define    PORT124_DSPI_3_dSCLK_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT124_SPI_0_CS1_0        (PORT_ALT2_FUNC_MODE)
#define    PORT124_EMIOS1_E1UC_25_Y_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT124_EMIOS1_E1UC_25_Y_IN        (PORT_INPUT1_MODE)
#define    PORT124_DSPI_3_dSCLK_IN        (PORT_INPUT2_MODE)
#define    PORT124_DSPI_3_dSCLK_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT124_EMIOS1_E1UC_25_Y_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT128_GPIO        (PORT_GPIO_MODE)
#define    PORT128_EMIOS0_E0UC_28_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT128_LIN_8_LIN8TX        (PORT_ALT2_FUNC_MODE)
#define    PORT128_IIC_1_SDA1_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT128_EMIOS0_E0UC_28_Y_IN        (PORT_INPUT1_MODE)
#define    PORT128_IIC_1_SDA1_IN        (PORT_INPUT2_MODE)
#define    PORT128_GLITCH_FILTER0_INP        (PORT_INPUT3_MODE)
#define    PORT128_EMIOS0_E0UC_28_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT128_IIC_1_SDA1_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT129_GPIO        (PORT_GPIO_MODE)
#define    PORT129_EMIOS0_E0UC_29_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT129_IIC_1_SCL1_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT129_WKPU_WKPU_24        (PORT_ONLY_INPUT_MODE)
#define    PORT129_EMIOS0_E0UC_29_Y_IN        (PORT_INPUT1_MODE)
#define    PORT129_LIN_8_LIN8RX        (PORT_INPUT2_MODE)
#define    PORT129_IIC_1_SCL1_IN        (PORT_INPUT3_MODE)
#define    PORT129_GLITCH_FILTER0_INP        (PORT_INPUT4_MODE)
#define    PORT129_EMIOS0_E0UC_29_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT129_IIC_1_SCL1_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT130_GPIO        (PORT_GPIO_MODE)
#define    PORT130_EMIOS0_E0UC_30_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT130_LIN_9_LIN9TX        (PORT_ALT2_FUNC_MODE)
#define    PORT130_IIC_2_SDA2_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT130_EMIOS0_E0UC_30_Y_IN        (PORT_INPUT1_MODE)
#define    PORT130_IIC_2_SDA2_IN        (PORT_INPUT2_MODE)
#define    PORT130_GLITCH_FILTER1_INP        (PORT_INPUT3_MODE)
#define    PORT130_EMIOS0_E0UC_30_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT130_IIC_2_SDA2_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT131_GPIO        (PORT_GPIO_MODE)
#define    PORT131_EMIOS0_E0UC_31_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT131_IIC_2_SCL2_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT131_WKPU_WKPU_23        (PORT_ONLY_INPUT_MODE)
#define    PORT131_EMIOS0_E0UC_31_Y_IN        (PORT_INPUT1_MODE)
#define    PORT131_LIN_9_LIN9RX        (PORT_INPUT2_MODE)
#define    PORT131_IIC_2_SCL2_IN        (PORT_INPUT3_MODE)
#define    PORT131_GLITCH_FILTER1_INP        (PORT_INPUT4_MODE)
#define    PORT131_EMIOS0_E0UC_31_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT131_IIC_2_SCL2_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT142_GPIO        (PORT_GPIO_MODE)
#define    PORT142_SAI2_SAI2_D0_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT142_ADC_0_ADC0_S_22        (PORT_ANALOG_INPUT_MODE)
#define    PORT142_SPI_0_SIN_0        (PORT_INPUT1_MODE)
#define    PORT142_SAI2_SAI2_D0_IN        (PORT_INPUT2_MODE)
#define    PORT142_SAI2_SAI2_D0_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT144_GPIO        (PORT_GPIO_MODE)
#define    PORT144_SPI_0_CS1_0        (PORT_ALT1_FUNC_MODE)
#define    PORT144_DSPI_2_dCS3        (PORT_ALT2_FUNC_MODE)
#define    PORT144_SAI2_SAI2_SYNC_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT144_ADC_0_ADC0_S_24        (PORT_ANALOG_INPUT_MODE)
#define    PORT144_SAI2_SAI2_SYNC_IN        (PORT_INPUT1_MODE)
#define    PORT144_SAI2_SAI2_SYNC_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT145_GPIO        (PORT_GPIO_MODE)
#define    PORT145_SPI_0_SOUT_0        (PORT_ALT1_FUNC_MODE)
#define    PORT145_SAI2_SAI2_BCLK_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT145_ADC_0_ADC0_S_25        (PORT_ANALOG_INPUT_MODE)
#define    PORT145_SPI_1_SIN_1        (PORT_INPUT1_MODE)
#define    PORT145_SAI2_SAI2_BCLK_IN        (PORT_INPUT2_MODE)
#define    PORT145_SAI2_SAI2_BCLK_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT146_GPIO        (PORT_GPIO_MODE)
#define    PORT146_SPI_1_CS0_1        (PORT_ALT1_FUNC_MODE)
#define    PORT146_SPI_2_CS0_2        (PORT_ALT2_FUNC_MODE)
#define    PORT146_SPI_3_CS0_3        (PORT_ALT3_FUNC_MODE)
#define    PORT146_SAI1_SAI1_D0_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT146_ADC_0_ADC0_S_26        (PORT_ANALOG_INPUT_MODE)
#define    PORT146_SPI_1_SS_1        (PORT_INPUT1_MODE)
#define    PORT146_SPI_2_SS_2        (PORT_INPUT2_MODE)
#define    PORT146_SPI_3_SS_3        (PORT_INPUT3_MODE)
#define    PORT146_SAI1_SAI1_D0_IN        (PORT_INPUT4_MODE)
#define    PORT146_SAI1_SAI1_D0_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT157_GPIO        (PORT_GPIO_MODE)
#define    PORT157_SPI_3_CS1_3        (PORT_ALT1_FUNC_MODE)
#define    PORT157_EMIOS1_E1UC_15_H_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT157_WKPU_WKPU_31        (PORT_ONLY_INPUT_MODE)
#define    PORT157_EMIOS1_E1UC_15_H_IN        (PORT_INPUT1_MODE)
#define    PORT157_FlexCAN_1_RX        (PORT_INPUT2_MODE)
#define    PORT157_FlexCAN_4_RX        (PORT_INPUT3_MODE)
#define    PORT157_FlexCAN_6_RX        (PORT_INPUT4_MODE)
#define    PORT157_EMIOS1_E1UC_15_H_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT158_GPIO        (PORT_GPIO_MODE)
#define    PORT158_FlexCAN_1_TX        (PORT_ALT1_FUNC_MODE)
#define    PORT158_FlexCAN_4_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT158_SPI_3_CS2_3        (PORT_ALT3_FUNC_MODE)
#define    PORT158_FlexCAN_6_TX        (PORT_ALT4_FUNC_MODE)
#define    PORT158_EMIOS1_E1UC_14_H_OUT        (PORT_ALT6_FUNC_MODE)
#define    PORT158_EMIOS1_E1UC_14_H_IN        (PORT_INPUT1_MODE)
#define    PORT158_EMIOS1_E1UC_14_H_IN_OUT        (PORT_INOUT6_MODE)
[!ENDVAR!]




[!VAR "PinAbstractionModes_2"!]

#define    PORT0_GPIO        (PORT_GPIO_MODE)
#define    PORT0_EMIOS0_E0UC_0_X_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT0_CGM_CLKOUT0        (PORT_ALT2_FUNC_MODE)
#define    PORT0_EMIOS0_E0UC_13_H_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT0_WKPU_WKPU_19        (PORT_ONLY_INPUT_MODE)
#define    PORT0_EMIOS0_E0UC_0_X_IN        (PORT_INPUT1_MODE)
#define    PORT0_EMIOS0_E0UC_13_H_IN        (PORT_INPUT2_MODE)
#define    PORT0_EMIOS0_E0UC_0_X_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT0_EMIOS0_E0UC_13_H_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT0_FlexCAN_1_RX        (PORT_INPUT3_MODE)
#define    PORT1_GPIO        (PORT_GPIO_MODE)
#define    PORT1_EMIOS0_E0UC_1_G_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT1_WKPU_WKPU_2        (PORT_ONLY_INPUT_MODE)
#define    PORT1_WKPU_NMI_0        (PORT_ONLY_INPUT_MODE)
#define    PORT1_EMIOS0_E0UC_1_G_IN        (PORT_INPUT1_MODE)
#define    PORT1_FlexCAN_3_RX        (PORT_INPUT2_MODE)
#define    PORT1_EMIOS0_E0UC_1_G_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT2_GPIO        (PORT_GPIO_MODE)
#define    PORT2_EMIOS0_E0UC_2_G_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT2_ADC_0_ADC0_MA_2        (PORT_ALT3_FUNC_MODE)
#define    PORT2_WKPU_WKPU_3        (PORT_ONLY_INPUT_MODE)
#define    PORT2_EMIOS0_E0UC_2_G_IN        (PORT_INPUT1_MODE)
#define    PORT2_EMIOS0_E0UC_2_G_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT3_GPIO        (PORT_GPIO_MODE)
#define    PORT3_EMIOS0_E0UC_3_G_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT3_LIN_5_LIN5TX        (PORT_ALT2_FUNC_MODE)
#define    PORT3_DSPI_1_dCS4        (PORT_ALT3_FUNC_MODE)
#define    PORT3_ADC_1_ADC1_S_0        (PORT_ANALOG_INPUT_MODE)
#define    PORT3_EMIOS0_E0UC_3_G_IN        (PORT_INPUT1_MODE)
#define    PORT3_SIUL2_EIRQ0        (PORT_INPUT2_MODE)
#define    PORT3_ENET0_MII_0_RX_CLK        (PORT_INPUT3_MODE)
#define    PORT3_EMIOS0_E0UC_3_G_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT4_GPIO        (PORT_GPIO_MODE)
#define    PORT4_EMIOS0_E0UC_4_G_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT4_DSPI_1_dCS0        (PORT_ALT2_FUNC_MODE)
#define    PORT4_EMIOS0_E0UC_24_X_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT4_WKPU_WKPU_9        (PORT_ONLY_INPUT_MODE)
#define    PORT4_CMP1_CMP1_13        (PORT_ANALOG_INPUT_MODE)
#define    PORT4_EMIOS0_E0UC_4_G_IN        (PORT_INPUT1_MODE)
#define    PORT4_LIN_5_LIN5RX        (PORT_INPUT2_MODE)
#define    PORT4_DSPI_1_dSS        (PORT_INPUT3_MODE)
#define    PORT4_EMIOS0_E0UC_24_X_IN        (PORT_INPUT4_MODE)
#define    PORT4_EMIOS0_E0UC_4_G_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT4_EMIOS0_E0UC_24_X_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT5_GPIO        (PORT_GPIO_MODE)
#define    PORT5_EMIOS0_E0UC_5_G_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT5_LIN_4_LIN4TX        (PORT_ALT2_FUNC_MODE)
#define    PORT5_EMIOS0_E0UC_5_G_IN        (PORT_INPUT1_MODE)
#define    PORT5_EMIOS0_E0UC_5_G_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT6_GPIO        (PORT_GPIO_MODE)
#define    PORT6_EMIOS0_E0UC_6_G_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT6_DSPI_1_dCS1        (PORT_ALT2_FUNC_MODE)
#define    PORT6_EMIOS0_E0UC_6_G_IN        (PORT_INPUT1_MODE)
#define    PORT6_SIUL2_EIRQ1        (PORT_INPUT2_MODE)
#define    PORT6_LIN_4_LIN4RX        (PORT_INPUT3_MODE)
#define    PORT6_EMIOS0_E0UC_6_G_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT7_GPIO        (PORT_GPIO_MODE)
#define    PORT7_EMIOS0_E0UC_7_G_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT7_LIN_3_LIN3TX        (PORT_ALT2_FUNC_MODE)
#define    PORT7_ADC_1_ADC1_S_8        (PORT_ANALOG_INPUT_MODE)
#define    PORT7_EMIOS0_E0UC_7_G_IN        (PORT_INPUT1_MODE)
#define    PORT7_SIUL2_EIRQ2        (PORT_INPUT2_MODE)
#define    PORT7_ENET0_MII_0_RXD_2        (PORT_INPUT3_MODE)
#define    PORT7_EMIOS0_E0UC_7_G_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT8_GPIO        (PORT_GPIO_MODE)
#define    PORT8_EMIOS0_E0UC_8_X_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT8_EMIOS0_E0UC_14_H_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT8_ADC_1_ADC1_S_9        (PORT_ANALOG_INPUT_MODE)
#define    PORT8_EMIOS0_E0UC_8_X_IN        (PORT_INPUT1_MODE)
#define    PORT8_EMIOS0_E0UC_14_H_IN        (PORT_INPUT2_MODE)
#define    PORT8_SIUL2_EIRQ3        (PORT_INPUT3_MODE)
#define    PORT8_LIN_3_LIN3RX        (PORT_INPUT4_MODE)
#define    PORT8_ENET0_MII_RMII_0_RXD_1        (PORT_INPUT5_MODE)
#define    PORT8_EMIOS0_E0UC_8_X_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT8_EMIOS0_E0UC_14_H_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT9_GPIO        (PORT_GPIO_MODE)
#define    PORT9_EMIOS0_E0UC_9_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT9_DSPI_1_dCS2        (PORT_ALT2_FUNC_MODE)
#define    PORT9_ADC_1_ADC1_S_10        (PORT_ANALOG_INPUT_MODE)
#define    PORT9_EMIOS0_E0UC_9_H_IN        (PORT_INPUT1_MODE)
#define    PORT9_ENET0_MII_RMII_0_RXD_0        (PORT_INPUT2_MODE)
#define    PORT9_EMIOS0_E0UC_9_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT10_GPIO        (PORT_GPIO_MODE)
#define    PORT10_EMIOS0_E0UC_10_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT10_IIC_0_SDA0_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT10_LIN_2_LIN2TX        (PORT_ALT3_FUNC_MODE)
#define    PORT10_ADC_1_ADC1_S_11        (PORT_ANALOG_INPUT_MODE)
#define    PORT10_EMIOS0_E0UC_10_H_IN        (PORT_INPUT1_MODE)
#define    PORT10_IIC_0_SDA0_IN        (PORT_INPUT2_MODE)
#define    PORT10_DSPI_1_dSIN        (PORT_INPUT3_MODE)
#define    PORT10_ENET0_MII_0_COL        (PORT_INPUT4_MODE)
#define    PORT10_EMIOS0_E0UC_10_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT10_IIC_0_SDA0_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT11_GPIO        (PORT_GPIO_MODE)
#define    PORT11_EMIOS0_E0UC_11_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT11_IIC_0_SCL0_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT11_ADC_1_ADC1_S_12        (PORT_ANALOG_INPUT_MODE)
#define    PORT11_EMIOS0_E0UC_11_H_IN        (PORT_INPUT1_MODE)
#define    PORT11_SIUL2_EIRQ16        (PORT_INPUT2_MODE)
#define    PORT11_LIN_2_LIN2RX        (PORT_INPUT3_MODE)
#define    PORT11_IIC_0_SCL0_IN        (PORT_INPUT4_MODE)
#define    PORT11_ENET0_MII_RMII_0_RX_ER        (PORT_INPUT5_MODE)
#define    PORT11_EMIOS0_E0UC_11_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT11_IIC_0_SCL0_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT12_GPIO        (PORT_GPIO_MODE)
#define    PORT12_EMIOS0_E0UC_28_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT12_DSPI_1_dCS3        (PORT_ALT2_FUNC_MODE)
#define    PORT12_EMIOS0_E0UC_26_Y_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT12_CMP1_CMP1_15        (PORT_ANALOG_INPUT_MODE)
#define    PORT12_EMIOS0_E0UC_28_Y_IN        (PORT_INPUT1_MODE)
#define    PORT12_SIUL2_EIRQ17        (PORT_INPUT2_MODE)
#define    PORT12_DSPI_0_dSIN        (PORT_INPUT3_MODE)
#define    PORT12_EMIOS0_E0UC_26_Y_IN        (PORT_INPUT4_MODE)
#define    PORT12_GLITCH_FILTER0_INP        (PORT_INPUT5_MODE)
#define    PORT12_EMIOS0_E0UC_28_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT12_EMIOS0_E0UC_26_Y_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT13_GPIO        (PORT_GPIO_MODE)
#define    PORT13_DSPI_0_dSOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT13_EMIOS0_E0UC_29_Y_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT13_FlexCAN_0_TX        (PORT_ALT4_FUNC_MODE)
#define    PORT13_EMIOS0_E0UC_25_Y_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT13_CMP1_CMP1_14        (PORT_ANALOG_INPUT_MODE)
#define    PORT13_EMIOS0_E0UC_29_Y_IN        (PORT_INPUT1_MODE)
#define    PORT13_EMIOS0_E0UC_25_Y_IN        (PORT_INPUT2_MODE)
#define    PORT13_GLITCH_FILTER0_INP        (PORT_INPUT3_MODE)
#define    PORT13_EMIOS0_E0UC_29_Y_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT13_EMIOS0_E0UC_25_Y_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT14_GPIO        (PORT_GPIO_MODE)
#define    PORT14_DSPI_0_dSCLK_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT14_DSPI_0_dCS0        (PORT_ALT2_FUNC_MODE)
#define    PORT14_EMIOS0_E0UC_0_X_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT14_EMIOS0_E0UC_23_X_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT14_CMP1_CMP1_12        (PORT_ANALOG_INPUT_MODE)
#define    PORT14_EMIOS0_E0UC_0_X_IN        (PORT_INPUT1_MODE)
#define    PORT14_SIUL2_EIRQ4        (PORT_INPUT2_MODE)
#define    PORT14_DSPI_0_dSCLK_IN        (PORT_INPUT3_MODE)
#define    PORT14_DSPI_0_dSS        (PORT_INPUT4_MODE)
#define    PORT14_EMIOS0_E0UC_23_X_IN        (PORT_INPUT5_MODE)
#define    PORT14_DSPI_0_dSCLK_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT14_EMIOS0_E0UC_0_X_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT14_EMIOS0_E0UC_23_X_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT15_GPIO        (PORT_GPIO_MODE)
#define    PORT15_DSPI_0_dCS0        (PORT_ALT1_FUNC_MODE)
#define    PORT15_DSPI_0_dSCLK_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT15_EMIOS0_E0UC_1_G_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT15_EMIOS0_E0UC_21_Y_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT15_WKPU_WKPU_10        (PORT_ONLY_INPUT_MODE)
#define    PORT15_CMP1_CMP1_10        (PORT_ANALOG_INPUT_MODE)
#define    PORT15_EMIOS0_E0UC_1_G_IN        (PORT_INPUT1_MODE)
#define    PORT15_FlexCAN_0_RX        (PORT_INPUT2_MODE)
#define    PORT15_DSPI_0_dSCLK_IN        (PORT_INPUT3_MODE)
#define    PORT15_DSPI_0_dSS        (PORT_INPUT4_MODE)
#define    PORT15_EMIOS0_E0UC_21_Y_IN        (PORT_INPUT5_MODE)
#define    PORT15_DSPI_0_dSCLK_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT15_EMIOS0_E0UC_1_G_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT15_EMIOS0_E0UC_21_Y_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT16_GPIO        (PORT_GPIO_MODE)
#define    PORT16_FlexCAN_0_TX        (PORT_ALT1_FUNC_MODE)
#define    PORT16_EMIOS0_E0UC_30_Y_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT16_LIN_0_LIN0TX        (PORT_ALT3_FUNC_MODE)
#define    PORT16_EMIOS0_E0UC_4_G_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT16_CMP0_CMP0_2        (PORT_ANALOG_INPUT_MODE)
#define    PORT16_EMIOS0_E0UC_30_Y_IN        (PORT_INPUT1_MODE)
#define    PORT16_EMIOS0_E0UC_4_G_IN        (PORT_INPUT2_MODE)
#define    PORT16_GLITCH_FILTER1_INP        (PORT_INPUT3_MODE)
#define    PORT16_EMIOS0_E0UC_30_Y_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT16_EMIOS0_E0UC_4_G_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT17_GPIO        (PORT_GPIO_MODE)
#define    PORT17_EMIOS0_E0UC_31_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT17_EMIOS0_E0UC_5_G_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT17_WKPU_WKPU_4        (PORT_ONLY_INPUT_MODE)
#define    PORT17_CMP0_CMP0_3        (PORT_ANALOG_INPUT_MODE)
#define    PORT17_EMIOS0_E0UC_31_Y_IN        (PORT_INPUT1_MODE)
#define    PORT17_FlexCAN_0_RX        (PORT_INPUT2_MODE)
#define    PORT17_LIN_0_LIN0RX        (PORT_INPUT3_MODE)
#define    PORT17_EMIOS0_E0UC_5_G_IN        (PORT_INPUT4_MODE)
#define    PORT17_GLITCH_FILTER1_INP        (PORT_INPUT5_MODE)
#define    PORT17_EMIOS0_E0UC_31_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT17_EMIOS0_E0UC_5_G_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT18_GPIO        (PORT_GPIO_MODE)
#define    PORT18_LIN_0_LIN0TX        (PORT_ALT1_FUNC_MODE)
#define    PORT18_IIC_0_SDA0_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT18_EMIOS0_E0UC_30_Y_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT18_EMIOS0_E0UC_30_Y_IN        (PORT_INPUT1_MODE)
#define    PORT18_IIC_0_SDA0_IN        (PORT_INPUT2_MODE)
#define    PORT18_GLITCH_FILTER1_INP        (PORT_INPUT3_MODE)
#define    PORT18_IIC_0_SDA0_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT18_EMIOS0_E0UC_30_Y_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT19_GPIO        (PORT_GPIO_MODE)
#define    PORT19_EMIOS0_E0UC_31_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT19_IIC_0_SCL0_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT19_EMIOS0_E0UC_8_X_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT19_WKPU_WKPU_11        (PORT_ONLY_INPUT_MODE)
#define    PORT19_EMIOS0_E0UC_31_Y_IN        (PORT_INPUT1_MODE)
#define    PORT19_LIN_0_LIN0RX        (PORT_INPUT2_MODE)
#define    PORT19_IIC_0_SCL0_IN        (PORT_INPUT3_MODE)
#define    PORT19_EMIOS0_E0UC_8_X_IN        (PORT_INPUT4_MODE)
#define    PORT19_GLITCH_FILTER1_INP        (PORT_INPUT5_MODE)
#define    PORT19_EMIOS0_E0UC_31_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT19_IIC_0_SCL0_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT19_EMIOS0_E0UC_8_X_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT20_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT20_ADC_1_ADC1_P_0        (PORT_ANALOG_INPUT_MODE)
#define    PORT21_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT21_ADC_1_ADC1_P_1        (PORT_ANALOG_INPUT_MODE)
#define    PORT22_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT22_ADC_1_ADC1_P_2        (PORT_ANALOG_INPUT_MODE)
#define    PORT23_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT23_ADC_1_ADC1_P_3        (PORT_ANALOG_INPUT_MODE)
#define    PORT24_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT24_ADC_0_ADC0_S_0        (PORT_ANALOG_INPUT_MODE)
#define    PORT24_WKPU_WKPU_25        (PORT_ONLY_INPUT_MODE)
#define    PORT24_XOSC_OSC32K_XTAL        (PORT_ONLY_INPUT_MODE)
#define    PORT25_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT25_ADC_0_ADC0_S_1        (PORT_ANALOG_INPUT_MODE)
#define    PORT25_WKPU_WKPU_26        (PORT_ONLY_INPUT_MODE)
#define    PORT25_XOSC_OSC32K_EXTAL        (PORT_ONLY_INPUT_MODE)
#define    PORT26_GPIO        (PORT_GPIO_MODE)
#define    PORT26_DSPI_1_dSOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT26_FlexCAN_3_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT26_CMP2_CMP2_O        (PORT_ALT3_FUNC_MODE)
#define    PORT26_SAI0_SAI0_SYNC_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT26_EMIOS0_E0UC_29_Y_OUT        (PORT_ALT5_FUNC_MODE)
#define    PORT26_ADC_0_ADC0_S_2        (PORT_ANALOG_INPUT_MODE)
#define    PORT26_WKPU_WKPU_8        (PORT_ONLY_INPUT_MODE)
#define    PORT26_FlexCAN_6_RX        (PORT_INPUT1_MODE)
#define    PORT26_SAI0_SAI0_SYNC_IN        (PORT_INPUT2_MODE)
#define    PORT26_EMIOS0_E0UC_29_Y_IN        (PORT_INPUT3_MODE)
#define    PORT26_SAI0_SAI0_SYNC_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT26_EMIOS0_E0UC_29_Y_IN_OUT        (PORT_INOUT5_MODE)
#define    PORT27_GPIO        (PORT_GPIO_MODE)
#define    PORT27_EMIOS0_E0UC_3_G_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT27_DSPI_0_dCS0        (PORT_ALT2_FUNC_MODE)
#define    PORT27_ADC_0_ADC0_S_3        (PORT_ANALOG_INPUT_MODE)
#define    PORT27_EMIOS0_E0UC_3_G_IN        (PORT_INPUT1_MODE)
#define    PORT27_DSPI_0_dSS        (PORT_INPUT2_MODE)
#define    PORT27_EMIOS0_E0UC_3_G_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT28_GPIO        (PORT_GPIO_MODE)
#define    PORT28_EMIOS0_E0UC_4_G_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT28_DSPI_0_dCS1        (PORT_ALT2_FUNC_MODE)
#define    PORT28_HSM_DO1        (PORT_ALT3_FUNC_MODE)
#define    PORT28_ADC_0_ADC0_X_0        (PORT_ANALOG_INPUT_MODE)
#define    PORT28_EMIOS0_E0UC_4_G_IN        (PORT_INPUT1_MODE)
#define    PORT28_EMIOS0_E0UC_4_G_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT29_GPIO        (PORT_GPIO_MODE)
#define    PORT29_EMIOS0_E0UC_5_G_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT29_DSPI_0_dCS2        (PORT_ALT2_FUNC_MODE)
#define    PORT29_ADC_0_ADC0_X_1        (PORT_ANALOG_INPUT_MODE)
#define    PORT29_EMIOS0_E0UC_5_G_IN        (PORT_INPUT1_MODE)
#define    PORT29_EMIOS0_E0UC_5_G_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT30_GPIO        (PORT_GPIO_MODE)
#define    PORT30_EMIOS0_E0UC_6_G_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT30_DSPI_0_dCS3        (PORT_ALT2_FUNC_MODE)
#define    PORT30_FlexRay_FR_DBG_1        (PORT_ALT3_FUNC_MODE)
#define    PORT30_ADC_0_ADC0_X_2        (PORT_ANALOG_INPUT_MODE)
#define    PORT30_EMIOS0_E0UC_6_G_IN        (PORT_INPUT1_MODE)
#define    PORT30_EMIOS0_E0UC_6_G_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT31_GPIO        (PORT_GPIO_MODE)
#define    PORT31_EMIOS0_E0UC_7_G_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT31_DSPI_0_dCS4        (PORT_ALT2_FUNC_MODE)
#define    PORT31_ADC_0_ADC0_X_3        (PORT_ANALOG_INPUT_MODE)
#define    PORT31_EMIOS0_E0UC_7_G_IN        (PORT_INPUT1_MODE)
#define    PORT31_EMIOS0_E0UC_7_G_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT32_GPIO        (PORT_GPIO_MODE)
#define    PORT32_DCI_TDI        (PORT_ALT1_FUNC_MODE)
#define    PORT33_GPIO        (PORT_GPIO_MODE)
#define    PORT33_DCI_TDO        (PORT_ALT1_FUNC_MODE)
#define    PORT34_GPIO        (PORT_GPIO_MODE)
#define    PORT34_DSPI_1_dSCLK_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT34_FlexCAN_4_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT34_SSCM_SSCM_DBG_0        (PORT_ALT4_FUNC_MODE)
#define    PORT34_SIUL2_EIRQ5        (PORT_INPUT1_MODE)
#define    PORT34_DSPI_1_dSCLK_IN        (PORT_INPUT2_MODE)
#define    PORT34_DSPI_1_dSCLK_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT35_GPIO        (PORT_GPIO_MODE)
#define    PORT35_DSPI_1_dCS0        (PORT_ALT1_FUNC_MODE)
#define    PORT35_ADC_0_ADC0_MA_0        (PORT_ALT2_FUNC_MODE)
#define    PORT35_SSCM_SSCM_DBG_1        (PORT_ALT4_FUNC_MODE)
#define    PORT35_SIUL2_EIRQ6        (PORT_INPUT1_MODE)
#define    PORT35_FlexCAN_1_RX        (PORT_INPUT2_MODE)
#define    PORT35_FlexCAN_4_RX        (PORT_INPUT3_MODE)
#define    PORT35_DSPI_1_dSS        (PORT_INPUT4_MODE)
#define    PORT36_GPIO        (PORT_GPIO_MODE)
#define    PORT36_EMIOS1_E1UC_31_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT36_FlexRay_FR_B_TX_EN        (PORT_ALT2_FUNC_MODE)
#define    PORT36_SSCM_SSCM_DBG_2        (PORT_ALT5_FUNC_MODE)
#define    PORT36_EMIOS1_E1UC_31_Y_IN        (PORT_INPUT1_MODE)
#define    PORT36_SIUL2_EIRQ18        (PORT_INPUT2_MODE)
#define    PORT36_FlexCAN_3_RX        (PORT_INPUT3_MODE)
#define    PORT36_DSPI_1_dSIN        (PORT_INPUT4_MODE)
#define    PORT36_GLITCH_FILTER3_INP        (PORT_INPUT5_MODE)
#define    PORT36_EMIOS1_E1UC_31_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT37_GPIO        (PORT_GPIO_MODE)
#define    PORT37_DSPI_1_dSOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT37_FlexCAN_3_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT37_FlexRay_FR_A_TX        (PORT_ALT4_FUNC_MODE)
#define    PORT37_SSCM_SSCM_DBG_3        (PORT_ALT7_FUNC_MODE)
#define    PORT37_SIUL2_EIRQ7        (PORT_INPUT1_MODE)
#define    PORT38_GPIO        (PORT_GPIO_MODE)
#define    PORT38_LIN_1_LIN1TX        (PORT_ALT1_FUNC_MODE)
#define    PORT38_EMIOS1_E1UC_28_Y_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT38_SSCM_SSCM_DBG_4        (PORT_ALT4_FUNC_MODE)
#define    PORT38_EMIOS0_E0UC_17_Y_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT38_CMP0_CMP0_7        (PORT_ANALOG_INPUT_MODE)
#define    PORT38_EMIOS1_E1UC_28_Y_IN        (PORT_INPUT1_MODE)
#define    PORT38_EMIOS0_E0UC_17_Y_IN        (PORT_INPUT2_MODE)
#define    PORT38_GLITCH_FILTER2_INP        (PORT_INPUT3_MODE)
#define    PORT38_EMIOS1_E1UC_28_Y_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT38_EMIOS0_E0UC_17_Y_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT39_GPIO        (PORT_GPIO_MODE)
#define    PORT39_EMIOS1_E1UC_29_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT39_CMP1_CMP1_O        (PORT_ALT2_FUNC_MODE)
#define    PORT39_SSCM_SSCM_DBG_5        (PORT_ALT4_FUNC_MODE)
#define    PORT39_EMIOS0_E0UC_18_Y_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT39_WKPU_WKPU_12        (PORT_ONLY_INPUT_MODE)
#define    PORT39_EMIOS1_E1UC_29_Y_IN        (PORT_INPUT1_MODE)
#define    PORT39_LIN_1_LIN1RX        (PORT_INPUT2_MODE)
#define    PORT39_EMIOS0_E0UC_18_Y_IN        (PORT_INPUT3_MODE)
#define    PORT39_GLITCH_FILTER2_INP        (PORT_INPUT4_MODE)
#define    PORT39_EMIOS1_E1UC_29_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT39_EMIOS0_E0UC_18_Y_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT40_GPIO        (PORT_GPIO_MODE)
#define    PORT40_LIN_2_LIN2TX        (PORT_ALT1_FUNC_MODE)
#define    PORT40_EMIOS0_E0UC_3_G_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT40_SSCM_SSCM_DBG_6        (PORT_ALT4_FUNC_MODE)
#define    PORT40_EMIOS0_E0UC_3_G_IN        (PORT_INPUT1_MODE)
#define    PORT40_EMIOS0_E0UC_3_G_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT41_GPIO        (PORT_GPIO_MODE)
#define    PORT41_EMIOS0_E0UC_7_G_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT41_SSCM_SSCM_DBG_7        (PORT_ALT3_FUNC_MODE)
#define    PORT41_WKPU_WKPU_13        (PORT_ONLY_INPUT_MODE)
#define    PORT41_EMIOS0_E0UC_7_G_IN        (PORT_INPUT1_MODE)
#define    PORT41_LIN_2_LIN2RX        (PORT_INPUT2_MODE)
#define    PORT41_EMIOS0_E0UC_7_G_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT42_GPIO        (PORT_GPIO_MODE)
#define    PORT42_FlexCAN_1_TX        (PORT_ALT1_FUNC_MODE)
#define    PORT42_FlexCAN_4_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT42_ADC_0_ADC0_MA_1        (PORT_ALT3_FUNC_MODE)
#define    PORT42_CMP0_CMP0_O        (PORT_ALT4_FUNC_MODE)
#define    PORT42_LIN_6_LIN6TX        (PORT_ALT6_FUNC_MODE)
#define    PORT43_GPIO        (PORT_GPIO_MODE)
#define    PORT43_ADC_0_ADC0_MA_2        (PORT_ALT1_FUNC_MODE)
#define    PORT43_EMIOS0_E0UC_1_G_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT43_WKPU_WKPU_5        (PORT_ONLY_INPUT_MODE)
#define    PORT43_FlexCAN_1_RX        (PORT_INPUT1_MODE)
#define    PORT43_FlexCAN_4_RX        (PORT_INPUT2_MODE)
#define    PORT43_EMIOS0_E0UC_1_G_IN        (PORT_INPUT3_MODE)
#define    PORT43_EMIOS0_E0UC_1_G_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT44_GPIO        (PORT_GPIO_MODE)
#define    PORT44_EMIOS0_E0UC_12_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT44_FlexRay_FR_DBG_0        (PORT_ALT2_FUNC_MODE)
#define    PORT44_EMIOS0_E0UC_12_H_IN        (PORT_INPUT1_MODE)
#define    PORT44_SIUL2_EIRQ19        (PORT_INPUT2_MODE)
#define    PORT44_DSPI_2_dSIN        (PORT_INPUT3_MODE)
#define    PORT44_EMIOS0_E0UC_12_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT45_GPIO        (PORT_GPIO_MODE)
#define    PORT45_EMIOS0_E0UC_13_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT45_DSPI_2_dSOUT        (PORT_ALT2_FUNC_MODE)
#define    PORT45_FlexRay_FR_DBG_1        (PORT_ALT3_FUNC_MODE)
#define    PORT45_EMIOS0_E0UC_13_H_IN        (PORT_INPUT1_MODE)
#define    PORT45_EMIOS0_E0UC_13_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT46_GPIO        (PORT_GPIO_MODE)
#define    PORT46_EMIOS0_E0UC_14_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT46_DSPI_2_dSCLK_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT46_FlexRay_FR_DBG_2        (PORT_ALT4_FUNC_MODE)
#define    PORT46_FlexCAN_4_TX        (PORT_ALT5_FUNC_MODE)
#define    PORT46_EMIOS0_E0UC_14_H_IN        (PORT_INPUT1_MODE)
#define    PORT46_SIUL2_EIRQ8        (PORT_INPUT2_MODE)
#define    PORT46_DSPI_2_dSCLK_IN        (PORT_INPUT3_MODE)
#define    PORT46_EMIOS0_E0UC_14_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT46_DSPI_2_dSCLK_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT47_GPIO        (PORT_GPIO_MODE)
#define    PORT47_EMIOS0_E0UC_15_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT47_DSPI_2_dCS0        (PORT_ALT2_FUNC_MODE)
#define    PORT47_FlexRay_FR_DBG_3        (PORT_ALT4_FUNC_MODE)
#define    PORT47_EMIOS0_E0UC_15_H_IN        (PORT_INPUT1_MODE)
#define    PORT47_SIUL2_EIRQ20        (PORT_INPUT2_MODE)
#define    PORT47_DSPI_2_dSS        (PORT_INPUT3_MODE)
#define    PORT47_FlexCAN_4_RX        (PORT_INPUT4_MODE)
#define    PORT47_EMIOS0_E0UC_15_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT48_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT48_ADC_1_ADC1_P_4        (PORT_ANALOG_INPUT_MODE)
#define    PORT48_WKPU_WKPU_27        (PORT_ONLY_INPUT_MODE)
#define    PORT49_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT49_ADC_1_ADC1_P_5        (PORT_ANALOG_INPUT_MODE)
#define    PORT49_WKPU_WKPU_28        (PORT_ONLY_INPUT_MODE)
#define    PORT50_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT50_ADC_1_ADC1_P_6        (PORT_ANALOG_INPUT_MODE)
#define    PORT51_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT51_ADC_1_ADC1_P_7        (PORT_ANALOG_INPUT_MODE)
#define    PORT52_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT52_ADC_1_ADC1_P_8        (PORT_ANALOG_INPUT_MODE)
#define    PORT53_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT53_ADC_1_ADC1_P_9        (PORT_ANALOG_INPUT_MODE)
#define    PORT54_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT54_ADC_1_ADC1_P_10        (PORT_ANALOG_INPUT_MODE)
#define    PORT55_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT55_ADC_1_ADC1_P_11        (PORT_ANALOG_INPUT_MODE)
#define    PORT56_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT56_ADC_1_ADC1_P_12        (PORT_ANALOG_INPUT_MODE)
#define    PORT57_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT57_ADC_1_ADC1_P_13        (PORT_ANALOG_INPUT_MODE)
#define    PORT58_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT58_ADC_1_ADC1_P_14        (PORT_ANALOG_INPUT_MODE)
#define    PORT60_GPIO        (PORT_GPIO_MODE)
#define    PORT60_DSPI_0_dCS5        (PORT_ALT1_FUNC_MODE)
#define    PORT60_EMIOS0_E0UC_24_X_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT60_HSM_DO0        (PORT_ALT3_FUNC_MODE)
#define    PORT60_ADC_0_ADC0_S_4        (PORT_ANALOG_INPUT_MODE)
#define    PORT60_EMIOS0_E0UC_24_X_IN        (PORT_INPUT1_MODE)
#define    PORT60_EMIOS0_E0UC_24_X_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT61_GPIO        (PORT_GPIO_MODE)
#define    PORT61_DSPI_1_dCS0        (PORT_ALT1_FUNC_MODE)
#define    PORT61_EMIOS0_E0UC_25_Y_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT61_ENET0_ENET0_TMR0_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT61_ADC_0_ADC0_S_5        (PORT_ANALOG_INPUT_MODE)
#define    PORT61_EMIOS0_E0UC_25_Y_IN        (PORT_INPUT1_MODE)
#define    PORT61_DSPI_1_dSS        (PORT_INPUT2_MODE)
#define    PORT61_ENET0_ENET0_TMR0_IN        (PORT_INPUT3_MODE)
#define    PORT61_EMIOS0_E0UC_25_Y_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT61_ENET0_ENET0_TMR0_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT62_GPIO        (PORT_GPIO_MODE)
#define    PORT62_DSPI_1_dCS1        (PORT_ALT1_FUNC_MODE)
#define    PORT62_EMIOS0_E0UC_26_Y_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT62_FlexRay_FR_DBG_0        (PORT_ALT3_FUNC_MODE)
#define    PORT62_ADC_0_ADC0_S_6        (PORT_ANALOG_INPUT_MODE)
#define    PORT62_EMIOS0_E0UC_26_Y_IN        (PORT_INPUT1_MODE)
#define    PORT62_EMIOS0_E0UC_26_Y_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT63_GPIO        (PORT_GPIO_MODE)
#define    PORT63_DSPI_1_dCS2        (PORT_ALT1_FUNC_MODE)
#define    PORT63_EMIOS0_E0UC_27_Y_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT63_FlexRay_FR_DBG_1        (PORT_ALT3_FUNC_MODE)
#define    PORT63_ADC_0_ADC0_S_7        (PORT_ANALOG_INPUT_MODE)
#define    PORT63_EMIOS0_E0UC_27_Y_IN        (PORT_INPUT1_MODE)
#define    PORT63_EMIOS0_E0UC_27_Y_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT64_GPIO        (PORT_GPIO_MODE)
#define    PORT64_EMIOS0_E0UC_16_X_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT64_IIC_1_SCL1_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT64_WKPU_WKPU_6        (PORT_ONLY_INPUT_MODE)
#define    PORT64_EMIOS0_E0UC_16_X_IN        (PORT_INPUT1_MODE)
#define    PORT64_FlexCAN_5_RX        (PORT_INPUT2_MODE)
#define    PORT64_LIN_11_LIN11RX        (PORT_INPUT3_MODE)
#define    PORT64_IIC_1_SCL1_IN        (PORT_INPUT4_MODE)
#define    PORT64_EMIOS0_E0UC_16_X_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT64_IIC_1_SCL1_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT65_GPIO        (PORT_GPIO_MODE)
#define    PORT65_EMIOS0_E0UC_17_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT65_FlexCAN_5_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT65_IIC_1_SDA1_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT65_EMIOS0_E0UC_17_Y_IN        (PORT_INPUT1_MODE)
#define    PORT65_IIC_1_SDA1_IN        (PORT_INPUT2_MODE)
#define    PORT65_EMIOS0_E0UC_17_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT65_IIC_1_SDA1_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT66_GPIO        (PORT_GPIO_MODE)
#define    PORT66_EMIOS0_E0UC_18_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT66_FlexRay_FR_A_TX_EN        (PORT_ALT2_FUNC_MODE)
#define    PORT66_EMIOS0_E0UC_18_Y_IN        (PORT_INPUT1_MODE)
#define    PORT66_SIUL2_EIRQ21        (PORT_INPUT2_MODE)
#define    PORT66_DSPI_1_dSIN        (PORT_INPUT3_MODE)
#define    PORT66_EMIOS0_E0UC_18_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT67_GPIO        (PORT_GPIO_MODE)
#define    PORT67_EMIOS0_E0UC_19_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT67_DSPI_1_dSOUT        (PORT_ALT2_FUNC_MODE)
#define    PORT67_WKPU_WKPU_29        (PORT_ONLY_INPUT_MODE)
#define    PORT67_EMIOS0_E0UC_19_Y_IN        (PORT_INPUT1_MODE)
#define    PORT67_FlexRay_FR_A_RX        (PORT_INPUT2_MODE)
#define    PORT67_EMIOS0_E0UC_19_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT68_GPIO        (PORT_GPIO_MODE)
#define    PORT68_EMIOS0_E0UC_20_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT68_DSPI_1_dSCLK_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT68_FlexRay_FR_B_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT68_EMIOS0_E0UC_20_Y_IN        (PORT_INPUT1_MODE)
#define    PORT68_SIUL2_EIRQ9        (PORT_INPUT2_MODE)
#define    PORT68_DSPI_1_dSCLK_IN        (PORT_INPUT3_MODE)
#define    PORT68_EMIOS0_E0UC_20_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT68_DSPI_1_dSCLK_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT69_GPIO        (PORT_GPIO_MODE)
#define    PORT69_EMIOS0_E0UC_21_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT69_DSPI_1_dCS0        (PORT_ALT2_FUNC_MODE)
#define    PORT69_ADC_0_ADC0_MA_2        (PORT_ALT3_FUNC_MODE)
#define    PORT69_WKPU_WKPU_30        (PORT_ONLY_INPUT_MODE)
#define    PORT69_EMIOS0_E0UC_21_Y_IN        (PORT_INPUT1_MODE)
#define    PORT69_FlexRay_FR_B_RX        (PORT_INPUT2_MODE)
#define    PORT69_DSPI_1_dSS        (PORT_INPUT3_MODE)
#define    PORT69_EMIOS0_E0UC_21_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT70_GPIO        (PORT_GPIO_MODE)
#define    PORT70_EMIOS0_E0UC_22_X_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT70_DSPI_0_dCS3        (PORT_ALT2_FUNC_MODE)
#define    PORT70_ADC_0_ADC0_MA_1        (PORT_ALT3_FUNC_MODE)
#define    PORT70_ADC_1_ADC1_MA_1        (PORT_ALT4_FUNC_MODE)
#define    PORT70_EMIOS0_E0UC_22_X_IN        (PORT_INPUT1_MODE)
#define    PORT70_SIUL2_EIRQ22        (PORT_INPUT2_MODE)
#define    PORT70_EMIOS0_E0UC_22_X_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT71_GPIO        (PORT_GPIO_MODE)
#define    PORT71_EMIOS0_E0UC_23_X_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT71_DSPI_0_dCS2        (PORT_ALT2_FUNC_MODE)
#define    PORT71_ADC_0_ADC0_MA_0        (PORT_ALT3_FUNC_MODE)
#define    PORT71_ADC_1_ADC1_MA_0        (PORT_ALT4_FUNC_MODE)
#define    PORT71_EMIOS0_E0UC_23_X_IN        (PORT_INPUT1_MODE)
#define    PORT71_SIUL2_EIRQ23        (PORT_INPUT2_MODE)
#define    PORT71_EMIOS0_E0UC_23_X_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT72_GPIO        (PORT_GPIO_MODE)
#define    PORT72_FlexCAN_2_TX        (PORT_ALT1_FUNC_MODE)
#define    PORT72_EMIOS0_E0UC_22_X_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT72_FlexCAN_3_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT72_IIC_2_SDA2_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT72_LIN_6_LIN6TX        (PORT_ALT5_FUNC_MODE)
#define    PORT72_EMIOS0_E0UC_22_X_IN        (PORT_INPUT1_MODE)
#define    PORT72_IIC_2_SDA2_IN        (PORT_INPUT2_MODE)
#define    PORT72_EMIOS0_E0UC_22_X_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT72_IIC_2_SDA2_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT73_GPIO        (PORT_GPIO_MODE)
#define    PORT73_EMIOS0_E0UC_23_X_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT73_IIC_2_SCL2_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT73_WKPU_WKPU_7        (PORT_ONLY_INPUT_MODE)
#define    PORT73_EMIOS0_E0UC_23_X_IN        (PORT_INPUT1_MODE)
#define    PORT73_FlexCAN_2_RX        (PORT_INPUT2_MODE)
#define    PORT73_FlexCAN_3_RX        (PORT_INPUT3_MODE)
#define    PORT73_IIC_2_SCL2_IN        (PORT_INPUT4_MODE)
#define    PORT73_EMIOS0_E0UC_23_X_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT73_IIC_2_SCL2_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT74_GPIO        (PORT_GPIO_MODE)
#define    PORT74_LIN_3_LIN3TX        (PORT_ALT1_FUNC_MODE)
#define    PORT74_DSPI_1_dCS3        (PORT_ALT2_FUNC_MODE)
#define    PORT74_EMIOS1_E1UC_30_Y_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT74_IIC_3_SDA3_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT74_EMIOS1_E1UC_30_Y_IN        (PORT_INPUT1_MODE)
#define    PORT74_SIUL2_EIRQ10        (PORT_INPUT2_MODE)
#define    PORT74_IIC_3_SDA3_IN        (PORT_INPUT3_MODE)
#define    PORT74_GLITCH_FILTER3_INP        (PORT_INPUT4_MODE)
#define    PORT74_EMIOS1_E1UC_30_Y_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT74_IIC_3_SDA3_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT75_GPIO        (PORT_GPIO_MODE)
#define    PORT75_EMIOS0_E0UC_24_X_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT75_DSPI_1_dCS4        (PORT_ALT2_FUNC_MODE)
#define    PORT75_CGM_CLKOUT1        (PORT_ALT3_FUNC_MODE)
#define    PORT75_IIC_3_SCL3_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT75_WKPU_WKPU_14        (PORT_ONLY_INPUT_MODE)
#define    PORT75_EMIOS0_E0UC_24_X_IN        (PORT_INPUT1_MODE)
#define    PORT75_LIN_3_LIN3RX        (PORT_INPUT2_MODE)
#define    PORT75_IIC_3_SCL3_IN        (PORT_INPUT3_MODE)
#define    PORT75_EMIOS0_E0UC_24_X_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT75_IIC_3_SCL3_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT76_GPIO        (PORT_GPIO_MODE)
#define    PORT76_EMIOS1_E1UC_19_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT76_ADC_1_ADC1_S_13        (PORT_ANALOG_INPUT_MODE)
#define    PORT76_EMIOS1_E1UC_19_Y_IN        (PORT_INPUT1_MODE)
#define    PORT76_SIUL2_EIRQ11        (PORT_INPUT2_MODE)
#define    PORT76_DSPI_2_dSIN        (PORT_INPUT3_MODE)
#define    PORT76_ENET0_MII_0_CRS        (PORT_INPUT4_MODE)
#define    PORT76_EMIOS1_E1UC_19_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT77_GPIO        (PORT_GPIO_MODE)
#define    PORT77_DSPI_2_dSOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT77_EMIOS1_E1UC_20_Y_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT77_ADC_1_ADC1_X_3        (PORT_ANALOG_INPUT_MODE)
#define    PORT77_EMIOS1_E1UC_20_Y_IN        (PORT_INPUT1_MODE)
#define    PORT77_ENET0_MII_0_RXD_3        (PORT_INPUT2_MODE)
#define    PORT77_EMIOS1_E1UC_20_Y_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT78_GPIO        (PORT_GPIO_MODE)
#define    PORT78_DSPI_2_dSCLK_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT78_EMIOS1_E1UC_21_Y_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT78_EMIOS1_E1UC_21_Y_IN        (PORT_INPUT1_MODE)
#define    PORT78_SIUL2_EIRQ12        (PORT_INPUT2_MODE)
#define    PORT78_DSPI_2_dSCLK_IN        (PORT_INPUT3_MODE)
#define    PORT78_DSPI_2_dSCLK_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT78_EMIOS1_E1UC_21_Y_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT79_GPIO        (PORT_GPIO_MODE)
#define    PORT79_DSPI_2_dCS0        (PORT_ALT1_FUNC_MODE)
#define    PORT79_EMIOS1_E1UC_22_X_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT79_SPI_2_SCLK_2_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT79_EMIOS1_E1UC_22_X_IN        (PORT_INPUT1_MODE)
#define    PORT79_DSPI_2_dSS        (PORT_INPUT2_MODE)
#define    PORT79_SPI_2_SCLK_2_IN        (PORT_INPUT3_MODE)
#define    PORT79_EMIOS1_E1UC_22_X_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT79_SPI_2_SCLK_2_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT80_GPIO        (PORT_GPIO_MODE)
#define    PORT80_EMIOS0_E0UC_10_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT80_DSPI_1_dCS3        (PORT_ALT2_FUNC_MODE)
#define    PORT80_FlexCAN_6_TX        (PORT_ALT4_FUNC_MODE)
#define    PORT80_ADC_0_ADC0_S_8        (PORT_ANALOG_INPUT_MODE)
#define    PORT80_CMP2_CMP2_16        (PORT_ANALOG_INPUT_MODE)
#define    PORT80_SAI0_SAI0_MCLK_OUT        (PORT_ALT7_FUNC_MODE)
#define    PORT80_EMIOS0_E0UC_10_H_IN        (PORT_INPUT1_MODE)
#define    PORT80_SAI0_SAI0_MCLK_IN        (PORT_INPUT2_MODE)
#define    PORT80_EMIOS0_E0UC_10_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT80_SAI0_SAI0_MCLK_IN_OUT        (PORT_INOUT7_MODE)
#define    PORT81_GPIO        (PORT_GPIO_MODE)
#define    PORT81_EMIOS0_E0UC_11_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT81_DSPI_1_dCS4        (PORT_ALT2_FUNC_MODE)
#define    PORT81_SPI_0_CS3_0        (PORT_ALT3_FUNC_MODE)
#define    PORT81_SAI0_SAI0_BCLK_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT81_ADC_0_ADC0_S_9        (PORT_ANALOG_INPUT_MODE)
#define    PORT81_CMP2_CMP2_17        (PORT_ANALOG_INPUT_MODE)
#define    PORT81_EMIOS0_E0UC_11_H_IN        (PORT_INPUT1_MODE)
#define    PORT81_SAI0_SAI0_BCLK_IN        (PORT_INPUT2_MODE)
#define    PORT81_EMIOS0_E0UC_11_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT81_SAI0_SAI0_BCLK_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT82_GPIO        (PORT_GPIO_MODE)
#define    PORT82_EMIOS0_E0UC_12_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT82_DSPI_2_dCS0        (PORT_ALT2_FUNC_MODE)
#define    PORT82_SAI0_SAI0_D3_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT82_ADC_0_ADC0_S_10        (PORT_ANALOG_INPUT_MODE)
#define    PORT82_CMP2_CMP2_18        (PORT_ANALOG_INPUT_MODE)
#define    PORT82_EMIOS0_E0UC_12_H_IN        (PORT_INPUT1_MODE)
#define    PORT82_DSPI_2_dSS        (PORT_INPUT2_MODE)
#define    PORT82_SAI0_SAI0_D3_IN        (PORT_INPUT3_MODE)
#define    PORT82_GLITCH_FILTER0_INP        (PORT_INPUT4_MODE)
#define    PORT82_EMIOS0_E0UC_12_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT82_SAI0_SAI0_D3_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT83_GPIO        (PORT_GPIO_MODE)
#define    PORT83_EMIOS0_E0UC_13_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT83_DSPI_2_dCS1        (PORT_ALT2_FUNC_MODE)
#define    PORT83_SAI0_SAI0_D2_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT83_ADC_0_ADC0_S_11        (PORT_ANALOG_INPUT_MODE)
#define    PORT83_CMP2_CMP2_19        (PORT_ANALOG_INPUT_MODE)
#define    PORT83_EMIOS0_E0UC_13_H_IN        (PORT_INPUT1_MODE)
#define    PORT83_SAI0_SAI0_D2_IN        (PORT_INPUT2_MODE)
#define    PORT83_GLITCH_FILTER1_INP        (PORT_INPUT3_MODE)
#define    PORT83_EMIOS0_E0UC_13_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT83_SAI0_SAI0_D2_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT84_GPIO        (PORT_GPIO_MODE)
#define    PORT84_EMIOS0_E0UC_14_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT84_DSPI_2_dCS2        (PORT_ALT2_FUNC_MODE)
#define    PORT84_SAI0_SAI0_D1_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT84_ADC_0_ADC0_S_12        (PORT_ANALOG_INPUT_MODE)
#define    PORT84_CMP2_CMP2_20        (PORT_ANALOG_INPUT_MODE)
#define    PORT84_EMIOS0_E0UC_14_H_IN        (PORT_INPUT1_MODE)
#define    PORT84_SAI0_SAI0_D1_IN        (PORT_INPUT2_MODE)
#define    PORT84_GLITCH_FILTER2_INP        (PORT_INPUT3_MODE)
#define    PORT84_EMIOS0_E0UC_14_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT84_SAI0_SAI0_D1_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT85_GPIO        (PORT_GPIO_MODE)
#define    PORT85_EMIOS0_E0UC_22_X_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT85_DSPI_2_dCS3        (PORT_ALT2_FUNC_MODE)
#define    PORT85_SPI_0_CS2_0        (PORT_ALT3_FUNC_MODE)
#define    PORT85_SAI0_SAI0_D0_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT85_ADC_0_ADC0_S_13        (PORT_ANALOG_INPUT_MODE)
#define    PORT85_CMP2_CMP2_21        (PORT_ANALOG_INPUT_MODE)
#define    PORT85_EMIOS0_E0UC_22_X_IN        (PORT_INPUT1_MODE)
#define    PORT85_SAI0_SAI0_D0_IN        (PORT_INPUT2_MODE)
#define    PORT85_GLITCH_FILTER3_INP        (PORT_INPUT3_MODE)
#define    PORT85_EMIOS0_E0UC_22_X_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT85_SAI0_SAI0_D0_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT86_GPIO        (PORT_GPIO_MODE)
#define    PORT86_EMIOS0_E0UC_23_X_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT86_DSPI_1_dCS1        (PORT_ALT2_FUNC_MODE)
#define    PORT86_SAI1_SAI1_SYNC_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT86_EMIOS0_E0UC_30_Y_OUT        (PORT_ALT5_FUNC_MODE)
#define    PORT86_ADC_0_ADC0_S_14        (PORT_ANALOG_INPUT_MODE)
#define    PORT86_CMP2_CMP2_22        (PORT_ANALOG_INPUT_MODE)
#define    PORT86_EMIOS0_E0UC_23_X_IN        (PORT_INPUT1_MODE)
#define    PORT86_SAI1_SAI1_SYNC_IN        (PORT_INPUT2_MODE)
#define    PORT86_EMIOS0_E0UC_30_Y_IN        (PORT_INPUT3_MODE)
#define    PORT86_EMIOS0_E0UC_23_X_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT86_SAI1_SAI1_SYNC_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT86_EMIOS0_E0UC_30_Y_IN_OUT        (PORT_INOUT5_MODE)
#define    PORT87_GPIO        (PORT_GPIO_MODE)
#define    PORT87_SPI_0_SCLK_0_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT87_DSPI_1_dCS2        (PORT_ALT2_FUNC_MODE)
#define    PORT87_ADC_0_ADC0_S_15        (PORT_ANALOG_INPUT_MODE)
#define    PORT87_CMP2_CMP2_23        (PORT_ANALOG_INPUT_MODE)
#define    PORT87_SAI1_SAI1_MCLK_OUT        (PORT_ALT6_FUNC_MODE)
#define    PORT87_SPI_0_SCLK_0_IN        (PORT_INPUT1_MODE)
#define    PORT87_SAI1_SAI1_MCLK_IN        (PORT_INPUT2_MODE)
#define    PORT87_SPI_0_SCLK_0_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT87_SAI1_SAI1_MCLK_IN_OUT        (PORT_INOUT6_MODE)
#define    PORT88_GPIO        (PORT_GPIO_MODE)
#define    PORT88_FlexCAN_3_TX        (PORT_ALT1_FUNC_MODE)
#define    PORT88_DSPI_0_dCS4        (PORT_ALT2_FUNC_MODE)
#define    PORT88_FlexCAN_2_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT88_EMIOS0_E0UC_15_H_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT88_CMP0_CMP0_5        (PORT_ANALOG_INPUT_MODE)
#define    PORT88_EMIOS0_E0UC_15_H_IN        (PORT_INPUT1_MODE)
#define    PORT88_EMIOS0_E0UC_15_H_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT89_GPIO        (PORT_GPIO_MODE)
#define    PORT89_EMIOS1_E1UC_1_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT89_DSPI_0_dCS5        (PORT_ALT2_FUNC_MODE)
#define    PORT89_EMIOS0_E0UC_14_H_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT89_WKPU_WKPU_22        (PORT_ONLY_INPUT_MODE)
#define    PORT89_CMP0_CMP0_4        (PORT_ANALOG_INPUT_MODE)
#define    PORT89_EMIOS1_E1UC_1_H_IN        (PORT_INPUT1_MODE)
#define    PORT89_FlexCAN_2_RX        (PORT_INPUT2_MODE)
#define    PORT89_FlexCAN_3_RX        (PORT_INPUT3_MODE)
#define    PORT89_EMIOS0_E0UC_14_H_IN        (PORT_INPUT4_MODE)
#define    PORT89_EMIOS1_E1UC_1_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT89_EMIOS0_E0UC_14_H_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT90_GPIO        (PORT_GPIO_MODE)
#define    PORT90_DSPI_0_dCS1        (PORT_ALT1_FUNC_MODE)
#define    PORT90_LIN_4_LIN4TX        (PORT_ALT2_FUNC_MODE)
#define    PORT90_EMIOS1_E1UC_2_H_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT90_FCCU_EOUT0_OUT        (PORT_ALT5_FUNC_MODE)
#define    PORT90_FCCU_EOUT0_IN        (PORT_ONLY_INPUT_MODE)
#define    PORT90_FCCU_EOUT0_IN_OUT        (PORT_INOUT5_MODE)
#define    PORT90_EMIOS0_E0UC_19_Y_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT90_CMP1_CMP1_8        (PORT_ANALOG_INPUT_MODE)
#define    PORT90_EMIOS1_E1UC_2_H_IN        (PORT_INPUT1_MODE)
#define    PORT90_EMIOS0_E0UC_19_Y_IN        (PORT_INPUT2_MODE)
#define    PORT90_EMIOS1_E1UC_2_H_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT90_EMIOS0_E0UC_19_Y_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT91_GPIO        (PORT_GPIO_MODE)
#define    PORT91_DSPI_0_dCS2        (PORT_ALT1_FUNC_MODE)
#define    PORT91_EMIOS1_E1UC_3_H_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT91_EMIOS0_E0UC_20_Y_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT91_WKPU_WKPU_15        (PORT_ONLY_INPUT_MODE)
#define    PORT91_CMP1_CMP1_9        (PORT_ANALOG_INPUT_MODE)
#define    PORT91_EMIOS1_E1UC_3_H_IN        (PORT_INPUT1_MODE)
#define    PORT91_LIN_4_LIN4RX        (PORT_INPUT2_MODE)
#define    PORT91_EMIOS0_E0UC_20_Y_IN        (PORT_INPUT3_MODE)
#define    PORT91_EMIOS1_E1UC_3_H_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT91_EMIOS0_E0UC_20_Y_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT92_GPIO        (PORT_GPIO_MODE)
#define    PORT92_EMIOS1_E1UC_25_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT92_LIN_5_LIN5TX        (PORT_ALT2_FUNC_MODE)
#define    PORT92_FCCU_EOUT1_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT92_FCCU_EOUT1_IN        (PORT_ONLY_INPUT_MODE)
#define    PORT92_FCCU_EOUT1_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT92_EMIOS0_E0UC_16_X_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT92_CMP0_CMP0_6        (PORT_ANALOG_INPUT_MODE)
#define    PORT92_EMIOS1_E1UC_25_Y_IN        (PORT_INPUT1_MODE)
#define    PORT92_EMIOS0_E0UC_16_X_IN        (PORT_INPUT2_MODE)
#define    PORT92_EMIOS1_E1UC_25_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT92_EMIOS0_E0UC_16_X_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT93_GPIO        (PORT_GPIO_MODE)
#define    PORT93_EMIOS1_E1UC_26_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT93_EMIOS0_E0UC_22_X_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT93_WKPU_WKPU_16        (PORT_ONLY_INPUT_MODE)
#define    PORT93_CMP1_CMP1_11        (PORT_ANALOG_INPUT_MODE)
#define    PORT93_EMIOS1_E1UC_26_Y_IN        (PORT_INPUT1_MODE)
#define    PORT93_LIN_5_LIN5RX        (PORT_INPUT2_MODE)
#define    PORT93_EMIOS0_E0UC_22_X_IN        (PORT_INPUT3_MODE)
#define    PORT93_EMIOS1_E1UC_26_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT93_EMIOS0_E0UC_22_X_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT94_GPIO        (PORT_GPIO_MODE)
#define    PORT94_FlexCAN_4_TX        (PORT_ALT1_FUNC_MODE)
#define    PORT94_EMIOS1_E1UC_27_Y_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT94_FlexCAN_1_TX        (PORT_ALT3_FUNC_MODE)
/**
* @violates @ref PORT_CFG_H_REF_1 MISRA 2004 Rule 1.4, The compiler/linker shall be checked to
*  ensure that 31 character significance and case sensitivity are supported for external ids
*/
#define    PORT94_ENET0_MII_RMII_0_MDIO_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT94_ADC_1_ADC1_X_2        (PORT_ANALOG_INPUT_MODE)
#define    PORT94_EMIOS1_E1UC_27_Y_IN        (PORT_INPUT1_MODE)
#define    PORT94_ENET0_MII_RMII_0_MDIO_IN        (PORT_INPUT2_MODE)
#define    PORT94_EMIOS1_E1UC_27_Y_IN_OUT        (PORT_INOUT2_MODE)
/**
* @violates @ref PORT_CFG_H_REF_1 MISRA 2004 Rule 1.4, The compiler/linker shall be checked to
*  ensure that 31 character significance and case sensitivity are supported for external ids
*/
#define    PORT94_ENET0_MII_RMII_0_MDIO_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT95_GPIO        (PORT_GPIO_MODE)
#define    PORT95_EMIOS1_E1UC_4_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT95_ADC_1_ADC1_X_1        (PORT_ANALOG_INPUT_MODE)
#define    PORT95_EMIOS1_E1UC_4_H_IN        (PORT_INPUT1_MODE)
#define    PORT95_SIUL2_EIRQ13        (PORT_INPUT2_MODE)
#define    PORT95_FlexCAN_1_RX        (PORT_INPUT3_MODE)
#define    PORT95_FlexCAN_4_RX        (PORT_INPUT4_MODE)
#define    PORT95_ENET0_MII_RMII_0_RX_DV        (PORT_INPUT5_MODE)
#define    PORT95_EMIOS1_E1UC_4_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT96_GPIO        (PORT_GPIO_MODE)
#define    PORT96_FlexCAN_5_TX        (PORT_ALT1_FUNC_MODE)
#define    PORT96_EMIOS1_E1UC_23_X_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT96_ENET0_MII_RMII_0_MDC        (PORT_ALT3_FUNC_MODE)
#define    PORT96_ADC_1_ADC1_X_0        (PORT_ANALOG_INPUT_MODE)
#define    PORT96_EMIOS1_E1UC_23_X_IN        (PORT_INPUT1_MODE)
#define    PORT96_EMIOS1_E1UC_23_X_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT97_GPIO        (PORT_GPIO_MODE)
#define    PORT97_EMIOS1_E1UC_24_X_OUT        (PORT_ALT1_FUNC_MODE)
/**
* @violates @ref PORT_CFG_H_REF_1 MISRA 2004 Rule 1.4, The compiler/linker shall be checked to
*  ensure that 31 character significance and case sensitivity are supported for external ids
*/
#define    PORT97_ENET0_MII_RMII_0_TX_CLK_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT97_ADC_1_ADC1_S_7        (PORT_ANALOG_INPUT_MODE)
#define    PORT97_EMIOS1_E1UC_24_X_IN        (PORT_INPUT1_MODE)
#define    PORT97_SIUL2_EIRQ14        (PORT_INPUT2_MODE)
#define    PORT97_FlexCAN_5_RX        (PORT_INPUT3_MODE)
/**
* @violates @ref PORT_CFG_H_REF_1 MISRA 2004 Rule 1.4, The compiler/linker shall be checked to
*  ensure that 31 character significance and case sensitivity are supported for external ids
*/
#define    PORT97_ENET0_MII_RMII_0_TX_CLK_IN        (PORT_INPUT4_MODE)
#define    PORT97_EMIOS1_E1UC_24_X_IN_OUT        (PORT_INOUT1_MODE)
/**
* @violates @ref PORT_CFG_H_REF_1 MISRA 2004 Rule 1.4, The compiler/linker shall be checked to
*  ensure that 31 character significance and case sensitivity are supported for external ids
*/
#define    PORT97_ENET0_MII_RMII_0_TX_CLK_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT98_GPIO        (PORT_GPIO_MODE)
#define    PORT98_EMIOS1_E1UC_11_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT98_DSPI_3_dSOUT        (PORT_ALT2_FUNC_MODE)
#define    PORT98_FlexCAN_7_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT98_LIN_11_LIN11TX        (PORT_ALT4_FUNC_MODE)
#define    PORT98_EMIOS1_E1UC_11_H_IN        (PORT_INPUT1_MODE)
#define    PORT98_EMIOS1_E1UC_11_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT99_GPIO        (PORT_GPIO_MODE)
#define    PORT99_EMIOS1_E1UC_12_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT99_DSPI_3_dCS0        (PORT_ALT2_FUNC_MODE)
#define    PORT99_WKPU_WKPU_17        (PORT_ONLY_INPUT_MODE)
#define    PORT99_EMIOS1_E1UC_12_H_IN        (PORT_INPUT1_MODE)
#define    PORT99_FlexCAN_7_RX        (PORT_INPUT2_MODE)
#define    PORT99_DSPI_3_dSS        (PORT_INPUT3_MODE)
#define    PORT99_EMIOS1_E1UC_12_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT100_GPIO        (PORT_GPIO_MODE)
#define    PORT100_EMIOS1_E1UC_13_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT100_DSPI_3_dSCLK_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT100_LIN_10_LIN10TX        (PORT_ALT3_FUNC_MODE)
#define    PORT100_EMIOS1_E1UC_13_H_IN        (PORT_INPUT1_MODE)
#define    PORT100_DSPI_3_dSCLK_IN        (PORT_INPUT2_MODE)
#define    PORT100_EMIOS1_E1UC_13_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT100_DSPI_3_dSCLK_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT101_GPIO        (PORT_GPIO_MODE)
#define    PORT101_EMIOS1_E1UC_14_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT101_EMIOS0_E0UC_2_G_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT101_WKPU_WKPU_18        (PORT_ONLY_INPUT_MODE)
#define    PORT101_EMIOS1_E1UC_14_H_IN        (PORT_INPUT1_MODE)
#define    PORT101_LIN_10_LIN10RX        (PORT_INPUT2_MODE)
#define    PORT101_DSPI_3_dSIN        (PORT_INPUT3_MODE)
#define    PORT101_EMIOS0_E0UC_2_G_IN        (PORT_INPUT4_MODE)
#define    PORT101_EMIOS1_E1UC_14_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT101_EMIOS0_E0UC_2_G_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT102_GPIO        (PORT_GPIO_MODE)
#define    PORT102_EMIOS1_E1UC_15_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT102_LIN_6_LIN6TX        (PORT_ALT2_FUNC_MODE)
#define    PORT102_CGM_CLKOUT1        (PORT_ALT3_FUNC_MODE)
#define    PORT102_EMIOS0_E0UC_3_G_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT102_CMP0_CMP0_1        (PORT_ANALOG_INPUT_MODE)
#define    PORT102_PMCDIG_EXTREGC        (PORT_ONLY_OUTPUT_MODE)
#define    PORT102_EMIOS1_E1UC_15_H_IN        (PORT_INPUT1_MODE)
#define    PORT102_EMIOS0_E0UC_3_G_IN        (PORT_INPUT2_MODE)
#define    PORT102_EMIOS1_E1UC_15_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT102_EMIOS0_E0UC_3_G_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT103_GPIO        (PORT_GPIO_MODE)
#define    PORT103_EMIOS1_E1UC_16_X_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT103_EMIOS1_E1UC_30_Y_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT103_CGM_CLKOUT0        (PORT_ALT3_FUNC_MODE)
#define    PORT103_WKPU_WKPU_20        (PORT_ONLY_INPUT_MODE)
#define    PORT103_CMP0_CMP0_0        (PORT_ANALOG_INPUT_MODE)
#define    PORT103_EMIOS1_E1UC_16_X_IN        (PORT_INPUT1_MODE)
#define    PORT103_EMIOS1_E1UC_30_Y_IN        (PORT_INPUT2_MODE)
#define    PORT103_LIN_6_LIN6RX        (PORT_INPUT3_MODE)
#define    PORT103_GLITCH_FILTER3_INP        (PORT_INPUT4_MODE)
#define    PORT103_EMIOS1_E1UC_16_X_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT103_EMIOS1_E1UC_30_Y_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT104_GPIO        (PORT_GPIO_MODE)
#define    PORT104_EMIOS1_E1UC_17_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT104_LIN_7_LIN7TX        (PORT_ALT2_FUNC_MODE)
#define    PORT104_DSPI_2_dCS0        (PORT_ALT3_FUNC_MODE)
#define    PORT104_FlexCAN_7_TX        (PORT_ALT4_FUNC_MODE)
#define    PORT104_EMIOS1_E1UC_17_Y_IN        (PORT_INPUT1_MODE)
#define    PORT104_SIUL2_EIRQ15        (PORT_INPUT2_MODE)
#define    PORT104_DSPI_2_dSS        (PORT_INPUT3_MODE)
#define    PORT104_EMIOS1_E1UC_17_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT105_GPIO        (PORT_GPIO_MODE)
#define    PORT105_EMIOS1_E1UC_18_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT105_DSPI_2_dSCLK_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT105_EMIOS0_E0UC_0_X_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT105_WKPU_WKPU_21        (PORT_ONLY_INPUT_MODE)
#define    PORT105_EMIOS1_E1UC_18_Y_IN        (PORT_INPUT1_MODE)
#define    PORT105_FlexCAN_7_RX        (PORT_INPUT2_MODE)
#define    PORT105_LIN_7_LIN7RX        (PORT_INPUT3_MODE)
#define    PORT105_DSPI_2_dSCLK_IN        (PORT_INPUT4_MODE)
#define    PORT105_EMIOS0_E0UC_0_X_IN        (PORT_INPUT5_MODE)
#define    PORT105_EMIOS1_E1UC_18_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT105_DSPI_2_dSCLK_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT105_EMIOS0_E0UC_0_X_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT106_GPIO        (PORT_GPIO_MODE)
#define    PORT106_EMIOS0_E0UC_24_X_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT106_EMIOS1_E1UC_31_Y_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT106_EMIOS0_E0UC_24_X_IN        (PORT_INPUT1_MODE)
#define    PORT106_EMIOS1_E1UC_31_Y_IN        (PORT_INPUT2_MODE)
#define    PORT106_SPI_0_SIN_0        (PORT_INPUT3_MODE)
#define    PORT106_GLITCH_FILTER3_INP        (PORT_INPUT4_MODE)
#define    PORT106_EMIOS0_E0UC_24_X_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT106_EMIOS1_E1UC_31_Y_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT107_GPIO        (PORT_GPIO_MODE)
#define    PORT107_EMIOS0_E0UC_25_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT107_SPI_0_CS0_0        (PORT_ALT2_FUNC_MODE)
#define    PORT107_SPI_2_CS0_2        (PORT_ALT3_FUNC_MODE)
#define    PORT107_EMIOS0_E0UC_25_Y_IN        (PORT_INPUT1_MODE)
#define    PORT107_SPI_0_SS_0        (PORT_INPUT2_MODE)
#define    PORT107_SPI_2_SS_2        (PORT_INPUT3_MODE)
#define    PORT107_EMIOS0_E0UC_25_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT108_GPIO        (PORT_GPIO_MODE)
#define    PORT108_EMIOS0_E0UC_26_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT108_SPI_0_SOUT_0        (PORT_ALT2_FUNC_MODE)
#define    PORT108_ENET0_MII_0_TXD_2        (PORT_ALT4_FUNC_MODE)
#define    PORT108_ADC_1_ADC1_S_2        (PORT_ANALOG_INPUT_MODE)
#define    PORT108_EMIOS0_E0UC_26_Y_IN        (PORT_INPUT1_MODE)
#define    PORT108_EMIOS0_E0UC_26_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT109_GPIO        (PORT_GPIO_MODE)
#define    PORT109_EMIOS0_E0UC_27_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT109_SPI_0_SCLK_0_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT109_ENET0_MII_0_TXD_3        (PORT_ALT4_FUNC_MODE)
#define    PORT109_ADC_1_ADC1_S_1        (PORT_ANALOG_INPUT_MODE)
#define    PORT109_EMIOS0_E0UC_27_Y_IN        (PORT_INPUT1_MODE)
#define    PORT109_SPI_0_SCLK_0_IN        (PORT_INPUT2_MODE)
#define    PORT109_EMIOS0_E0UC_27_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT109_SPI_0_SCLK_0_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT110_GPIO        (PORT_GPIO_MODE)
#define    PORT110_EMIOS1_E1UC_0_X_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT110_LIN_8_LIN8TX        (PORT_ALT2_FUNC_MODE)
#define    PORT110_EMIOS1_E1UC_0_X_IN        (PORT_INPUT1_MODE)
#define    PORT110_SPI_2_SIN_2        (PORT_INPUT2_MODE)
#define    PORT110_EMIOS1_E1UC_0_X_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT111_GPIO        (PORT_GPIO_MODE)
#define    PORT111_EMIOS1_E1UC_1_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT111_SPI_2_SOUT_2        (PORT_ALT2_FUNC_MODE)
#define    PORT111_EMIOS1_E1UC_1_H_IN        (PORT_INPUT1_MODE)
#define    PORT111_LIN_8_LIN8RX        (PORT_INPUT2_MODE)
#define    PORT111_EMIOS1_E1UC_1_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT112_GPIO        (PORT_GPIO_MODE)
#define    PORT112_EMIOS1_E1UC_2_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT112_ENET0_MII_RMII_0_TXD_1        (PORT_ALT3_FUNC_MODE)
#define    PORT112_ADC_1_ADC1_S_3        (PORT_ANALOG_INPUT_MODE)
#define    PORT112_EMIOS1_E1UC_2_H_IN        (PORT_INPUT1_MODE)
#define    PORT112_DSPI_1_dSIN        (PORT_INPUT2_MODE)
#define    PORT112_EMIOS1_E1UC_2_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT113_GPIO        (PORT_GPIO_MODE)
#define    PORT113_EMIOS1_E1UC_3_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT113_DSPI_1_dSOUT        (PORT_ALT2_FUNC_MODE)
#define    PORT113_ENET0_MII_RMII_0_TXD_0        (PORT_ALT4_FUNC_MODE)
#define    PORT113_ADC_1_ADC1_S_4        (PORT_ANALOG_INPUT_MODE)
#define    PORT113_EMIOS1_E1UC_3_H_IN        (PORT_INPUT1_MODE)
#define    PORT113_EMIOS1_E1UC_3_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT114_GPIO        (PORT_GPIO_MODE)
#define    PORT114_EMIOS1_E1UC_4_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT114_DSPI_1_dSCLK_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT114_ENET0_MII_RMII_0_TX_EN        (PORT_ALT4_FUNC_MODE)
#define    PORT114_ADC_1_ADC1_S_5        (PORT_ANALOG_INPUT_MODE)
#define    PORT114_EMIOS1_E1UC_4_H_IN        (PORT_INPUT1_MODE)
#define    PORT114_DSPI_1_dSCLK_IN        (PORT_INPUT2_MODE)
#define    PORT114_EMIOS1_E1UC_4_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT114_DSPI_1_dSCLK_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT115_GPIO        (PORT_GPIO_MODE)
#define    PORT115_EMIOS1_E1UC_5_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT115_DSPI_1_dCS0        (PORT_ALT2_FUNC_MODE)
#define    PORT115_ENET0_MII_0_TX_ER        (PORT_ALT3_FUNC_MODE)
#define    PORT115_ADC_1_ADC1_S_6        (PORT_ANALOG_INPUT_MODE)
#define    PORT115_EMIOS1_E1UC_5_H_IN        (PORT_INPUT1_MODE)
#define    PORT115_DSPI_1_dSS        (PORT_INPUT2_MODE)
#define    PORT115_EMIOS1_E1UC_5_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT116_GPIO        (PORT_GPIO_MODE)
#define    PORT116_EMIOS1_E1UC_6_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT116_SPI_3_SOUT_3        (PORT_ALT2_FUNC_MODE)
#define    PORT116_IIC_3_SCL3_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT116_EMIOS1_E1UC_6_H_IN        (PORT_INPUT1_MODE)
#define    PORT116_IIC_3_SCL3_IN        (PORT_INPUT2_MODE)
#define    PORT116_EMIOS1_E1UC_6_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT116_IIC_3_SCL3_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT117_GPIO        (PORT_GPIO_MODE)
#define    PORT117_EMIOS1_E1UC_7_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT117_IIC_3_SDA3_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT117_EMIOS1_E1UC_7_H_IN        (PORT_INPUT1_MODE)
#define    PORT117_IIC_3_SDA3_IN        (PORT_INPUT2_MODE)
#define    PORT117_SPI_3_SIN_3        (PORT_INPUT3_MODE)
#define    PORT117_EMIOS1_E1UC_7_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT117_IIC_3_SDA3_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT118_GPIO        (PORT_GPIO_MODE)
#define    PORT118_EMIOS1_E1UC_8_X_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT118_SPI_3_SCLK_3_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT118_ADC_0_ADC0_MA_2        (PORT_ALT3_FUNC_MODE)
#define    PORT118_ADC_1_ADC1_MA_2        (PORT_ALT4_FUNC_MODE)
#define    PORT118_EMIOS1_E1UC_8_X_IN        (PORT_INPUT1_MODE)
#define    PORT118_SPI_3_SCLK_3_IN        (PORT_INPUT2_MODE)
#define    PORT118_EMIOS1_E1UC_8_X_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT118_SPI_3_SCLK_3_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT119_GPIO        (PORT_GPIO_MODE)
#define    PORT119_EMIOS1_E1UC_9_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT119_DSPI_2_dCS3        (PORT_ALT2_FUNC_MODE)
#define    PORT119_ADC_0_ADC0_MA_1        (PORT_ALT3_FUNC_MODE)
#define    PORT119_SPI_3_CS0_3        (PORT_ALT4_FUNC_MODE)
#define    PORT119_ADC_1_ADC1_MA_1        (PORT_ALT5_FUNC_MODE)
#define    PORT119_EMIOS1_E1UC_9_H_IN        (PORT_INPUT1_MODE)
#define    PORT119_SPI_3_SS_3        (PORT_INPUT2_MODE)
#define    PORT119_EMIOS1_E1UC_9_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT120_GPIO        (PORT_GPIO_MODE)
#define    PORT120_EMIOS1_E1UC_10_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT120_DSPI_2_dCS2        (PORT_ALT2_FUNC_MODE)
#define    PORT120_ADC_0_ADC0_MA_0        (PORT_ALT3_FUNC_MODE)
#define    PORT120_ADC_1_ADC1_MA_0        (PORT_ALT4_FUNC_MODE)
#define    PORT120_EMIOS1_E1UC_10_H_IN        (PORT_INPUT1_MODE)
#define    PORT120_EMIOS1_E1UC_10_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT121_GPIO        (PORT_GPIO_MODE)
#define    PORT121_DCI_TCK        (PORT_ALT1_FUNC_MODE)
#define    PORT122_GPIO        (PORT_GPIO_MODE)
#define    PORT122_DCI_TMS_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT122_DCI_TMS_IN        (PORT_ONLY_INPUT_MODE)
#define    PORT122_DCI_TMS_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT123_GPIO        (PORT_GPIO_MODE)
#define    PORT123_DSPI_3_dSOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT123_SPI_0_CS0_0        (PORT_ALT2_FUNC_MODE)
#define    PORT123_EMIOS1_E1UC_5_H_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT123_EMIOS1_E1UC_5_H_IN        (PORT_INPUT1_MODE)
#define    PORT123_SPI_0_SS_0        (PORT_INPUT2_MODE)
#define    PORT123_EMIOS1_E1UC_5_H_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT124_GPIO        (PORT_GPIO_MODE)
#define    PORT124_DSPI_3_dSCLK_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT124_SPI_0_CS1_0        (PORT_ALT2_FUNC_MODE)
#define    PORT124_EMIOS1_E1UC_25_Y_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT124_EMIOS1_E1UC_25_Y_IN        (PORT_INPUT1_MODE)
#define    PORT124_DSPI_3_dSCLK_IN        (PORT_INPUT2_MODE)
#define    PORT124_DSPI_3_dSCLK_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT124_EMIOS1_E1UC_25_Y_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT125_GPIO        (PORT_GPIO_MODE)
#define    PORT125_SPI_0_SOUT_0        (PORT_ALT1_FUNC_MODE)
#define    PORT125_DSPI_3_dCS0        (PORT_ALT2_FUNC_MODE)
#define    PORT125_EMIOS1_E1UC_26_Y_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT125_FCCU_EOUT1_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT125_FCCU_EOUT1_IN        (PORT_ONLY_INPUT_MODE)
#define    PORT125_FCCU_EOUT1_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT125_EMIOS1_E1UC_26_Y_IN        (PORT_INPUT1_MODE)
#define    PORT125_DSPI_3_dSS        (PORT_INPUT2_MODE)
#define    PORT125_EMIOS1_E1UC_26_Y_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT126_GPIO        (PORT_GPIO_MODE)
#define    PORT126_SPI_0_SCLK_0_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT126_DSPI_3_dCS1        (PORT_ALT2_FUNC_MODE)
#define    PORT126_EMIOS1_E1UC_27_Y_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT126_EMIOS1_E1UC_27_Y_IN        (PORT_INPUT1_MODE)
#define    PORT126_SPI_0_SCLK_0_IN        (PORT_INPUT2_MODE)
#define    PORT126_FCCU_EIN_ERR        (PORT_INPUT3_MODE)
#define    PORT126_SPI_0_SCLK_0_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT126_EMIOS1_E1UC_27_Y_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT127_GPIO        (PORT_GPIO_MODE)
#define    PORT127_SPI_1_SOUT_1        (PORT_ALT1_FUNC_MODE)
#define    PORT127_EMIOS1_E1UC_17_Y_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT127_FCCU_EOUT0_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT127_FCCU_EOUT0_IN        (PORT_ONLY_INPUT_MODE)
#define    PORT127_FCCU_EOUT0_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT127_EMIOS1_E1UC_17_Y_IN        (PORT_INPUT1_MODE)
#define    PORT127_EMIOS1_E1UC_17_Y_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT128_GPIO        (PORT_GPIO_MODE)
#define    PORT128_EMIOS0_E0UC_28_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT128_LIN_8_LIN8TX        (PORT_ALT2_FUNC_MODE)
#define    PORT128_IIC_1_SDA1_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT128_EMIOS0_E0UC_28_Y_IN        (PORT_INPUT1_MODE)
#define    PORT128_IIC_1_SDA1_IN        (PORT_INPUT2_MODE)
#define    PORT128_GLITCH_FILTER0_INP        (PORT_INPUT3_MODE)
#define    PORT128_EMIOS0_E0UC_28_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT128_IIC_1_SDA1_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT129_GPIO        (PORT_GPIO_MODE)
#define    PORT129_EMIOS0_E0UC_29_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT129_IIC_1_SCL1_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT129_WKPU_WKPU_24        (PORT_ONLY_INPUT_MODE)
#define    PORT129_EMIOS0_E0UC_29_Y_IN        (PORT_INPUT1_MODE)
#define    PORT129_LIN_8_LIN8RX        (PORT_INPUT2_MODE)
#define    PORT129_IIC_1_SCL1_IN        (PORT_INPUT3_MODE)
#define    PORT129_GLITCH_FILTER0_INP        (PORT_INPUT4_MODE)
#define    PORT129_EMIOS0_E0UC_29_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT129_IIC_1_SCL1_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT130_GPIO        (PORT_GPIO_MODE)
#define    PORT130_EMIOS0_E0UC_30_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT130_LIN_9_LIN9TX        (PORT_ALT2_FUNC_MODE)
#define    PORT130_IIC_2_SDA2_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT130_EMIOS0_E0UC_30_Y_IN        (PORT_INPUT1_MODE)
#define    PORT130_IIC_2_SDA2_IN        (PORT_INPUT2_MODE)
#define    PORT130_GLITCH_FILTER1_INP        (PORT_INPUT3_MODE)
#define    PORT130_EMIOS0_E0UC_30_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT130_IIC_2_SDA2_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT131_GPIO        (PORT_GPIO_MODE)
#define    PORT131_EMIOS0_E0UC_31_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT131_IIC_2_SCL2_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT131_WKPU_WKPU_23        (PORT_ONLY_INPUT_MODE)
#define    PORT131_EMIOS0_E0UC_31_Y_IN        (PORT_INPUT1_MODE)
#define    PORT131_LIN_9_LIN9RX        (PORT_INPUT2_MODE)
#define    PORT131_IIC_2_SCL2_IN        (PORT_INPUT3_MODE)
#define    PORT131_GLITCH_FILTER1_INP        (PORT_INPUT4_MODE)
#define    PORT131_EMIOS0_E0UC_31_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT131_IIC_2_SCL2_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT132_GPIO        (PORT_GPIO_MODE)
#define    PORT132_EMIOS1_E1UC_28_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT132_SPI_0_SOUT_0        (PORT_ALT2_FUNC_MODE)
#define    PORT132_EMIOS1_E1UC_28_Y_IN        (PORT_INPUT1_MODE)
#define    PORT132_GLITCH_FILTER2_INP        (PORT_INPUT2_MODE)
#define    PORT132_EMIOS1_E1UC_28_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT133_GPIO        (PORT_GPIO_MODE)
#define    PORT133_EMIOS1_E1UC_29_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT133_SPI_0_SCLK_0_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT133_SPI_1_CS2_1        (PORT_ALT3_FUNC_MODE)
#define    PORT133_SPI_2_CS2_2        (PORT_ALT4_FUNC_MODE)
#define    PORT133_EMIOS1_E1UC_29_Y_IN        (PORT_INPUT1_MODE)
#define    PORT133_SPI_0_SCLK_0_IN        (PORT_INPUT2_MODE)
#define    PORT133_GLITCH_FILTER2_INP        (PORT_INPUT3_MODE)
#define    PORT133_EMIOS1_E1UC_29_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT133_SPI_0_SCLK_0_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT134_GPIO        (PORT_GPIO_MODE)
#define    PORT134_EMIOS1_E1UC_30_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT134_SPI_0_CS0_0        (PORT_ALT2_FUNC_MODE)
#define    PORT134_SPI_1_CS0_1        (PORT_ALT3_FUNC_MODE)
#define    PORT134_SPI_2_CS0_2        (PORT_ALT4_FUNC_MODE)
#define    PORT134_HSM_DO0        (PORT_ALT5_FUNC_MODE)
#define    PORT134_EMIOS1_E1UC_30_Y_IN        (PORT_INPUT1_MODE)
#define    PORT134_SPI_0_SS_0        (PORT_INPUT2_MODE)
#define    PORT134_SPI_1_SS_1        (PORT_INPUT3_MODE)
#define    PORT134_SPI_2_SS_2        (PORT_INPUT4_MODE)
#define    PORT134_GLITCH_FILTER3_INP        (PORT_INPUT5_MODE)
#define    PORT134_EMIOS1_E1UC_30_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT135_GPIO        (PORT_GPIO_MODE)
#define    PORT135_EMIOS1_E1UC_31_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT135_SPI_0_CS1_0        (PORT_ALT2_FUNC_MODE)
#define    PORT135_SPI_1_CS1_1        (PORT_ALT3_FUNC_MODE)
#define    PORT135_SPI_2_CS1_2        (PORT_ALT4_FUNC_MODE)
#define    PORT135_HSM_DO1        (PORT_ALT5_FUNC_MODE)
#define    PORT135_EMIOS1_E1UC_31_Y_IN        (PORT_INPUT1_MODE)
#define    PORT135_GLITCH_FILTER3_INP        (PORT_INPUT2_MODE)
#define    PORT135_EMIOS1_E1UC_31_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT136_GPIO        (PORT_GPIO_MODE)
#define    PORT136_ADC_0_ADC0_S_16        (PORT_ANALOG_INPUT_MODE)
#define    PORT139_GPIO        (PORT_GPIO_MODE)
#define    PORT139_ENET0_ENET0_TMR1_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT139_ADC_0_ADC0_S_19        (PORT_ANALOG_INPUT_MODE)
#define    PORT139_DSPI_3_dSIN        (PORT_INPUT1_MODE)
#define    PORT139_ENET0_ENET0_TMR1_IN        (PORT_INPUT2_MODE)
#define    PORT139_ENET0_ENET0_TMR1_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT140_GPIO        (PORT_GPIO_MODE)
#define    PORT140_DSPI_3_dCS0        (PORT_ALT1_FUNC_MODE)
#define    PORT140_DSPI_2_dCS0        (PORT_ALT2_FUNC_MODE)
#define    PORT140_ADC_0_ADC0_S_20        (PORT_ANALOG_INPUT_MODE)
#define    PORT140_DSPI_2_dSS        (PORT_INPUT1_MODE)
#define    PORT140_DSPI_3_dSS        (PORT_INPUT2_MODE)
#define    PORT141_GPIO        (PORT_GPIO_MODE)
#define    PORT141_DSPI_3_dCS1        (PORT_ALT1_FUNC_MODE)
#define    PORT141_DSPI_2_dCS1        (PORT_ALT2_FUNC_MODE)
#define    PORT141_ADC_0_ADC0_S_21        (PORT_ANALOG_INPUT_MODE)
#define    PORT142_GPIO        (PORT_GPIO_MODE)
#define    PORT142_SAI2_SAI2_D0_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT142_ADC_0_ADC0_S_22        (PORT_ANALOG_INPUT_MODE)
#define    PORT142_SPI_0_SIN_0        (PORT_INPUT1_MODE)
#define    PORT142_SAI2_SAI2_D0_IN        (PORT_INPUT2_MODE)
#define    PORT142_SAI2_SAI2_D0_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT143_GPIO        (PORT_GPIO_MODE)
#define    PORT143_SPI_0_CS0_0        (PORT_ALT1_FUNC_MODE)
#define    PORT143_DSPI_2_dCS2        (PORT_ALT2_FUNC_MODE)
#define    PORT143_SAI2_SAI2_MCLK_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT143_ADC_0_ADC0_S_23        (PORT_ANALOG_INPUT_MODE)
#define    PORT143_SPI_0_SS_0        (PORT_INPUT1_MODE)
#define    PORT143_SAI2_SAI2_MCLK_IN        (PORT_INPUT2_MODE)
#define    PORT143_SAI2_SAI2_MCLK_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT144_GPIO        (PORT_GPIO_MODE)
#define    PORT144_SPI_0_CS1_0        (PORT_ALT1_FUNC_MODE)
#define    PORT144_DSPI_2_dCS3        (PORT_ALT2_FUNC_MODE)
#define    PORT144_SAI2_SAI2_SYNC_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT144_ADC_0_ADC0_S_24        (PORT_ANALOG_INPUT_MODE)
#define    PORT144_SAI2_SAI2_SYNC_IN        (PORT_INPUT1_MODE)
#define    PORT144_SAI2_SAI2_SYNC_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT145_GPIO        (PORT_GPIO_MODE)
#define    PORT145_SPI_0_SOUT_0        (PORT_ALT1_FUNC_MODE)
#define    PORT145_SAI2_SAI2_BCLK_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT145_ADC_0_ADC0_S_25        (PORT_ANALOG_INPUT_MODE)
#define    PORT145_SPI_1_SIN_1        (PORT_INPUT1_MODE)
#define    PORT145_SAI2_SAI2_BCLK_IN        (PORT_INPUT2_MODE)
#define    PORT145_SAI2_SAI2_BCLK_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT146_GPIO        (PORT_GPIO_MODE)
#define    PORT146_SPI_1_CS0_1        (PORT_ALT1_FUNC_MODE)
#define    PORT146_SPI_2_CS0_2        (PORT_ALT2_FUNC_MODE)
#define    PORT146_SPI_3_CS0_3        (PORT_ALT3_FUNC_MODE)
#define    PORT146_SAI1_SAI1_D0_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT146_ADC_0_ADC0_S_26        (PORT_ANALOG_INPUT_MODE)
#define    PORT146_SPI_1_SS_1        (PORT_INPUT1_MODE)
#define    PORT146_SPI_2_SS_2        (PORT_INPUT2_MODE)
#define    PORT146_SPI_3_SS_3        (PORT_INPUT3_MODE)
#define    PORT146_SAI1_SAI1_D0_IN        (PORT_INPUT4_MODE)
#define    PORT146_SAI1_SAI1_D0_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT147_GPIO        (PORT_GPIO_MODE)
#define    PORT147_SPI_1_CS1_1        (PORT_ALT1_FUNC_MODE)
#define    PORT147_SPI_2_CS1_2        (PORT_ALT2_FUNC_MODE)
#define    PORT147_SPI_3_CS1_3        (PORT_ALT3_FUNC_MODE)
#define    PORT147_SAI1_SAI1_BCLK_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT147_ADC_0_ADC0_S_27        (PORT_ANALOG_INPUT_MODE)
#define    PORT147_SAI1_SAI1_BCLK_IN        (PORT_INPUT1_MODE)
#define    PORT147_SAI1_SAI1_BCLK_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT148_GPIO        (PORT_GPIO_MODE)
#define    PORT148_SPI_1_SCLK_1_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT148_EMIOS1_E1UC_18_Y_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT148_EMIOS1_E1UC_18_Y_IN        (PORT_INPUT1_MODE)
#define    PORT148_SPI_1_SCLK_1_IN        (PORT_INPUT2_MODE)
#define    PORT148_FCCU_EIN_ERR        (PORT_INPUT3_MODE)
#define    PORT148_SPI_1_SCLK_1_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT148_EMIOS1_E1UC_18_Y_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT157_GPIO        (PORT_GPIO_MODE)
#define    PORT157_SPI_3_CS1_3        (PORT_ALT1_FUNC_MODE)
#define    PORT157_EMIOS1_E1UC_15_H_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT157_WKPU_WKPU_31        (PORT_ONLY_INPUT_MODE)
#define    PORT157_EMIOS1_E1UC_15_H_IN        (PORT_INPUT1_MODE)
#define    PORT157_FlexCAN_1_RX        (PORT_INPUT2_MODE)
#define    PORT157_FlexCAN_4_RX        (PORT_INPUT3_MODE)
#define    PORT157_FlexCAN_6_RX        (PORT_INPUT4_MODE)
#define    PORT157_EMIOS1_E1UC_15_H_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT158_GPIO        (PORT_GPIO_MODE)
#define    PORT158_FlexCAN_1_TX        (PORT_ALT1_FUNC_MODE)
#define    PORT158_FlexCAN_4_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT158_SPI_3_CS2_3        (PORT_ALT3_FUNC_MODE)
#define    PORT158_FlexCAN_6_TX        (PORT_ALT4_FUNC_MODE)
#define    PORT158_EMIOS1_E1UC_14_H_OUT        (PORT_ALT6_FUNC_MODE)
#define    PORT158_EMIOS1_E1UC_14_H_IN        (PORT_INPUT1_MODE)
#define    PORT158_EMIOS1_E1UC_14_H_IN_OUT        (PORT_INOUT6_MODE)
[!ENDVAR!]




[!VAR "PinAbstractionModes_3"!]

#define    PORT0_GPIO        (PORT_GPIO_MODE)
#define    PORT0_EMIOS0_E0UC_0_X_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT0_CGM_CLKOUT0        (PORT_ALT2_FUNC_MODE)
#define    PORT0_EMIOS0_E0UC_13_H_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT0_WKPU_WKPU_19        (PORT_ONLY_INPUT_MODE)
#define    PORT0_EMIOS0_E0UC_0_X_IN        (PORT_INPUT1_MODE)
#define    PORT0_EMIOS0_E0UC_13_H_IN        (PORT_INPUT2_MODE)
#define    PORT0_EMIOS0_E0UC_0_X_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT0_EMIOS0_E0UC_13_H_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT0_FlexCAN_1_RX        (PORT_INPUT3_MODE)
#define    PORT1_GPIO        (PORT_GPIO_MODE)
#define    PORT1_EMIOS0_E0UC_1_G_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT1_WKPU_WKPU_2        (PORT_ONLY_INPUT_MODE)
#define    PORT1_WKPU_NMI_0        (PORT_ONLY_INPUT_MODE)
#define    PORT1_EMIOS0_E0UC_1_G_IN        (PORT_INPUT1_MODE)
#define    PORT1_FlexCAN_3_RX        (PORT_INPUT2_MODE)
#define    PORT1_EMIOS0_E0UC_1_G_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT2_GPIO        (PORT_GPIO_MODE)
#define    PORT2_EMIOS0_E0UC_2_G_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT2_ADC_0_ADC0_MA_2        (PORT_ALT3_FUNC_MODE)
#define    PORT2_WKPU_WKPU_3        (PORT_ONLY_INPUT_MODE)
#define    PORT2_EMIOS0_E0UC_2_G_IN        (PORT_INPUT1_MODE)
#define    PORT2_EMIOS0_E0UC_2_G_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT3_GPIO        (PORT_GPIO_MODE)
#define    PORT3_EMIOS0_E0UC_3_G_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT3_LIN_5_LIN5TX        (PORT_ALT2_FUNC_MODE)
#define    PORT3_DSPI_1_dCS4        (PORT_ALT3_FUNC_MODE)
#define    PORT3_ADC_1_ADC1_S_0        (PORT_ANALOG_INPUT_MODE)
#define    PORT3_EMIOS0_E0UC_3_G_IN        (PORT_INPUT1_MODE)
#define    PORT3_SIUL2_EIRQ0        (PORT_INPUT2_MODE)
#define    PORT3_ENET0_MII_0_RX_CLK        (PORT_INPUT3_MODE)
#define    PORT3_EMIOS0_E0UC_3_G_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT4_GPIO        (PORT_GPIO_MODE)
#define    PORT4_EMIOS0_E0UC_4_G_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT4_DSPI_1_dCS0        (PORT_ALT2_FUNC_MODE)
#define    PORT4_EMIOS0_E0UC_24_X_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT4_WKPU_WKPU_9        (PORT_ONLY_INPUT_MODE)
#define    PORT4_CMP1_CMP1_13        (PORT_ANALOG_INPUT_MODE)
#define    PORT4_EMIOS0_E0UC_4_G_IN        (PORT_INPUT1_MODE)
#define    PORT4_LIN_5_LIN5RX        (PORT_INPUT2_MODE)
#define    PORT4_DSPI_1_dSS        (PORT_INPUT3_MODE)
#define    PORT4_EMIOS0_E0UC_24_X_IN        (PORT_INPUT4_MODE)
#define    PORT4_EMIOS0_E0UC_4_G_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT4_EMIOS0_E0UC_24_X_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT5_GPIO        (PORT_GPIO_MODE)
#define    PORT5_EMIOS0_E0UC_5_G_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT5_LIN_4_LIN4TX        (PORT_ALT2_FUNC_MODE)
#define    PORT5_EMIOS0_E0UC_5_G_IN        (PORT_INPUT1_MODE)
#define    PORT5_EMIOS0_E0UC_5_G_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT6_GPIO        (PORT_GPIO_MODE)
#define    PORT6_EMIOS0_E0UC_6_G_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT6_DSPI_1_dCS1        (PORT_ALT2_FUNC_MODE)
#define    PORT6_EMIOS0_E0UC_6_G_IN        (PORT_INPUT1_MODE)
#define    PORT6_SIUL2_EIRQ1        (PORT_INPUT2_MODE)
#define    PORT6_LIN_4_LIN4RX        (PORT_INPUT3_MODE)
#define    PORT6_EMIOS0_E0UC_6_G_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT7_GPIO        (PORT_GPIO_MODE)
#define    PORT7_EMIOS0_E0UC_7_G_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT7_LIN_3_LIN3TX        (PORT_ALT2_FUNC_MODE)
#define    PORT7_ADC_1_ADC1_S_8        (PORT_ANALOG_INPUT_MODE)
#define    PORT7_EMIOS0_E0UC_7_G_IN        (PORT_INPUT1_MODE)
#define    PORT7_SIUL2_EIRQ2        (PORT_INPUT2_MODE)
#define    PORT7_ENET0_MII_0_RXD_2        (PORT_INPUT3_MODE)
#define    PORT7_EMIOS0_E0UC_7_G_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT8_GPIO        (PORT_GPIO_MODE)
#define    PORT8_EMIOS0_E0UC_8_X_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT8_EMIOS0_E0UC_14_H_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT8_ADC_1_ADC1_S_9        (PORT_ANALOG_INPUT_MODE)
#define    PORT8_EMIOS0_E0UC_8_X_IN        (PORT_INPUT1_MODE)
#define    PORT8_EMIOS0_E0UC_14_H_IN        (PORT_INPUT2_MODE)
#define    PORT8_SIUL2_EIRQ3        (PORT_INPUT3_MODE)
#define    PORT8_LIN_3_LIN3RX        (PORT_INPUT4_MODE)
#define    PORT8_ENET0_MII_RMII_0_RXD_1        (PORT_INPUT5_MODE)
#define    PORT8_EMIOS0_E0UC_8_X_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT8_EMIOS0_E0UC_14_H_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT9_GPIO        (PORT_GPIO_MODE)
#define    PORT9_EMIOS0_E0UC_9_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT9_DSPI_1_dCS2        (PORT_ALT2_FUNC_MODE)
#define    PORT9_ADC_1_ADC1_S_10        (PORT_ANALOG_INPUT_MODE)
#define    PORT9_EMIOS0_E0UC_9_H_IN        (PORT_INPUT1_MODE)
#define    PORT9_ENET0_MII_RMII_0_RXD_0        (PORT_INPUT2_MODE)
#define    PORT9_EMIOS0_E0UC_9_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT10_GPIO        (PORT_GPIO_MODE)
#define    PORT10_EMIOS0_E0UC_10_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT10_IIC_0_SDA0_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT10_LIN_2_LIN2TX        (PORT_ALT3_FUNC_MODE)
#define    PORT10_ADC_1_ADC1_S_11        (PORT_ANALOG_INPUT_MODE)
#define    PORT10_EMIOS0_E0UC_10_H_IN        (PORT_INPUT1_MODE)
#define    PORT10_IIC_0_SDA0_IN        (PORT_INPUT2_MODE)
#define    PORT10_DSPI_1_dSIN        (PORT_INPUT3_MODE)
#define    PORT10_ENET0_MII_0_COL        (PORT_INPUT4_MODE)
#define    PORT10_EMIOS0_E0UC_10_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT10_IIC_0_SDA0_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT11_GPIO        (PORT_GPIO_MODE)
#define    PORT11_EMIOS0_E0UC_11_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT11_IIC_0_SCL0_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT11_ADC_1_ADC1_S_12        (PORT_ANALOG_INPUT_MODE)
#define    PORT11_EMIOS0_E0UC_11_H_IN        (PORT_INPUT1_MODE)
#define    PORT11_SIUL2_EIRQ16        (PORT_INPUT2_MODE)
#define    PORT11_LIN_2_LIN2RX        (PORT_INPUT3_MODE)
#define    PORT11_IIC_0_SCL0_IN        (PORT_INPUT4_MODE)
#define    PORT11_ENET0_MII_RMII_0_RX_ER        (PORT_INPUT5_MODE)
#define    PORT11_EMIOS0_E0UC_11_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT11_IIC_0_SCL0_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT12_GPIO        (PORT_GPIO_MODE)
#define    PORT12_EMIOS0_E0UC_28_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT12_DSPI_1_dCS3        (PORT_ALT2_FUNC_MODE)
#define    PORT12_EMIOS0_E0UC_26_Y_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT12_CMP1_CMP1_15        (PORT_ANALOG_INPUT_MODE)
#define    PORT12_EMIOS0_E0UC_28_Y_IN        (PORT_INPUT1_MODE)
#define    PORT12_SIUL2_EIRQ17        (PORT_INPUT2_MODE)
#define    PORT12_DSPI_0_dSIN        (PORT_INPUT3_MODE)
#define    PORT12_EMIOS0_E0UC_26_Y_IN        (PORT_INPUT4_MODE)
#define    PORT12_GLITCH_FILTER0_INP        (PORT_INPUT5_MODE)
#define    PORT12_EMIOS0_E0UC_28_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT12_EMIOS0_E0UC_26_Y_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT13_GPIO        (PORT_GPIO_MODE)
#define    PORT13_DSPI_0_dSOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT13_EMIOS0_E0UC_29_Y_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT13_FlexCAN_0_TX        (PORT_ALT4_FUNC_MODE)
#define    PORT13_EMIOS0_E0UC_25_Y_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT13_CMP1_CMP1_14        (PORT_ANALOG_INPUT_MODE)
#define    PORT13_EMIOS0_E0UC_29_Y_IN        (PORT_INPUT1_MODE)
#define    PORT13_EMIOS0_E0UC_25_Y_IN        (PORT_INPUT2_MODE)
#define    PORT13_GLITCH_FILTER0_INP        (PORT_INPUT3_MODE)
#define    PORT13_EMIOS0_E0UC_29_Y_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT13_EMIOS0_E0UC_25_Y_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT14_GPIO        (PORT_GPIO_MODE)
#define    PORT14_DSPI_0_dSCLK_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT14_DSPI_0_dCS0        (PORT_ALT2_FUNC_MODE)
#define    PORT14_EMIOS0_E0UC_0_X_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT14_EMIOS0_E0UC_23_X_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT14_CMP1_CMP1_12        (PORT_ANALOG_INPUT_MODE)
#define    PORT14_EMIOS0_E0UC_0_X_IN        (PORT_INPUT1_MODE)
#define    PORT14_SIUL2_EIRQ4        (PORT_INPUT2_MODE)
#define    PORT14_DSPI_0_dSCLK_IN        (PORT_INPUT3_MODE)
#define    PORT14_DSPI_0_dSS        (PORT_INPUT4_MODE)
#define    PORT14_EMIOS0_E0UC_23_X_IN        (PORT_INPUT5_MODE)
#define    PORT14_DSPI_0_dSCLK_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT14_EMIOS0_E0UC_0_X_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT14_EMIOS0_E0UC_23_X_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT15_GPIO        (PORT_GPIO_MODE)
#define    PORT15_DSPI_0_dCS0        (PORT_ALT1_FUNC_MODE)
#define    PORT15_DSPI_0_dSCLK_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT15_EMIOS0_E0UC_1_G_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT15_EMIOS0_E0UC_21_Y_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT15_WKPU_WKPU_10        (PORT_ONLY_INPUT_MODE)
#define    PORT15_CMP1_CMP1_10        (PORT_ANALOG_INPUT_MODE)
#define    PORT15_EMIOS0_E0UC_1_G_IN        (PORT_INPUT1_MODE)
#define    PORT15_FlexCAN_0_RX        (PORT_INPUT2_MODE)
#define    PORT15_DSPI_0_dSCLK_IN        (PORT_INPUT3_MODE)
#define    PORT15_DSPI_0_dSS        (PORT_INPUT4_MODE)
#define    PORT15_EMIOS0_E0UC_21_Y_IN        (PORT_INPUT5_MODE)
#define    PORT15_DSPI_0_dSCLK_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT15_EMIOS0_E0UC_1_G_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT15_EMIOS0_E0UC_21_Y_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT16_GPIO        (PORT_GPIO_MODE)
#define    PORT16_FlexCAN_0_TX        (PORT_ALT1_FUNC_MODE)
#define    PORT16_EMIOS0_E0UC_30_Y_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT16_LIN_0_LIN0TX        (PORT_ALT3_FUNC_MODE)
#define    PORT16_EMIOS0_E0UC_4_G_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT16_CMP0_CMP0_2        (PORT_ANALOG_INPUT_MODE)
#define    PORT16_EMIOS0_E0UC_30_Y_IN        (PORT_INPUT1_MODE)
#define    PORT16_EMIOS0_E0UC_4_G_IN        (PORT_INPUT2_MODE)
#define    PORT16_GLITCH_FILTER1_INP        (PORT_INPUT3_MODE)
#define    PORT16_EMIOS0_E0UC_30_Y_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT16_EMIOS0_E0UC_4_G_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT17_GPIO        (PORT_GPIO_MODE)
#define    PORT17_EMIOS0_E0UC_31_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT17_EMIOS0_E0UC_5_G_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT17_WKPU_WKPU_4        (PORT_ONLY_INPUT_MODE)
#define    PORT17_CMP0_CMP0_3        (PORT_ANALOG_INPUT_MODE)
#define    PORT17_EMIOS0_E0UC_31_Y_IN        (PORT_INPUT1_MODE)
#define    PORT17_FlexCAN_0_RX        (PORT_INPUT2_MODE)
#define    PORT17_LIN_0_LIN0RX        (PORT_INPUT3_MODE)
#define    PORT17_EMIOS0_E0UC_5_G_IN        (PORT_INPUT4_MODE)
#define    PORT17_GLITCH_FILTER1_INP        (PORT_INPUT5_MODE)
#define    PORT17_EMIOS0_E0UC_31_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT17_EMIOS0_E0UC_5_G_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT18_GPIO        (PORT_GPIO_MODE)
#define    PORT18_LIN_0_LIN0TX        (PORT_ALT1_FUNC_MODE)
#define    PORT18_IIC_0_SDA0_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT18_EMIOS0_E0UC_30_Y_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT18_EMIOS0_E0UC_30_Y_IN        (PORT_INPUT1_MODE)
#define    PORT18_IIC_0_SDA0_IN        (PORT_INPUT2_MODE)
#define    PORT18_GLITCH_FILTER1_INP        (PORT_INPUT3_MODE)
#define    PORT18_IIC_0_SDA0_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT18_EMIOS0_E0UC_30_Y_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT19_GPIO        (PORT_GPIO_MODE)
#define    PORT19_EMIOS0_E0UC_31_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT19_IIC_0_SCL0_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT19_EMIOS0_E0UC_8_X_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT19_WKPU_WKPU_11        (PORT_ONLY_INPUT_MODE)
#define    PORT19_EMIOS0_E0UC_31_Y_IN        (PORT_INPUT1_MODE)
#define    PORT19_LIN_0_LIN0RX        (PORT_INPUT2_MODE)
#define    PORT19_IIC_0_SCL0_IN        (PORT_INPUT3_MODE)
#define    PORT19_EMIOS0_E0UC_8_X_IN        (PORT_INPUT4_MODE)
#define    PORT19_GLITCH_FILTER1_INP        (PORT_INPUT5_MODE)
#define    PORT19_EMIOS0_E0UC_31_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT19_IIC_0_SCL0_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT19_EMIOS0_E0UC_8_X_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT20_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT20_ADC_1_ADC1_P_0        (PORT_ANALOG_INPUT_MODE)
#define    PORT21_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT21_ADC_1_ADC1_P_1        (PORT_ANALOG_INPUT_MODE)
#define    PORT22_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT22_ADC_1_ADC1_P_2        (PORT_ANALOG_INPUT_MODE)
#define    PORT23_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT23_ADC_1_ADC1_P_3        (PORT_ANALOG_INPUT_MODE)
#define    PORT24_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT24_ADC_0_ADC0_S_0        (PORT_ANALOG_INPUT_MODE)
#define    PORT24_WKPU_WKPU_25        (PORT_ONLY_INPUT_MODE)
#define    PORT24_XOSC_OSC32K_XTAL        (PORT_ONLY_INPUT_MODE)
#define    PORT25_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT25_ADC_0_ADC0_S_1        (PORT_ANALOG_INPUT_MODE)
#define    PORT25_WKPU_WKPU_26        (PORT_ONLY_INPUT_MODE)
#define    PORT25_XOSC_OSC32K_EXTAL        (PORT_ONLY_INPUT_MODE)
#define    PORT26_GPIO        (PORT_GPIO_MODE)
#define    PORT26_DSPI_1_dSOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT26_FlexCAN_3_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT26_CMP2_CMP2_O        (PORT_ALT3_FUNC_MODE)
#define    PORT26_SAI0_SAI0_SYNC_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT26_EMIOS0_E0UC_29_Y_OUT        (PORT_ALT5_FUNC_MODE)
#define    PORT26_ADC_0_ADC0_S_2        (PORT_ANALOG_INPUT_MODE)
#define    PORT26_WKPU_WKPU_8        (PORT_ONLY_INPUT_MODE)
#define    PORT26_FlexCAN_6_RX        (PORT_INPUT1_MODE)
#define    PORT26_SAI0_SAI0_SYNC_IN        (PORT_INPUT2_MODE)
#define    PORT26_EMIOS0_E0UC_29_Y_IN        (PORT_INPUT3_MODE)
#define    PORT26_SAI0_SAI0_SYNC_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT26_EMIOS0_E0UC_29_Y_IN_OUT        (PORT_INOUT5_MODE)
#define    PORT27_GPIO        (PORT_GPIO_MODE)
#define    PORT27_EMIOS0_E0UC_3_G_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT27_DSPI_0_dCS0        (PORT_ALT2_FUNC_MODE)
#define    PORT27_ADC_0_ADC0_S_3        (PORT_ANALOG_INPUT_MODE)
#define    PORT27_EMIOS0_E0UC_3_G_IN        (PORT_INPUT1_MODE)
#define    PORT27_DSPI_0_dSS        (PORT_INPUT2_MODE)
#define    PORT27_EMIOS0_E0UC_3_G_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT28_GPIO        (PORT_GPIO_MODE)
#define    PORT28_EMIOS0_E0UC_4_G_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT28_DSPI_0_dCS1        (PORT_ALT2_FUNC_MODE)
#define    PORT28_HSM_DO1        (PORT_ALT3_FUNC_MODE)
#define    PORT28_ADC_0_ADC0_X_0        (PORT_ANALOG_INPUT_MODE)
#define    PORT28_EMIOS0_E0UC_4_G_IN        (PORT_INPUT1_MODE)
#define    PORT28_EMIOS0_E0UC_4_G_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT29_GPIO        (PORT_GPIO_MODE)
#define    PORT29_EMIOS0_E0UC_5_G_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT29_DSPI_0_dCS2        (PORT_ALT2_FUNC_MODE)
#define    PORT29_ADC_0_ADC0_X_1        (PORT_ANALOG_INPUT_MODE)
#define    PORT29_EMIOS0_E0UC_5_G_IN        (PORT_INPUT1_MODE)
#define    PORT29_EMIOS0_E0UC_5_G_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT30_GPIO        (PORT_GPIO_MODE)
#define    PORT30_EMIOS0_E0UC_6_G_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT30_DSPI_0_dCS3        (PORT_ALT2_FUNC_MODE)
#define    PORT30_FlexRay_FR_DBG_1        (PORT_ALT3_FUNC_MODE)
#define    PORT30_ADC_0_ADC0_X_2        (PORT_ANALOG_INPUT_MODE)
#define    PORT30_EMIOS0_E0UC_6_G_IN        (PORT_INPUT1_MODE)
#define    PORT30_EMIOS0_E0UC_6_G_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT31_GPIO        (PORT_GPIO_MODE)
#define    PORT31_EMIOS0_E0UC_7_G_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT31_DSPI_0_dCS4        (PORT_ALT2_FUNC_MODE)
#define    PORT31_ADC_0_ADC0_X_3        (PORT_ANALOG_INPUT_MODE)
#define    PORT31_EMIOS0_E0UC_7_G_IN        (PORT_INPUT1_MODE)
#define    PORT31_EMIOS0_E0UC_7_G_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT32_GPIO        (PORT_GPIO_MODE)
#define    PORT32_DCI_TDI        (PORT_ALT1_FUNC_MODE)
#define    PORT33_GPIO        (PORT_GPIO_MODE)
#define    PORT33_DCI_TDO        (PORT_ALT1_FUNC_MODE)
#define    PORT34_GPIO        (PORT_GPIO_MODE)
#define    PORT34_DSPI_1_dSCLK_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT34_FlexCAN_4_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT34_SSCM_SSCM_DBG_0        (PORT_ALT4_FUNC_MODE)
#define    PORT34_SIUL2_EIRQ5        (PORT_INPUT1_MODE)
#define    PORT34_DSPI_1_dSCLK_IN        (PORT_INPUT2_MODE)
#define    PORT34_DSPI_1_dSCLK_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT35_GPIO        (PORT_GPIO_MODE)
#define    PORT35_DSPI_1_dCS0        (PORT_ALT1_FUNC_MODE)
#define    PORT35_ADC_0_ADC0_MA_0        (PORT_ALT2_FUNC_MODE)
#define    PORT35_SSCM_SSCM_DBG_1        (PORT_ALT4_FUNC_MODE)
#define    PORT35_SIUL2_EIRQ6        (PORT_INPUT1_MODE)
#define    PORT35_FlexCAN_1_RX        (PORT_INPUT2_MODE)
#define    PORT35_FlexCAN_4_RX        (PORT_INPUT3_MODE)
#define    PORT35_DSPI_1_dSS        (PORT_INPUT4_MODE)
#define    PORT36_GPIO        (PORT_GPIO_MODE)
#define    PORT36_EMIOS1_E1UC_31_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT36_FlexRay_FR_B_TX_EN        (PORT_ALT2_FUNC_MODE)
#define    PORT36_SSCM_SSCM_DBG_2        (PORT_ALT5_FUNC_MODE)
#define    PORT36_EMIOS1_E1UC_31_Y_IN        (PORT_INPUT1_MODE)
#define    PORT36_SIUL2_EIRQ18        (PORT_INPUT2_MODE)
#define    PORT36_FlexCAN_3_RX        (PORT_INPUT3_MODE)
#define    PORT36_DSPI_1_dSIN        (PORT_INPUT4_MODE)
#define    PORT36_GLITCH_FILTER3_INP        (PORT_INPUT5_MODE)
#define    PORT36_EMIOS1_E1UC_31_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT37_GPIO        (PORT_GPIO_MODE)
#define    PORT37_DSPI_1_dSOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT37_FlexCAN_3_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT37_FlexRay_FR_A_TX        (PORT_ALT4_FUNC_MODE)
#define    PORT37_SSCM_SSCM_DBG_3        (PORT_ALT7_FUNC_MODE)
#define    PORT37_SIUL2_EIRQ7        (PORT_INPUT1_MODE)
#define    PORT38_GPIO        (PORT_GPIO_MODE)
#define    PORT38_LIN_1_LIN1TX        (PORT_ALT1_FUNC_MODE)
#define    PORT38_EMIOS1_E1UC_28_Y_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT38_SSCM_SSCM_DBG_4        (PORT_ALT4_FUNC_MODE)
#define    PORT38_EMIOS0_E0UC_17_Y_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT38_CMP0_CMP0_7        (PORT_ANALOG_INPUT_MODE)
#define    PORT38_EMIOS1_E1UC_28_Y_IN        (PORT_INPUT1_MODE)
#define    PORT38_EMIOS0_E0UC_17_Y_IN        (PORT_INPUT2_MODE)
#define    PORT38_GLITCH_FILTER2_INP        (PORT_INPUT3_MODE)
#define    PORT38_EMIOS1_E1UC_28_Y_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT38_EMIOS0_E0UC_17_Y_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT39_GPIO        (PORT_GPIO_MODE)
#define    PORT39_EMIOS1_E1UC_29_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT39_CMP1_CMP1_O        (PORT_ALT2_FUNC_MODE)
#define    PORT39_SSCM_SSCM_DBG_5        (PORT_ALT4_FUNC_MODE)
#define    PORT39_EMIOS0_E0UC_18_Y_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT39_WKPU_WKPU_12        (PORT_ONLY_INPUT_MODE)
#define    PORT39_EMIOS1_E1UC_29_Y_IN        (PORT_INPUT1_MODE)
#define    PORT39_LIN_1_LIN1RX        (PORT_INPUT2_MODE)
#define    PORT39_EMIOS0_E0UC_18_Y_IN        (PORT_INPUT3_MODE)
#define    PORT39_GLITCH_FILTER2_INP        (PORT_INPUT4_MODE)
#define    PORT39_EMIOS1_E1UC_29_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT39_EMIOS0_E0UC_18_Y_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT40_GPIO        (PORT_GPIO_MODE)
#define    PORT40_LIN_2_LIN2TX        (PORT_ALT1_FUNC_MODE)
#define    PORT40_EMIOS0_E0UC_3_G_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT40_SSCM_SSCM_DBG_6        (PORT_ALT4_FUNC_MODE)
#define    PORT40_EMIOS0_E0UC_3_G_IN        (PORT_INPUT1_MODE)
#define    PORT40_EMIOS0_E0UC_3_G_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT41_GPIO        (PORT_GPIO_MODE)
#define    PORT41_EMIOS0_E0UC_7_G_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT41_SSCM_SSCM_DBG_7        (PORT_ALT3_FUNC_MODE)
#define    PORT41_WKPU_WKPU_13        (PORT_ONLY_INPUT_MODE)
#define    PORT41_EMIOS0_E0UC_7_G_IN        (PORT_INPUT1_MODE)
#define    PORT41_LIN_2_LIN2RX        (PORT_INPUT2_MODE)
#define    PORT41_EMIOS0_E0UC_7_G_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT42_GPIO        (PORT_GPIO_MODE)
#define    PORT42_FlexCAN_1_TX        (PORT_ALT1_FUNC_MODE)
#define    PORT42_FlexCAN_4_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT42_ADC_0_ADC0_MA_1        (PORT_ALT3_FUNC_MODE)
#define    PORT42_CMP0_CMP0_O        (PORT_ALT4_FUNC_MODE)
#define    PORT42_LIN_6_LIN6TX        (PORT_ALT6_FUNC_MODE)
#define    PORT43_GPIO        (PORT_GPIO_MODE)
#define    PORT43_ADC_0_ADC0_MA_2        (PORT_ALT1_FUNC_MODE)
#define    PORT43_EMIOS0_E0UC_1_G_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT43_WKPU_WKPU_5        (PORT_ONLY_INPUT_MODE)
#define    PORT43_FlexCAN_1_RX        (PORT_INPUT1_MODE)
#define    PORT43_FlexCAN_4_RX        (PORT_INPUT2_MODE)
#define    PORT43_EMIOS0_E0UC_1_G_IN        (PORT_INPUT3_MODE)
#define    PORT43_EMIOS0_E0UC_1_G_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT44_GPIO        (PORT_GPIO_MODE)
#define    PORT44_EMIOS0_E0UC_12_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT44_FlexRay_FR_DBG_0        (PORT_ALT2_FUNC_MODE)
#define    PORT44_EMIOS0_E0UC_12_H_IN        (PORT_INPUT1_MODE)
#define    PORT44_SIUL2_EIRQ19        (PORT_INPUT2_MODE)
#define    PORT44_DSPI_2_dSIN        (PORT_INPUT3_MODE)
#define    PORT44_EMIOS0_E0UC_12_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT45_GPIO        (PORT_GPIO_MODE)
#define    PORT45_EMIOS0_E0UC_13_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT45_DSPI_2_dSOUT        (PORT_ALT2_FUNC_MODE)
#define    PORT45_FlexRay_FR_DBG_1        (PORT_ALT3_FUNC_MODE)
#define    PORT45_EMIOS0_E0UC_13_H_IN        (PORT_INPUT1_MODE)
#define    PORT45_EMIOS0_E0UC_13_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT46_GPIO        (PORT_GPIO_MODE)
#define    PORT46_EMIOS0_E0UC_14_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT46_DSPI_2_dSCLK_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT46_FlexRay_FR_DBG_2        (PORT_ALT4_FUNC_MODE)
#define    PORT46_FlexCAN_4_TX        (PORT_ALT5_FUNC_MODE)
#define    PORT46_EMIOS0_E0UC_14_H_IN        (PORT_INPUT1_MODE)
#define    PORT46_SIUL2_EIRQ8        (PORT_INPUT2_MODE)
#define    PORT46_DSPI_2_dSCLK_IN        (PORT_INPUT3_MODE)
#define    PORT46_EMIOS0_E0UC_14_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT46_DSPI_2_dSCLK_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT47_GPIO        (PORT_GPIO_MODE)
#define    PORT47_EMIOS0_E0UC_15_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT47_DSPI_2_dCS0        (PORT_ALT2_FUNC_MODE)
#define    PORT47_FlexRay_FR_DBG_3        (PORT_ALT4_FUNC_MODE)
#define    PORT47_EMIOS0_E0UC_15_H_IN        (PORT_INPUT1_MODE)
#define    PORT47_SIUL2_EIRQ20        (PORT_INPUT2_MODE)
#define    PORT47_DSPI_2_dSS        (PORT_INPUT3_MODE)
#define    PORT47_FlexCAN_4_RX        (PORT_INPUT4_MODE)
#define    PORT47_EMIOS0_E0UC_15_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT48_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT48_ADC_1_ADC1_P_4        (PORT_ANALOG_INPUT_MODE)
#define    PORT48_WKPU_WKPU_27        (PORT_ONLY_INPUT_MODE)
#define    PORT49_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT49_ADC_1_ADC1_P_5        (PORT_ANALOG_INPUT_MODE)
#define    PORT49_WKPU_WKPU_28        (PORT_ONLY_INPUT_MODE)
#define    PORT50_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT50_ADC_1_ADC1_P_6        (PORT_ANALOG_INPUT_MODE)
#define    PORT51_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT51_ADC_1_ADC1_P_7        (PORT_ANALOG_INPUT_MODE)
#define    PORT52_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT52_ADC_1_ADC1_P_8        (PORT_ANALOG_INPUT_MODE)
#define    PORT53_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT53_ADC_1_ADC1_P_9        (PORT_ANALOG_INPUT_MODE)
#define    PORT54_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT54_ADC_1_ADC1_P_10        (PORT_ANALOG_INPUT_MODE)
#define    PORT55_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT55_ADC_1_ADC1_P_11        (PORT_ANALOG_INPUT_MODE)
#define    PORT56_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT56_ADC_1_ADC1_P_12        (PORT_ANALOG_INPUT_MODE)
#define    PORT57_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT57_ADC_1_ADC1_P_13        (PORT_ANALOG_INPUT_MODE)
#define    PORT58_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT58_ADC_1_ADC1_P_14        (PORT_ANALOG_INPUT_MODE)
#define    PORT59_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT59_ADC_1_ADC1_P_15        (PORT_ANALOG_INPUT_MODE)
#define    PORT60_GPIO        (PORT_GPIO_MODE)
#define    PORT60_DSPI_0_dCS5        (PORT_ALT1_FUNC_MODE)
#define    PORT60_EMIOS0_E0UC_24_X_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT60_HSM_DO0        (PORT_ALT3_FUNC_MODE)
#define    PORT60_ADC_0_ADC0_S_4        (PORT_ANALOG_INPUT_MODE)
#define    PORT60_EMIOS0_E0UC_24_X_IN        (PORT_INPUT1_MODE)
#define    PORT60_EMIOS0_E0UC_24_X_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT61_GPIO        (PORT_GPIO_MODE)
#define    PORT61_DSPI_1_dCS0        (PORT_ALT1_FUNC_MODE)
#define    PORT61_EMIOS0_E0UC_25_Y_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT61_ENET0_ENET0_TMR0_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT61_ADC_0_ADC0_S_5        (PORT_ANALOG_INPUT_MODE)
#define    PORT61_EMIOS0_E0UC_25_Y_IN        (PORT_INPUT1_MODE)
#define    PORT61_DSPI_1_dSS        (PORT_INPUT2_MODE)
#define    PORT61_ENET0_ENET0_TMR0_IN        (PORT_INPUT3_MODE)
#define    PORT61_EMIOS0_E0UC_25_Y_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT61_ENET0_ENET0_TMR0_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT62_GPIO        (PORT_GPIO_MODE)
#define    PORT62_DSPI_1_dCS1        (PORT_ALT1_FUNC_MODE)
#define    PORT62_EMIOS0_E0UC_26_Y_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT62_FlexRay_FR_DBG_0        (PORT_ALT3_FUNC_MODE)
#define    PORT62_ADC_0_ADC0_S_6        (PORT_ANALOG_INPUT_MODE)
#define    PORT62_EMIOS0_E0UC_26_Y_IN        (PORT_INPUT1_MODE)
#define    PORT62_EMIOS0_E0UC_26_Y_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT63_GPIO        (PORT_GPIO_MODE)
#define    PORT63_DSPI_1_dCS2        (PORT_ALT1_FUNC_MODE)
#define    PORT63_EMIOS0_E0UC_27_Y_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT63_FlexRay_FR_DBG_1        (PORT_ALT3_FUNC_MODE)
#define    PORT63_ADC_0_ADC0_S_7        (PORT_ANALOG_INPUT_MODE)
#define    PORT63_EMIOS0_E0UC_27_Y_IN        (PORT_INPUT1_MODE)
#define    PORT63_EMIOS0_E0UC_27_Y_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT64_GPIO        (PORT_GPIO_MODE)
#define    PORT64_EMIOS0_E0UC_16_X_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT64_IIC_1_SCL1_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT64_WKPU_WKPU_6        (PORT_ONLY_INPUT_MODE)
#define    PORT64_EMIOS0_E0UC_16_X_IN        (PORT_INPUT1_MODE)
#define    PORT64_FlexCAN_5_RX        (PORT_INPUT2_MODE)
#define    PORT64_LIN_11_LIN11RX        (PORT_INPUT3_MODE)
#define    PORT64_IIC_1_SCL1_IN        (PORT_INPUT4_MODE)
#define    PORT64_EMIOS0_E0UC_16_X_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT64_IIC_1_SCL1_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT65_GPIO        (PORT_GPIO_MODE)
#define    PORT65_EMIOS0_E0UC_17_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT65_FlexCAN_5_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT65_IIC_1_SDA1_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT65_EMIOS0_E0UC_17_Y_IN        (PORT_INPUT1_MODE)
#define    PORT65_IIC_1_SDA1_IN        (PORT_INPUT2_MODE)
#define    PORT65_EMIOS0_E0UC_17_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT65_IIC_1_SDA1_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT66_GPIO        (PORT_GPIO_MODE)
#define    PORT66_EMIOS0_E0UC_18_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT66_FlexRay_FR_A_TX_EN        (PORT_ALT2_FUNC_MODE)
#define    PORT66_EMIOS0_E0UC_18_Y_IN        (PORT_INPUT1_MODE)
#define    PORT66_SIUL2_EIRQ21        (PORT_INPUT2_MODE)
#define    PORT66_DSPI_1_dSIN        (PORT_INPUT3_MODE)
#define    PORT66_EMIOS0_E0UC_18_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT67_GPIO        (PORT_GPIO_MODE)
#define    PORT67_EMIOS0_E0UC_19_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT67_DSPI_1_dSOUT        (PORT_ALT2_FUNC_MODE)
#define    PORT67_WKPU_WKPU_29        (PORT_ONLY_INPUT_MODE)
#define    PORT67_EMIOS0_E0UC_19_Y_IN        (PORT_INPUT1_MODE)
#define    PORT67_FlexRay_FR_A_RX        (PORT_INPUT2_MODE)
#define    PORT67_EMIOS0_E0UC_19_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT68_GPIO        (PORT_GPIO_MODE)
#define    PORT68_EMIOS0_E0UC_20_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT68_DSPI_1_dSCLK_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT68_FlexRay_FR_B_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT68_EMIOS0_E0UC_20_Y_IN        (PORT_INPUT1_MODE)
#define    PORT68_SIUL2_EIRQ9        (PORT_INPUT2_MODE)
#define    PORT68_DSPI_1_dSCLK_IN        (PORT_INPUT3_MODE)
#define    PORT68_EMIOS0_E0UC_20_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT68_DSPI_1_dSCLK_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT69_GPIO        (PORT_GPIO_MODE)
#define    PORT69_EMIOS0_E0UC_21_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT69_DSPI_1_dCS0        (PORT_ALT2_FUNC_MODE)
#define    PORT69_ADC_0_ADC0_MA_2        (PORT_ALT3_FUNC_MODE)
#define    PORT69_WKPU_WKPU_30        (PORT_ONLY_INPUT_MODE)
#define    PORT69_EMIOS0_E0UC_21_Y_IN        (PORT_INPUT1_MODE)
#define    PORT69_FlexRay_FR_B_RX        (PORT_INPUT2_MODE)
#define    PORT69_DSPI_1_dSS        (PORT_INPUT3_MODE)
#define    PORT69_EMIOS0_E0UC_21_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT70_GPIO        (PORT_GPIO_MODE)
#define    PORT70_EMIOS0_E0UC_22_X_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT70_DSPI_0_dCS3        (PORT_ALT2_FUNC_MODE)
#define    PORT70_ADC_0_ADC0_MA_1        (PORT_ALT3_FUNC_MODE)
#define    PORT70_ADC_1_ADC1_MA_1        (PORT_ALT4_FUNC_MODE)
#define    PORT70_EMIOS0_E0UC_22_X_IN        (PORT_INPUT1_MODE)
#define    PORT70_SIUL2_EIRQ22        (PORT_INPUT2_MODE)
#define    PORT70_EMIOS0_E0UC_22_X_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT71_GPIO        (PORT_GPIO_MODE)
#define    PORT71_EMIOS0_E0UC_23_X_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT71_DSPI_0_dCS2        (PORT_ALT2_FUNC_MODE)
#define    PORT71_ADC_0_ADC0_MA_0        (PORT_ALT3_FUNC_MODE)
#define    PORT71_ADC_1_ADC1_MA_0        (PORT_ALT4_FUNC_MODE)
#define    PORT71_EMIOS0_E0UC_23_X_IN        (PORT_INPUT1_MODE)
#define    PORT71_SIUL2_EIRQ23        (PORT_INPUT2_MODE)
#define    PORT71_EMIOS0_E0UC_23_X_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT72_GPIO        (PORT_GPIO_MODE)
#define    PORT72_FlexCAN_2_TX        (PORT_ALT1_FUNC_MODE)
#define    PORT72_EMIOS0_E0UC_22_X_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT72_FlexCAN_3_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT72_IIC_2_SDA2_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT72_LIN_6_LIN6TX        (PORT_ALT5_FUNC_MODE)
#define    PORT72_EMIOS0_E0UC_22_X_IN        (PORT_INPUT1_MODE)
#define    PORT72_IIC_2_SDA2_IN        (PORT_INPUT2_MODE)
#define    PORT72_EMIOS0_E0UC_22_X_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT72_IIC_2_SDA2_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT73_GPIO        (PORT_GPIO_MODE)
#define    PORT73_EMIOS0_E0UC_23_X_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT73_IIC_2_SCL2_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT73_WKPU_WKPU_7        (PORT_ONLY_INPUT_MODE)
#define    PORT73_EMIOS0_E0UC_23_X_IN        (PORT_INPUT1_MODE)
#define    PORT73_FlexCAN_2_RX        (PORT_INPUT2_MODE)
#define    PORT73_FlexCAN_3_RX        (PORT_INPUT3_MODE)
#define    PORT73_IIC_2_SCL2_IN        (PORT_INPUT4_MODE)
#define    PORT73_EMIOS0_E0UC_23_X_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT73_IIC_2_SCL2_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT74_GPIO        (PORT_GPIO_MODE)
#define    PORT74_LIN_3_LIN3TX        (PORT_ALT1_FUNC_MODE)
#define    PORT74_DSPI_1_dCS3        (PORT_ALT2_FUNC_MODE)
#define    PORT74_EMIOS1_E1UC_30_Y_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT74_IIC_3_SDA3_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT74_EMIOS1_E1UC_30_Y_IN        (PORT_INPUT1_MODE)
#define    PORT74_SIUL2_EIRQ10        (PORT_INPUT2_MODE)
#define    PORT74_IIC_3_SDA3_IN        (PORT_INPUT3_MODE)
#define    PORT74_GLITCH_FILTER3_INP        (PORT_INPUT4_MODE)
#define    PORT74_EMIOS1_E1UC_30_Y_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT74_IIC_3_SDA3_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT75_GPIO        (PORT_GPIO_MODE)
#define    PORT75_EMIOS0_E0UC_24_X_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT75_DSPI_1_dCS4        (PORT_ALT2_FUNC_MODE)
#define    PORT75_CGM_CLKOUT1        (PORT_ALT3_FUNC_MODE)
#define    PORT75_IIC_3_SCL3_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT75_WKPU_WKPU_14        (PORT_ONLY_INPUT_MODE)
#define    PORT75_EMIOS0_E0UC_24_X_IN        (PORT_INPUT1_MODE)
#define    PORT75_LIN_3_LIN3RX        (PORT_INPUT2_MODE)
#define    PORT75_IIC_3_SCL3_IN        (PORT_INPUT3_MODE)
#define    PORT75_EMIOS0_E0UC_24_X_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT75_IIC_3_SCL3_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT76_GPIO        (PORT_GPIO_MODE)
#define    PORT76_EMIOS1_E1UC_19_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT76_ADC_1_ADC1_S_13        (PORT_ANALOG_INPUT_MODE)
#define    PORT76_EMIOS1_E1UC_19_Y_IN        (PORT_INPUT1_MODE)
#define    PORT76_SIUL2_EIRQ11        (PORT_INPUT2_MODE)
#define    PORT76_DSPI_2_dSIN        (PORT_INPUT3_MODE)
#define    PORT76_ENET0_MII_0_CRS        (PORT_INPUT4_MODE)
#define    PORT76_EMIOS1_E1UC_19_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT77_GPIO        (PORT_GPIO_MODE)
#define    PORT77_DSPI_2_dSOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT77_EMIOS1_E1UC_20_Y_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT77_ADC_1_ADC1_X_3        (PORT_ANALOG_INPUT_MODE)
#define    PORT77_EMIOS1_E1UC_20_Y_IN        (PORT_INPUT1_MODE)
#define    PORT77_ENET0_MII_0_RXD_3        (PORT_INPUT2_MODE)
#define    PORT77_EMIOS1_E1UC_20_Y_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT78_GPIO        (PORT_GPIO_MODE)
#define    PORT78_DSPI_2_dSCLK_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT78_EMIOS1_E1UC_21_Y_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT78_EMIOS1_E1UC_21_Y_IN        (PORT_INPUT1_MODE)
#define    PORT78_SIUL2_EIRQ12        (PORT_INPUT2_MODE)
#define    PORT78_DSPI_2_dSCLK_IN        (PORT_INPUT3_MODE)
#define    PORT78_DSPI_2_dSCLK_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT78_EMIOS1_E1UC_21_Y_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT79_GPIO        (PORT_GPIO_MODE)
#define    PORT79_DSPI_2_dCS0        (PORT_ALT1_FUNC_MODE)
#define    PORT79_EMIOS1_E1UC_22_X_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT79_SPI_2_SCLK_2_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT79_EMIOS1_E1UC_22_X_IN        (PORT_INPUT1_MODE)
#define    PORT79_DSPI_2_dSS        (PORT_INPUT2_MODE)
#define    PORT79_SPI_2_SCLK_2_IN        (PORT_INPUT3_MODE)
#define    PORT79_EMIOS1_E1UC_22_X_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT79_SPI_2_SCLK_2_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT80_GPIO        (PORT_GPIO_MODE)
#define    PORT80_EMIOS0_E0UC_10_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT80_DSPI_1_dCS3        (PORT_ALT2_FUNC_MODE)
#define    PORT80_FlexCAN_6_TX        (PORT_ALT4_FUNC_MODE)
#define    PORT80_ADC_0_ADC0_S_8        (PORT_ANALOG_INPUT_MODE)
#define    PORT80_CMP2_CMP2_16        (PORT_ANALOG_INPUT_MODE)
#define    PORT80_SAI0_SAI0_MCLK_OUT        (PORT_ALT7_FUNC_MODE)
#define    PORT80_EMIOS0_E0UC_10_H_IN        (PORT_INPUT1_MODE)
#define    PORT80_SAI0_SAI0_MCLK_IN        (PORT_INPUT2_MODE)
#define    PORT80_EMIOS0_E0UC_10_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT80_SAI0_SAI0_MCLK_IN_OUT        (PORT_INOUT7_MODE)
#define    PORT81_GPIO        (PORT_GPIO_MODE)
#define    PORT81_EMIOS0_E0UC_11_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT81_DSPI_1_dCS4        (PORT_ALT2_FUNC_MODE)
#define    PORT81_SPI_0_CS3_0        (PORT_ALT3_FUNC_MODE)
#define    PORT81_SAI0_SAI0_BCLK_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT81_ADC_0_ADC0_S_9        (PORT_ANALOG_INPUT_MODE)
#define    PORT81_CMP2_CMP2_17        (PORT_ANALOG_INPUT_MODE)
#define    PORT81_EMIOS0_E0UC_11_H_IN        (PORT_INPUT1_MODE)
#define    PORT81_SAI0_SAI0_BCLK_IN        (PORT_INPUT2_MODE)
#define    PORT81_EMIOS0_E0UC_11_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT81_SAI0_SAI0_BCLK_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT82_GPIO        (PORT_GPIO_MODE)
#define    PORT82_EMIOS0_E0UC_12_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT82_DSPI_2_dCS0        (PORT_ALT2_FUNC_MODE)
#define    PORT82_SAI0_SAI0_D3_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT82_ADC_0_ADC0_S_10        (PORT_ANALOG_INPUT_MODE)
#define    PORT82_CMP2_CMP2_18        (PORT_ANALOG_INPUT_MODE)
#define    PORT82_EMIOS0_E0UC_12_H_IN        (PORT_INPUT1_MODE)
#define    PORT82_DSPI_2_dSS        (PORT_INPUT2_MODE)
#define    PORT82_SAI0_SAI0_D3_IN        (PORT_INPUT3_MODE)
#define    PORT82_GLITCH_FILTER0_INP        (PORT_INPUT4_MODE)
#define    PORT82_EMIOS0_E0UC_12_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT82_SAI0_SAI0_D3_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT83_GPIO        (PORT_GPIO_MODE)
#define    PORT83_EMIOS0_E0UC_13_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT83_DSPI_2_dCS1        (PORT_ALT2_FUNC_MODE)
#define    PORT83_SAI0_SAI0_D2_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT83_ADC_0_ADC0_S_11        (PORT_ANALOG_INPUT_MODE)
#define    PORT83_CMP2_CMP2_19        (PORT_ANALOG_INPUT_MODE)
#define    PORT83_EMIOS0_E0UC_13_H_IN        (PORT_INPUT1_MODE)
#define    PORT83_SAI0_SAI0_D2_IN        (PORT_INPUT2_MODE)
#define    PORT83_GLITCH_FILTER1_INP        (PORT_INPUT3_MODE)
#define    PORT83_EMIOS0_E0UC_13_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT83_SAI0_SAI0_D2_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT84_GPIO        (PORT_GPIO_MODE)
#define    PORT84_EMIOS0_E0UC_14_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT84_DSPI_2_dCS2        (PORT_ALT2_FUNC_MODE)
#define    PORT84_SAI0_SAI0_D1_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT84_ADC_0_ADC0_S_12        (PORT_ANALOG_INPUT_MODE)
#define    PORT84_CMP2_CMP2_20        (PORT_ANALOG_INPUT_MODE)
#define    PORT84_EMIOS0_E0UC_14_H_IN        (PORT_INPUT1_MODE)
#define    PORT84_SAI0_SAI0_D1_IN        (PORT_INPUT2_MODE)
#define    PORT84_GLITCH_FILTER2_INP        (PORT_INPUT3_MODE)
#define    PORT84_EMIOS0_E0UC_14_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT84_SAI0_SAI0_D1_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT85_GPIO        (PORT_GPIO_MODE)
#define    PORT85_EMIOS0_E0UC_22_X_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT85_DSPI_2_dCS3        (PORT_ALT2_FUNC_MODE)
#define    PORT85_SPI_0_CS2_0        (PORT_ALT3_FUNC_MODE)
#define    PORT85_SAI0_SAI0_D0_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT85_ADC_0_ADC0_S_13        (PORT_ANALOG_INPUT_MODE)
#define    PORT85_CMP2_CMP2_21        (PORT_ANALOG_INPUT_MODE)
#define    PORT85_EMIOS0_E0UC_22_X_IN        (PORT_INPUT1_MODE)
#define    PORT85_SAI0_SAI0_D0_IN        (PORT_INPUT2_MODE)
#define    PORT85_GLITCH_FILTER3_INP        (PORT_INPUT3_MODE)
#define    PORT85_EMIOS0_E0UC_22_X_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT85_SAI0_SAI0_D0_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT86_GPIO        (PORT_GPIO_MODE)
#define    PORT86_EMIOS0_E0UC_23_X_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT86_DSPI_1_dCS1        (PORT_ALT2_FUNC_MODE)
#define    PORT86_SAI1_SAI1_SYNC_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT86_EMIOS0_E0UC_30_Y_OUT        (PORT_ALT5_FUNC_MODE)
#define    PORT86_ADC_0_ADC0_S_14        (PORT_ANALOG_INPUT_MODE)
#define    PORT86_CMP2_CMP2_22        (PORT_ANALOG_INPUT_MODE)
#define    PORT86_EMIOS0_E0UC_23_X_IN        (PORT_INPUT1_MODE)
#define    PORT86_SAI1_SAI1_SYNC_IN        (PORT_INPUT2_MODE)
#define    PORT86_EMIOS0_E0UC_30_Y_IN        (PORT_INPUT3_MODE)
#define    PORT86_EMIOS0_E0UC_23_X_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT86_SAI1_SAI1_SYNC_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT86_EMIOS0_E0UC_30_Y_IN_OUT        (PORT_INOUT5_MODE)
#define    PORT87_GPIO        (PORT_GPIO_MODE)
#define    PORT87_SPI_0_SCLK_0_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT87_DSPI_1_dCS2        (PORT_ALT2_FUNC_MODE)
#define    PORT87_ADC_0_ADC0_S_15        (PORT_ANALOG_INPUT_MODE)
#define    PORT87_CMP2_CMP2_23        (PORT_ANALOG_INPUT_MODE)
#define    PORT87_SAI1_SAI1_MCLK_OUT        (PORT_ALT6_FUNC_MODE)
#define    PORT87_SPI_0_SCLK_0_IN        (PORT_INPUT1_MODE)
#define    PORT87_SAI1_SAI1_MCLK_IN        (PORT_INPUT2_MODE)
#define    PORT87_SPI_0_SCLK_0_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT87_SAI1_SAI1_MCLK_IN_OUT        (PORT_INOUT6_MODE)
#define    PORT88_GPIO        (PORT_GPIO_MODE)
#define    PORT88_FlexCAN_3_TX        (PORT_ALT1_FUNC_MODE)
#define    PORT88_DSPI_0_dCS4        (PORT_ALT2_FUNC_MODE)
#define    PORT88_FlexCAN_2_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT88_EMIOS0_E0UC_15_H_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT88_CMP0_CMP0_5        (PORT_ANALOG_INPUT_MODE)
#define    PORT88_EMIOS0_E0UC_15_H_IN        (PORT_INPUT1_MODE)
#define    PORT88_EMIOS0_E0UC_15_H_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT89_GPIO        (PORT_GPIO_MODE)
#define    PORT89_EMIOS1_E1UC_1_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT89_DSPI_0_dCS5        (PORT_ALT2_FUNC_MODE)
#define    PORT89_EMIOS0_E0UC_14_H_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT89_WKPU_WKPU_22        (PORT_ONLY_INPUT_MODE)
#define    PORT89_CMP0_CMP0_4        (PORT_ANALOG_INPUT_MODE)
#define    PORT89_EMIOS1_E1UC_1_H_IN        (PORT_INPUT1_MODE)
#define    PORT89_FlexCAN_2_RX        (PORT_INPUT2_MODE)
#define    PORT89_FlexCAN_3_RX        (PORT_INPUT3_MODE)
#define    PORT89_EMIOS0_E0UC_14_H_IN        (PORT_INPUT4_MODE)
#define    PORT89_EMIOS1_E1UC_1_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT89_EMIOS0_E0UC_14_H_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT90_GPIO        (PORT_GPIO_MODE)
#define    PORT90_DSPI_0_dCS1        (PORT_ALT1_FUNC_MODE)
#define    PORT90_LIN_4_LIN4TX        (PORT_ALT2_FUNC_MODE)
#define    PORT90_EMIOS1_E1UC_2_H_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT90_FCCU_EOUT0_OUT        (PORT_ALT5_FUNC_MODE)
#define    PORT90_FCCU_EOUT0_IN        (PORT_ONLY_INPUT_MODE)
#define    PORT90_FCCU_EOUT0_IN_OUT        (PORT_INOUT5_MODE)
#define    PORT90_EMIOS0_E0UC_19_Y_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT90_CMP1_CMP1_8        (PORT_ANALOG_INPUT_MODE)
#define    PORT90_EMIOS1_E1UC_2_H_IN        (PORT_INPUT1_MODE)
#define    PORT90_EMIOS0_E0UC_19_Y_IN        (PORT_INPUT2_MODE)
#define    PORT90_EMIOS1_E1UC_2_H_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT90_EMIOS0_E0UC_19_Y_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT91_GPIO        (PORT_GPIO_MODE)
#define    PORT91_DSPI_0_dCS2        (PORT_ALT1_FUNC_MODE)
#define    PORT91_EMIOS1_E1UC_3_H_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT91_EMIOS0_E0UC_20_Y_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT91_WKPU_WKPU_15        (PORT_ONLY_INPUT_MODE)
#define    PORT91_CMP1_CMP1_9        (PORT_ANALOG_INPUT_MODE)
#define    PORT91_EMIOS1_E1UC_3_H_IN        (PORT_INPUT1_MODE)
#define    PORT91_LIN_4_LIN4RX        (PORT_INPUT2_MODE)
#define    PORT91_EMIOS0_E0UC_20_Y_IN        (PORT_INPUT3_MODE)
#define    PORT91_EMIOS1_E1UC_3_H_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT91_EMIOS0_E0UC_20_Y_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT92_GPIO        (PORT_GPIO_MODE)
#define    PORT92_EMIOS1_E1UC_25_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT92_LIN_5_LIN5TX        (PORT_ALT2_FUNC_MODE)
#define    PORT92_FCCU_EOUT1_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT92_FCCU_EOUT1_IN        (PORT_ONLY_INPUT_MODE)
#define    PORT92_FCCU_EOUT1_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT92_EMIOS0_E0UC_16_X_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT92_CMP0_CMP0_6        (PORT_ANALOG_INPUT_MODE)
#define    PORT92_EMIOS1_E1UC_25_Y_IN        (PORT_INPUT1_MODE)
#define    PORT92_EMIOS0_E0UC_16_X_IN        (PORT_INPUT2_MODE)
#define    PORT92_EMIOS1_E1UC_25_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT92_EMIOS0_E0UC_16_X_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT93_GPIO        (PORT_GPIO_MODE)
#define    PORT93_EMIOS1_E1UC_26_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT93_EMIOS0_E0UC_22_X_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT93_WKPU_WKPU_16        (PORT_ONLY_INPUT_MODE)
#define    PORT93_CMP1_CMP1_11        (PORT_ANALOG_INPUT_MODE)
#define    PORT93_EMIOS1_E1UC_26_Y_IN        (PORT_INPUT1_MODE)
#define    PORT93_LIN_5_LIN5RX        (PORT_INPUT2_MODE)
#define    PORT93_EMIOS0_E0UC_22_X_IN        (PORT_INPUT3_MODE)
#define    PORT93_EMIOS1_E1UC_26_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT93_EMIOS0_E0UC_22_X_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT94_GPIO        (PORT_GPIO_MODE)
#define    PORT94_FlexCAN_4_TX        (PORT_ALT1_FUNC_MODE)
#define    PORT94_EMIOS1_E1UC_27_Y_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT94_FlexCAN_1_TX        (PORT_ALT3_FUNC_MODE)
/**
* @violates @ref PORT_CFG_H_REF_1 MISRA 2004 Rule 1.4, The compiler/linker shall be checked to
*  ensure that 31 character significance and case sensitivity are supported for external ids
*/
#define    PORT94_ENET0_MII_RMII_0_MDIO_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT94_ADC_1_ADC1_X_2        (PORT_ANALOG_INPUT_MODE)
#define    PORT94_EMIOS1_E1UC_27_Y_IN        (PORT_INPUT1_MODE)
#define    PORT94_ENET0_MII_RMII_0_MDIO_IN        (PORT_INPUT2_MODE)
#define    PORT94_EMIOS1_E1UC_27_Y_IN_OUT        (PORT_INOUT2_MODE)
/**
* @violates @ref PORT_CFG_H_REF_1 MISRA 2004 Rule 1.4, The compiler/linker shall be checked to
*  ensure that 31 character significance and case sensitivity are supported for external ids
*/
#define    PORT94_ENET0_MII_RMII_0_MDIO_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT95_GPIO        (PORT_GPIO_MODE)
#define    PORT95_EMIOS1_E1UC_4_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT95_ADC_1_ADC1_X_1        (PORT_ANALOG_INPUT_MODE)
#define    PORT95_EMIOS1_E1UC_4_H_IN        (PORT_INPUT1_MODE)
#define    PORT95_SIUL2_EIRQ13        (PORT_INPUT2_MODE)
#define    PORT95_FlexCAN_1_RX        (PORT_INPUT3_MODE)
#define    PORT95_FlexCAN_4_RX        (PORT_INPUT4_MODE)
#define    PORT95_ENET0_MII_RMII_0_RX_DV        (PORT_INPUT5_MODE)
#define    PORT95_EMIOS1_E1UC_4_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT96_GPIO        (PORT_GPIO_MODE)
#define    PORT96_FlexCAN_5_TX        (PORT_ALT1_FUNC_MODE)
#define    PORT96_EMIOS1_E1UC_23_X_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT96_ENET0_MII_RMII_0_MDC        (PORT_ALT3_FUNC_MODE)
#define    PORT96_ADC_1_ADC1_X_0        (PORT_ANALOG_INPUT_MODE)
#define    PORT96_EMIOS1_E1UC_23_X_IN        (PORT_INPUT1_MODE)
#define    PORT96_EMIOS1_E1UC_23_X_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT97_GPIO        (PORT_GPIO_MODE)
#define    PORT97_EMIOS1_E1UC_24_X_OUT        (PORT_ALT1_FUNC_MODE)
/**
* @violates @ref PORT_CFG_H_REF_1 MISRA 2004 Rule 1.4, The compiler/linker shall be checked to
*  ensure that 31 character significance and case sensitivity are supported for external ids
*/
#define    PORT97_ENET0_MII_RMII_0_TX_CLK_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT97_ADC_1_ADC1_S_7        (PORT_ANALOG_INPUT_MODE)
#define    PORT97_EMIOS1_E1UC_24_X_IN        (PORT_INPUT1_MODE)
#define    PORT97_SIUL2_EIRQ14        (PORT_INPUT2_MODE)
#define    PORT97_FlexCAN_5_RX        (PORT_INPUT3_MODE)
/**
* @violates @ref PORT_CFG_H_REF_1 MISRA 2004 Rule 1.4, The compiler/linker shall be checked to
*  ensure that 31 character significance and case sensitivity are supported for external ids
*/
#define    PORT97_ENET0_MII_RMII_0_TX_CLK_IN        (PORT_INPUT4_MODE)
#define    PORT97_EMIOS1_E1UC_24_X_IN_OUT        (PORT_INOUT1_MODE)
/**
* @violates @ref PORT_CFG_H_REF_1 MISRA 2004 Rule 1.4, The compiler/linker shall be checked to
*  ensure that 31 character significance and case sensitivity are supported for external ids
*/
#define    PORT97_ENET0_MII_RMII_0_TX_CLK_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT98_GPIO        (PORT_GPIO_MODE)
#define    PORT98_EMIOS1_E1UC_11_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT98_DSPI_3_dSOUT        (PORT_ALT2_FUNC_MODE)
#define    PORT98_FlexCAN_7_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT98_LIN_11_LIN11TX        (PORT_ALT4_FUNC_MODE)
#define    PORT98_EMIOS1_E1UC_11_H_IN        (PORT_INPUT1_MODE)
#define    PORT98_EMIOS1_E1UC_11_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT99_GPIO        (PORT_GPIO_MODE)
#define    PORT99_EMIOS1_E1UC_12_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT99_DSPI_3_dCS0        (PORT_ALT2_FUNC_MODE)
#define    PORT99_WKPU_WKPU_17        (PORT_ONLY_INPUT_MODE)
#define    PORT99_EMIOS1_E1UC_12_H_IN        (PORT_INPUT1_MODE)
#define    PORT99_FlexCAN_7_RX        (PORT_INPUT2_MODE)
#define    PORT99_DSPI_3_dSS        (PORT_INPUT3_MODE)
#define    PORT99_EMIOS1_E1UC_12_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT100_GPIO        (PORT_GPIO_MODE)
#define    PORT100_EMIOS1_E1UC_13_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT100_DSPI_3_dSCLK_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT100_LIN_10_LIN10TX        (PORT_ALT3_FUNC_MODE)
#define    PORT100_EMIOS1_E1UC_13_H_IN        (PORT_INPUT1_MODE)
#define    PORT100_DSPI_3_dSCLK_IN        (PORT_INPUT2_MODE)
#define    PORT100_EMIOS1_E1UC_13_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT100_DSPI_3_dSCLK_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT101_GPIO        (PORT_GPIO_MODE)
#define    PORT101_EMIOS1_E1UC_14_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT101_EMIOS0_E0UC_2_G_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT101_WKPU_WKPU_18        (PORT_ONLY_INPUT_MODE)
#define    PORT101_EMIOS1_E1UC_14_H_IN        (PORT_INPUT1_MODE)
#define    PORT101_LIN_10_LIN10RX        (PORT_INPUT2_MODE)
#define    PORT101_DSPI_3_dSIN        (PORT_INPUT3_MODE)
#define    PORT101_EMIOS0_E0UC_2_G_IN        (PORT_INPUT4_MODE)
#define    PORT101_EMIOS1_E1UC_14_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT101_EMIOS0_E0UC_2_G_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT102_GPIO        (PORT_GPIO_MODE)
#define    PORT102_EMIOS1_E1UC_15_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT102_LIN_6_LIN6TX        (PORT_ALT2_FUNC_MODE)
#define    PORT102_CGM_CLKOUT1        (PORT_ALT3_FUNC_MODE)
#define    PORT102_EMIOS0_E0UC_3_G_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT102_CMP0_CMP0_1        (PORT_ANALOG_INPUT_MODE)
#define    PORT102_PMCDIG_EXTREGC        (PORT_ONLY_OUTPUT_MODE)
#define    PORT102_EMIOS1_E1UC_15_H_IN        (PORT_INPUT1_MODE)
#define    PORT102_EMIOS0_E0UC_3_G_IN        (PORT_INPUT2_MODE)
#define    PORT102_EMIOS1_E1UC_15_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT102_EMIOS0_E0UC_3_G_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT103_GPIO        (PORT_GPIO_MODE)
#define    PORT103_EMIOS1_E1UC_16_X_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT103_EMIOS1_E1UC_30_Y_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT103_CGM_CLKOUT0        (PORT_ALT3_FUNC_MODE)
#define    PORT103_WKPU_WKPU_20        (PORT_ONLY_INPUT_MODE)
#define    PORT103_CMP0_CMP0_0        (PORT_ANALOG_INPUT_MODE)
#define    PORT103_EMIOS1_E1UC_16_X_IN        (PORT_INPUT1_MODE)
#define    PORT103_EMIOS1_E1UC_30_Y_IN        (PORT_INPUT2_MODE)
#define    PORT103_LIN_6_LIN6RX        (PORT_INPUT3_MODE)
#define    PORT103_GLITCH_FILTER3_INP        (PORT_INPUT4_MODE)
#define    PORT103_EMIOS1_E1UC_16_X_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT103_EMIOS1_E1UC_30_Y_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT104_GPIO        (PORT_GPIO_MODE)
#define    PORT104_EMIOS1_E1UC_17_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT104_LIN_7_LIN7TX        (PORT_ALT2_FUNC_MODE)
#define    PORT104_DSPI_2_dCS0        (PORT_ALT3_FUNC_MODE)
#define    PORT104_FlexCAN_7_TX        (PORT_ALT4_FUNC_MODE)
#define    PORT104_EMIOS1_E1UC_17_Y_IN        (PORT_INPUT1_MODE)
#define    PORT104_SIUL2_EIRQ15        (PORT_INPUT2_MODE)
#define    PORT104_DSPI_2_dSS        (PORT_INPUT3_MODE)
#define    PORT104_EMIOS1_E1UC_17_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT105_GPIO        (PORT_GPIO_MODE)
#define    PORT105_EMIOS1_E1UC_18_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT105_DSPI_2_dSCLK_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT105_EMIOS0_E0UC_0_X_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT105_WKPU_WKPU_21        (PORT_ONLY_INPUT_MODE)
#define    PORT105_EMIOS1_E1UC_18_Y_IN        (PORT_INPUT1_MODE)
#define    PORT105_FlexCAN_7_RX        (PORT_INPUT2_MODE)
#define    PORT105_LIN_7_LIN7RX        (PORT_INPUT3_MODE)
#define    PORT105_DSPI_2_dSCLK_IN        (PORT_INPUT4_MODE)
#define    PORT105_EMIOS0_E0UC_0_X_IN        (PORT_INPUT5_MODE)
#define    PORT105_EMIOS1_E1UC_18_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT105_DSPI_2_dSCLK_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT105_EMIOS0_E0UC_0_X_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT106_GPIO        (PORT_GPIO_MODE)
#define    PORT106_EMIOS0_E0UC_24_X_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT106_EMIOS1_E1UC_31_Y_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT106_EMIOS0_E0UC_24_X_IN        (PORT_INPUT1_MODE)
#define    PORT106_EMIOS1_E1UC_31_Y_IN        (PORT_INPUT2_MODE)
#define    PORT106_SPI_0_SIN_0        (PORT_INPUT3_MODE)
#define    PORT106_GLITCH_FILTER3_INP        (PORT_INPUT4_MODE)
#define    PORT106_EMIOS0_E0UC_24_X_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT106_EMIOS1_E1UC_31_Y_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT107_GPIO        (PORT_GPIO_MODE)
#define    PORT107_EMIOS0_E0UC_25_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT107_SPI_0_CS0_0        (PORT_ALT2_FUNC_MODE)
#define    PORT107_SPI_2_CS0_2        (PORT_ALT3_FUNC_MODE)
#define    PORT107_EMIOS0_E0UC_25_Y_IN        (PORT_INPUT1_MODE)
#define    PORT107_SPI_0_SS_0        (PORT_INPUT2_MODE)
#define    PORT107_SPI_2_SS_2        (PORT_INPUT3_MODE)
#define    PORT107_EMIOS0_E0UC_25_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT108_GPIO        (PORT_GPIO_MODE)
#define    PORT108_EMIOS0_E0UC_26_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT108_SPI_0_SOUT_0        (PORT_ALT2_FUNC_MODE)
#define    PORT108_ENET0_MII_0_TXD_2        (PORT_ALT4_FUNC_MODE)
#define    PORT108_ADC_1_ADC1_S_2        (PORT_ANALOG_INPUT_MODE)
#define    PORT108_EMIOS0_E0UC_26_Y_IN        (PORT_INPUT1_MODE)
#define    PORT108_EMIOS0_E0UC_26_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT109_GPIO        (PORT_GPIO_MODE)
#define    PORT109_EMIOS0_E0UC_27_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT109_SPI_0_SCLK_0_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT109_ENET0_MII_0_TXD_3        (PORT_ALT4_FUNC_MODE)
#define    PORT109_ADC_1_ADC1_S_1        (PORT_ANALOG_INPUT_MODE)
#define    PORT109_EMIOS0_E0UC_27_Y_IN        (PORT_INPUT1_MODE)
#define    PORT109_SPI_0_SCLK_0_IN        (PORT_INPUT2_MODE)
#define    PORT109_EMIOS0_E0UC_27_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT109_SPI_0_SCLK_0_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT110_GPIO        (PORT_GPIO_MODE)
#define    PORT110_EMIOS1_E1UC_0_X_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT110_LIN_8_LIN8TX        (PORT_ALT2_FUNC_MODE)
#define    PORT110_EMIOS1_E1UC_0_X_IN        (PORT_INPUT1_MODE)
#define    PORT110_SPI_2_SIN_2        (PORT_INPUT2_MODE)
#define    PORT110_EMIOS1_E1UC_0_X_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT111_GPIO        (PORT_GPIO_MODE)
#define    PORT111_EMIOS1_E1UC_1_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT111_SPI_2_SOUT_2        (PORT_ALT2_FUNC_MODE)
#define    PORT111_EMIOS1_E1UC_1_H_IN        (PORT_INPUT1_MODE)
#define    PORT111_LIN_8_LIN8RX        (PORT_INPUT2_MODE)
#define    PORT111_EMIOS1_E1UC_1_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT112_GPIO        (PORT_GPIO_MODE)
#define    PORT112_EMIOS1_E1UC_2_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT112_ENET0_MII_RMII_0_TXD_1        (PORT_ALT3_FUNC_MODE)
#define    PORT112_ADC_1_ADC1_S_3        (PORT_ANALOG_INPUT_MODE)
#define    PORT112_EMIOS1_E1UC_2_H_IN        (PORT_INPUT1_MODE)
#define    PORT112_DSPI_1_dSIN        (PORT_INPUT2_MODE)
#define    PORT112_EMIOS1_E1UC_2_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT113_GPIO        (PORT_GPIO_MODE)
#define    PORT113_EMIOS1_E1UC_3_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT113_DSPI_1_dSOUT        (PORT_ALT2_FUNC_MODE)
#define    PORT113_ENET0_MII_RMII_0_TXD_0        (PORT_ALT4_FUNC_MODE)
#define    PORT113_ADC_1_ADC1_S_4        (PORT_ANALOG_INPUT_MODE)
#define    PORT113_EMIOS1_E1UC_3_H_IN        (PORT_INPUT1_MODE)
#define    PORT113_EMIOS1_E1UC_3_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT114_GPIO        (PORT_GPIO_MODE)
#define    PORT114_EMIOS1_E1UC_4_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT114_DSPI_1_dSCLK_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT114_ENET0_MII_RMII_0_TX_EN        (PORT_ALT4_FUNC_MODE)
#define    PORT114_ADC_1_ADC1_S_5        (PORT_ANALOG_INPUT_MODE)
#define    PORT114_EMIOS1_E1UC_4_H_IN        (PORT_INPUT1_MODE)
#define    PORT114_DSPI_1_dSCLK_IN        (PORT_INPUT2_MODE)
#define    PORT114_EMIOS1_E1UC_4_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT114_DSPI_1_dSCLK_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT115_GPIO        (PORT_GPIO_MODE)
#define    PORT115_EMIOS1_E1UC_5_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT115_DSPI_1_dCS0        (PORT_ALT2_FUNC_MODE)
#define    PORT115_ENET0_MII_0_TX_ER        (PORT_ALT3_FUNC_MODE)
#define    PORT115_ADC_1_ADC1_S_6        (PORT_ANALOG_INPUT_MODE)
#define    PORT115_EMIOS1_E1UC_5_H_IN        (PORT_INPUT1_MODE)
#define    PORT115_DSPI_1_dSS        (PORT_INPUT2_MODE)
#define    PORT115_EMIOS1_E1UC_5_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT116_GPIO        (PORT_GPIO_MODE)
#define    PORT116_EMIOS1_E1UC_6_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT116_SPI_3_SOUT_3        (PORT_ALT2_FUNC_MODE)
#define    PORT116_IIC_3_SCL3_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT116_EMIOS1_E1UC_6_H_IN        (PORT_INPUT1_MODE)
#define    PORT116_IIC_3_SCL3_IN        (PORT_INPUT2_MODE)
#define    PORT116_EMIOS1_E1UC_6_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT116_IIC_3_SCL3_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT117_GPIO        (PORT_GPIO_MODE)
#define    PORT117_EMIOS1_E1UC_7_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT117_IIC_3_SDA3_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT117_EMIOS1_E1UC_7_H_IN        (PORT_INPUT1_MODE)
#define    PORT117_IIC_3_SDA3_IN        (PORT_INPUT2_MODE)
#define    PORT117_SPI_3_SIN_3        (PORT_INPUT3_MODE)
#define    PORT117_EMIOS1_E1UC_7_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT117_IIC_3_SDA3_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT118_GPIO        (PORT_GPIO_MODE)
#define    PORT118_EMIOS1_E1UC_8_X_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT118_SPI_3_SCLK_3_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT118_ADC_0_ADC0_MA_2        (PORT_ALT3_FUNC_MODE)
#define    PORT118_ADC_1_ADC1_MA_2        (PORT_ALT4_FUNC_MODE)
#define    PORT118_EMIOS1_E1UC_8_X_IN        (PORT_INPUT1_MODE)
#define    PORT118_SPI_3_SCLK_3_IN        (PORT_INPUT2_MODE)
#define    PORT118_EMIOS1_E1UC_8_X_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT118_SPI_3_SCLK_3_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT119_GPIO        (PORT_GPIO_MODE)
#define    PORT119_EMIOS1_E1UC_9_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT119_DSPI_2_dCS3        (PORT_ALT2_FUNC_MODE)
#define    PORT119_ADC_0_ADC0_MA_1        (PORT_ALT3_FUNC_MODE)
#define    PORT119_SPI_3_CS0_3        (PORT_ALT4_FUNC_MODE)
#define    PORT119_ADC_1_ADC1_MA_1        (PORT_ALT5_FUNC_MODE)
#define    PORT119_EMIOS1_E1UC_9_H_IN        (PORT_INPUT1_MODE)
#define    PORT119_SPI_3_SS_3        (PORT_INPUT2_MODE)
#define    PORT119_EMIOS1_E1UC_9_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT120_GPIO        (PORT_GPIO_MODE)
#define    PORT120_EMIOS1_E1UC_10_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT120_DSPI_2_dCS2        (PORT_ALT2_FUNC_MODE)
#define    PORT120_ADC_0_ADC0_MA_0        (PORT_ALT3_FUNC_MODE)
#define    PORT120_ADC_1_ADC1_MA_0        (PORT_ALT4_FUNC_MODE)
#define    PORT120_EMIOS1_E1UC_10_H_IN        (PORT_INPUT1_MODE)
#define    PORT120_EMIOS1_E1UC_10_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT121_GPIO        (PORT_GPIO_MODE)
#define    PORT121_DCI_TCK        (PORT_ALT1_FUNC_MODE)
#define    PORT122_GPIO        (PORT_GPIO_MODE)
#define    PORT122_DCI_TMS_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT122_DCI_TMS_IN        (PORT_ONLY_INPUT_MODE)
#define    PORT122_DCI_TMS_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT123_GPIO        (PORT_GPIO_MODE)
#define    PORT123_DSPI_3_dSOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT123_SPI_0_CS0_0        (PORT_ALT2_FUNC_MODE)
#define    PORT123_EMIOS1_E1UC_5_H_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT123_EMIOS1_E1UC_5_H_IN        (PORT_INPUT1_MODE)
#define    PORT123_SPI_0_SS_0        (PORT_INPUT2_MODE)
#define    PORT123_EMIOS1_E1UC_5_H_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT124_GPIO        (PORT_GPIO_MODE)
#define    PORT124_DSPI_3_dSCLK_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT124_SPI_0_CS1_0        (PORT_ALT2_FUNC_MODE)
#define    PORT124_EMIOS1_E1UC_25_Y_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT124_EMIOS1_E1UC_25_Y_IN        (PORT_INPUT1_MODE)
#define    PORT124_DSPI_3_dSCLK_IN        (PORT_INPUT2_MODE)
#define    PORT124_DSPI_3_dSCLK_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT124_EMIOS1_E1UC_25_Y_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT125_GPIO        (PORT_GPIO_MODE)
#define    PORT125_SPI_0_SOUT_0        (PORT_ALT1_FUNC_MODE)
#define    PORT125_DSPI_3_dCS0        (PORT_ALT2_FUNC_MODE)
#define    PORT125_EMIOS1_E1UC_26_Y_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT125_FCCU_EOUT1_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT125_FCCU_EOUT1_IN        (PORT_ONLY_INPUT_MODE)
#define    PORT125_FCCU_EOUT1_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT125_EMIOS1_E1UC_26_Y_IN        (PORT_INPUT1_MODE)
#define    PORT125_DSPI_3_dSS        (PORT_INPUT2_MODE)
#define    PORT125_EMIOS1_E1UC_26_Y_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT126_GPIO        (PORT_GPIO_MODE)
#define    PORT126_SPI_0_SCLK_0_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT126_DSPI_3_dCS1        (PORT_ALT2_FUNC_MODE)
#define    PORT126_EMIOS1_E1UC_27_Y_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT126_EMIOS1_E1UC_27_Y_IN        (PORT_INPUT1_MODE)
#define    PORT126_SPI_0_SCLK_0_IN        (PORT_INPUT2_MODE)
#define    PORT126_FCCU_EIN_ERR        (PORT_INPUT3_MODE)
#define    PORT126_SPI_0_SCLK_0_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT126_EMIOS1_E1UC_27_Y_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT127_GPIO        (PORT_GPIO_MODE)
#define    PORT127_SPI_1_SOUT_1        (PORT_ALT1_FUNC_MODE)
#define    PORT127_EMIOS1_E1UC_17_Y_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT127_FCCU_EOUT0_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT127_FCCU_EOUT0_IN        (PORT_ONLY_INPUT_MODE)
#define    PORT127_FCCU_EOUT0_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT127_EMIOS1_E1UC_17_Y_IN        (PORT_INPUT1_MODE)
#define    PORT127_EMIOS1_E1UC_17_Y_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT128_GPIO        (PORT_GPIO_MODE)
#define    PORT128_EMIOS0_E0UC_28_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT128_LIN_8_LIN8TX        (PORT_ALT2_FUNC_MODE)
#define    PORT128_IIC_1_SDA1_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT128_EMIOS0_E0UC_28_Y_IN        (PORT_INPUT1_MODE)
#define    PORT128_IIC_1_SDA1_IN        (PORT_INPUT2_MODE)
#define    PORT128_GLITCH_FILTER0_INP        (PORT_INPUT3_MODE)
#define    PORT128_EMIOS0_E0UC_28_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT128_IIC_1_SDA1_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT129_GPIO        (PORT_GPIO_MODE)
#define    PORT129_EMIOS0_E0UC_29_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT129_IIC_1_SCL1_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT129_WKPU_WKPU_24        (PORT_ONLY_INPUT_MODE)
#define    PORT129_EMIOS0_E0UC_29_Y_IN        (PORT_INPUT1_MODE)
#define    PORT129_LIN_8_LIN8RX        (PORT_INPUT2_MODE)
#define    PORT129_IIC_1_SCL1_IN        (PORT_INPUT3_MODE)
#define    PORT129_GLITCH_FILTER0_INP        (PORT_INPUT4_MODE)
#define    PORT129_EMIOS0_E0UC_29_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT129_IIC_1_SCL1_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT130_GPIO        (PORT_GPIO_MODE)
#define    PORT130_EMIOS0_E0UC_30_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT130_LIN_9_LIN9TX        (PORT_ALT2_FUNC_MODE)
#define    PORT130_IIC_2_SDA2_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT130_EMIOS0_E0UC_30_Y_IN        (PORT_INPUT1_MODE)
#define    PORT130_IIC_2_SDA2_IN        (PORT_INPUT2_MODE)
#define    PORT130_GLITCH_FILTER1_INP        (PORT_INPUT3_MODE)
#define    PORT130_EMIOS0_E0UC_30_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT130_IIC_2_SDA2_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT131_GPIO        (PORT_GPIO_MODE)
#define    PORT131_EMIOS0_E0UC_31_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT131_IIC_2_SCL2_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT131_WKPU_WKPU_23        (PORT_ONLY_INPUT_MODE)
#define    PORT131_EMIOS0_E0UC_31_Y_IN        (PORT_INPUT1_MODE)
#define    PORT131_LIN_9_LIN9RX        (PORT_INPUT2_MODE)
#define    PORT131_IIC_2_SCL2_IN        (PORT_INPUT3_MODE)
#define    PORT131_GLITCH_FILTER1_INP        (PORT_INPUT4_MODE)
#define    PORT131_EMIOS0_E0UC_31_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT131_IIC_2_SCL2_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT132_GPIO        (PORT_GPIO_MODE)
#define    PORT132_EMIOS1_E1UC_28_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT132_SPI_0_SOUT_0        (PORT_ALT2_FUNC_MODE)
#define    PORT132_EMIOS1_E1UC_28_Y_IN        (PORT_INPUT1_MODE)
#define    PORT132_GLITCH_FILTER2_INP        (PORT_INPUT2_MODE)
#define    PORT132_EMIOS1_E1UC_28_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT133_GPIO        (PORT_GPIO_MODE)
#define    PORT133_EMIOS1_E1UC_29_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT133_SPI_0_SCLK_0_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT133_SPI_1_CS2_1        (PORT_ALT3_FUNC_MODE)
#define    PORT133_SPI_2_CS2_2        (PORT_ALT4_FUNC_MODE)
#define    PORT133_EMIOS1_E1UC_29_Y_IN        (PORT_INPUT1_MODE)
#define    PORT133_SPI_0_SCLK_0_IN        (PORT_INPUT2_MODE)
#define    PORT133_GLITCH_FILTER2_INP        (PORT_INPUT3_MODE)
#define    PORT133_EMIOS1_E1UC_29_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT133_SPI_0_SCLK_0_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT134_GPIO        (PORT_GPIO_MODE)
#define    PORT134_EMIOS1_E1UC_30_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT134_SPI_0_CS0_0        (PORT_ALT2_FUNC_MODE)
#define    PORT134_SPI_1_CS0_1        (PORT_ALT3_FUNC_MODE)
#define    PORT134_SPI_2_CS0_2        (PORT_ALT4_FUNC_MODE)
#define    PORT134_HSM_DO0        (PORT_ALT5_FUNC_MODE)
#define    PORT134_EMIOS1_E1UC_30_Y_IN        (PORT_INPUT1_MODE)
#define    PORT134_SPI_0_SS_0        (PORT_INPUT2_MODE)
#define    PORT134_SPI_1_SS_1        (PORT_INPUT3_MODE)
#define    PORT134_SPI_2_SS_2        (PORT_INPUT4_MODE)
#define    PORT134_GLITCH_FILTER3_INP        (PORT_INPUT5_MODE)
#define    PORT134_EMIOS1_E1UC_30_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT135_GPIO        (PORT_GPIO_MODE)
#define    PORT135_EMIOS1_E1UC_31_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT135_SPI_0_CS1_0        (PORT_ALT2_FUNC_MODE)
#define    PORT135_SPI_1_CS1_1        (PORT_ALT3_FUNC_MODE)
#define    PORT135_SPI_2_CS1_2        (PORT_ALT4_FUNC_MODE)
#define    PORT135_HSM_DO1        (PORT_ALT5_FUNC_MODE)
#define    PORT135_EMIOS1_E1UC_31_Y_IN        (PORT_INPUT1_MODE)
#define    PORT135_GLITCH_FILTER3_INP        (PORT_INPUT2_MODE)
#define    PORT135_EMIOS1_E1UC_31_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT136_GPIO        (PORT_GPIO_MODE)
#define    PORT136_ADC_0_ADC0_S_16        (PORT_ANALOG_INPUT_MODE)
#define    PORT137_GPIO        (PORT_GPIO_MODE)
#define    PORT137_ADC_0_ADC0_S_17        (PORT_ANALOG_INPUT_MODE)
#define    PORT138_GPIO        (PORT_GPIO_MODE)
#define    PORT138_ADC_0_ADC0_S_18        (PORT_ANALOG_INPUT_MODE)
#define    PORT139_GPIO        (PORT_GPIO_MODE)
#define    PORT139_ENET0_ENET0_TMR1_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT139_ADC_0_ADC0_S_19        (PORT_ANALOG_INPUT_MODE)
#define    PORT139_DSPI_3_dSIN        (PORT_INPUT1_MODE)
#define    PORT139_ENET0_ENET0_TMR1_IN        (PORT_INPUT2_MODE)
#define    PORT139_ENET0_ENET0_TMR1_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT140_GPIO        (PORT_GPIO_MODE)
#define    PORT140_DSPI_3_dCS0        (PORT_ALT1_FUNC_MODE)
#define    PORT140_DSPI_2_dCS0        (PORT_ALT2_FUNC_MODE)
#define    PORT140_ADC_0_ADC0_S_20        (PORT_ANALOG_INPUT_MODE)
#define    PORT140_DSPI_2_dSS        (PORT_INPUT1_MODE)
#define    PORT140_DSPI_3_dSS        (PORT_INPUT2_MODE)
#define    PORT141_GPIO        (PORT_GPIO_MODE)
#define    PORT141_DSPI_3_dCS1        (PORT_ALT1_FUNC_MODE)
#define    PORT141_DSPI_2_dCS1        (PORT_ALT2_FUNC_MODE)
#define    PORT141_ADC_0_ADC0_S_21        (PORT_ANALOG_INPUT_MODE)
#define    PORT142_GPIO        (PORT_GPIO_MODE)
#define    PORT142_SAI2_SAI2_D0_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT142_ADC_0_ADC0_S_22        (PORT_ANALOG_INPUT_MODE)
#define    PORT142_SPI_0_SIN_0        (PORT_INPUT1_MODE)
#define    PORT142_SAI2_SAI2_D0_IN        (PORT_INPUT2_MODE)
#define    PORT142_SAI2_SAI2_D0_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT143_GPIO        (PORT_GPIO_MODE)
#define    PORT143_SPI_0_CS0_0        (PORT_ALT1_FUNC_MODE)
#define    PORT143_DSPI_2_dCS2        (PORT_ALT2_FUNC_MODE)
#define    PORT143_SAI2_SAI2_MCLK_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT143_ADC_0_ADC0_S_23        (PORT_ANALOG_INPUT_MODE)
#define    PORT143_SPI_0_SS_0        (PORT_INPUT1_MODE)
#define    PORT143_SAI2_SAI2_MCLK_IN        (PORT_INPUT2_MODE)
#define    PORT143_SAI2_SAI2_MCLK_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT144_GPIO        (PORT_GPIO_MODE)
#define    PORT144_SPI_0_CS1_0        (PORT_ALT1_FUNC_MODE)
#define    PORT144_DSPI_2_dCS3        (PORT_ALT2_FUNC_MODE)
#define    PORT144_SAI2_SAI2_SYNC_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT144_ADC_0_ADC0_S_24        (PORT_ANALOG_INPUT_MODE)
#define    PORT144_SAI2_SAI2_SYNC_IN        (PORT_INPUT1_MODE)
#define    PORT144_SAI2_SAI2_SYNC_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT145_GPIO        (PORT_GPIO_MODE)
#define    PORT145_SPI_0_SOUT_0        (PORT_ALT1_FUNC_MODE)
#define    PORT145_SAI2_SAI2_BCLK_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT145_ADC_0_ADC0_S_25        (PORT_ANALOG_INPUT_MODE)
#define    PORT145_SPI_1_SIN_1        (PORT_INPUT1_MODE)
#define    PORT145_SAI2_SAI2_BCLK_IN        (PORT_INPUT2_MODE)
#define    PORT145_SAI2_SAI2_BCLK_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT146_GPIO        (PORT_GPIO_MODE)
#define    PORT146_SPI_1_CS0_1        (PORT_ALT1_FUNC_MODE)
#define    PORT146_SPI_2_CS0_2        (PORT_ALT2_FUNC_MODE)
#define    PORT146_SPI_3_CS0_3        (PORT_ALT3_FUNC_MODE)
#define    PORT146_SAI1_SAI1_D0_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT146_ADC_0_ADC0_S_26        (PORT_ANALOG_INPUT_MODE)
#define    PORT146_SPI_1_SS_1        (PORT_INPUT1_MODE)
#define    PORT146_SPI_2_SS_2        (PORT_INPUT2_MODE)
#define    PORT146_SPI_3_SS_3        (PORT_INPUT3_MODE)
#define    PORT146_SAI1_SAI1_D0_IN        (PORT_INPUT4_MODE)
#define    PORT146_SAI1_SAI1_D0_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT147_GPIO        (PORT_GPIO_MODE)
#define    PORT147_SPI_1_CS1_1        (PORT_ALT1_FUNC_MODE)
#define    PORT147_SPI_2_CS1_2        (PORT_ALT2_FUNC_MODE)
#define    PORT147_SPI_3_CS1_3        (PORT_ALT3_FUNC_MODE)
#define    PORT147_SAI1_SAI1_BCLK_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT147_ADC_0_ADC0_S_27        (PORT_ANALOG_INPUT_MODE)
#define    PORT147_SAI1_SAI1_BCLK_IN        (PORT_INPUT1_MODE)
#define    PORT147_SAI1_SAI1_BCLK_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT148_GPIO        (PORT_GPIO_MODE)
#define    PORT148_SPI_1_SCLK_1_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT148_EMIOS1_E1UC_18_Y_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT148_EMIOS1_E1UC_18_Y_IN        (PORT_INPUT1_MODE)
#define    PORT148_SPI_1_SCLK_1_IN        (PORT_INPUT2_MODE)
#define    PORT148_FCCU_EIN_ERR        (PORT_INPUT3_MODE)
#define    PORT148_SPI_1_SCLK_1_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT148_EMIOS1_E1UC_18_Y_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT149_GPIO        (PORT_GPIO_MODE)
#define    PORT149_SAI2_SAI2_D0_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT149_ADC_0_ADC0_S_28        (PORT_ANALOG_INPUT_MODE)
#define    PORT149_SAI2_SAI2_D0_IN        (PORT_INPUT1_MODE)
#define    PORT149_SAI2_SAI2_D0_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT150_GPIO        (PORT_GPIO_MODE)
#define    PORT150_SAI2_SAI2_BCLK_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT150_ADC_0_ADC0_S_29        (PORT_ANALOG_INPUT_MODE)
#define    PORT150_SAI2_SAI2_BCLK_IN        (PORT_INPUT1_MODE)
#define    PORT150_SAI2_SAI2_BCLK_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT151_GPIO        (PORT_GPIO_MODE)
#define    PORT151_ADC_0_ADC0_S_30        (PORT_ANALOG_INPUT_MODE)
#define    PORT151_SAI2_SAI2_MCLK_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT151_SAI2_SAI2_MCLK_IN        (PORT_INPUT1_MODE)
#define    PORT151_SAI2_SAI2_MCLK_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT152_GPIO        (PORT_GPIO_MODE)
#define    PORT152_SAI2_SAI2_SYNC_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT152_ADC_0_ADC0_S_31        (PORT_ANALOG_INPUT_MODE)
#define    PORT152_SAI2_SAI2_SYNC_IN        (PORT_INPUT1_MODE)
#define    PORT152_SAI2_SAI2_SYNC_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT153_GPIO        (PORT_GPIO_MODE)
#define    PORT153_FlexCAN_4_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT153_EMIOS1_E1UC_17_Y_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT153_EMIOS1_E1UC_17_Y_IN        (PORT_INPUT1_MODE)
#define    PORT153_EMIOS1_E1UC_17_Y_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT154_GPIO        (PORT_GPIO_MODE)
#define    PORT154_EMIOS1_E1UC_16_X_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT154_EMIOS1_E1UC_16_X_IN        (PORT_INPUT1_MODE)
#define    PORT154_FlexCAN_4_RX        (PORT_INPUT2_MODE)
#define    PORT154_EMIOS1_E1UC_16_X_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT155_GPIO        (PORT_GPIO_MODE)
#define    PORT155_FlexCAN_2_TX        (PORT_ALT1_FUNC_MODE)
#define    PORT155_EMIOS1_E1UC_11_H_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT155_EMIOS1_E1UC_11_H_IN        (PORT_INPUT1_MODE)
#define    PORT155_EMIOS1_E1UC_11_H_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT156_GPIO        (PORT_GPIO_MODE)
#define    PORT156_EMIOS1_E1UC_10_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT156_EMIOS1_E1UC_10_H_IN        (PORT_INPUT1_MODE)
#define    PORT156_FlexCAN_2_RX        (PORT_INPUT2_MODE)
#define    PORT156_EMIOS1_E1UC_10_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT157_GPIO        (PORT_GPIO_MODE)
#define    PORT157_SPI_3_CS1_3        (PORT_ALT1_FUNC_MODE)
#define    PORT157_EMIOS1_E1UC_15_H_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT157_WKPU_WKPU_31        (PORT_ONLY_INPUT_MODE)
#define    PORT157_EMIOS1_E1UC_15_H_IN        (PORT_INPUT1_MODE)
#define    PORT157_FlexCAN_1_RX        (PORT_INPUT2_MODE)
#define    PORT157_FlexCAN_4_RX        (PORT_INPUT3_MODE)
#define    PORT157_FlexCAN_6_RX        (PORT_INPUT4_MODE)
#define    PORT157_EMIOS1_E1UC_15_H_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT158_GPIO        (PORT_GPIO_MODE)
#define    PORT158_FlexCAN_1_TX        (PORT_ALT1_FUNC_MODE)
#define    PORT158_FlexCAN_4_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT158_SPI_3_CS2_3        (PORT_ALT3_FUNC_MODE)
#define    PORT158_FlexCAN_6_TX        (PORT_ALT4_FUNC_MODE)
#define    PORT158_EMIOS1_E1UC_14_H_OUT        (PORT_ALT6_FUNC_MODE)
#define    PORT158_EMIOS1_E1UC_14_H_IN        (PORT_INPUT1_MODE)
#define    PORT158_EMIOS1_E1UC_14_H_IN_OUT        (PORT_INOUT6_MODE)
#define    PORT159_GPIO        (PORT_GPIO_MODE)
#define    PORT159_SPI_2_CS1_2        (PORT_ALT1_FUNC_MODE)
#define    PORT159_EMIOS1_E1UC_13_H_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT159_EMIOS1_E1UC_13_H_IN        (PORT_INPUT1_MODE)
#define    PORT159_FlexCAN_1_RX        (PORT_INPUT2_MODE)
#define    PORT159_FlexCAN_3_RX        (PORT_INPUT3_MODE)
#define    PORT159_EMIOS1_E1UC_13_H_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT160_GPIO        (PORT_GPIO_MODE)
#define    PORT160_FlexCAN_1_TX        (PORT_ALT1_FUNC_MODE)
#define    PORT160_SPI_2_CS2_2        (PORT_ALT2_FUNC_MODE)
#define    PORT160_FlexCAN_3_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT160_EMIOS1_E1UC_12_H_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT160_EMIOS1_E1UC_12_H_IN        (PORT_INPUT1_MODE)
#define    PORT160_EMIOS1_E1UC_12_H_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT161_GPIO        (PORT_GPIO_MODE)
#define    PORT161_SPI_2_CS3_2        (PORT_ALT1_FUNC_MODE)
#define    PORT161_EMIOS1_E1UC_1_H_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT161_EMIOS0_E0UC_6_G_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT161_EMIOS1_E1UC_1_H_IN        (PORT_INPUT1_MODE)
#define    PORT161_FlexCAN_4_RX        (PORT_INPUT2_MODE)
#define    PORT161_EMIOS0_E0UC_6_G_IN        (PORT_INPUT3_MODE)
#define    PORT161_EMIOS1_E1UC_1_H_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT161_EMIOS0_E0UC_6_G_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT162_GPIO        (PORT_GPIO_MODE)
#define    PORT162_FlexCAN_4_TX        (PORT_ALT1_FUNC_MODE)
#define    PORT162_EMIOS1_E1UC_2_H_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT162_EMIOS1_E1UC_2_H_IN        (PORT_INPUT1_MODE)
#define    PORT162_EMIOS1_E1UC_2_H_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT163_GPIO        (PORT_GPIO_MODE)
#define    PORT163_EMIOS1_E1UC_0_X_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT163_EMIOS1_E1UC_3_H_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT163_EMIOS1_E1UC_0_X_IN        (PORT_INPUT1_MODE)
#define    PORT163_EMIOS1_E1UC_3_H_IN        (PORT_INPUT2_MODE)
#define    PORT163_SIUL2_EIRQ31        (PORT_INPUT3_MODE)
#define    PORT163_FlexCAN_5_RX        (PORT_INPUT4_MODE)
#define    PORT163_LIN_8_LIN8RX        (PORT_INPUT5_MODE)
#define    PORT163_EMIOS1_E1UC_0_X_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT163_EMIOS1_E1UC_3_H_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT164_GPIO        (PORT_GPIO_MODE)
#define    PORT164_FlexCAN_5_TX        (PORT_ALT1_FUNC_MODE)
#define    PORT164_LIN_8_LIN8TX        (PORT_ALT2_FUNC_MODE)
#define    PORT164_EMIOS1_E1UC_1_H_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT164_EMIOS0_E0UC_9_H_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT164_EMIOS1_E1UC_1_H_IN        (PORT_INPUT1_MODE)
#define    PORT164_EMIOS0_E0UC_9_H_IN        (PORT_INPUT2_MODE)
#define    PORT164_EMIOS1_E1UC_1_H_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT164_EMIOS0_E0UC_9_H_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT165_GPIO        (PORT_GPIO_MODE)
#define    PORT165_EMIOS1_E1UC_4_H_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT165_EMIOS0_E0UC_10_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT165_EMIOS1_E1UC_4_H_IN        (PORT_INPUT1_MODE)
#define    PORT165_FlexCAN_2_RX        (PORT_INPUT2_MODE)
#define    PORT165_LIN_2_LIN2RX        (PORT_INPUT3_MODE)
#define    PORT165_EMIOS0_E0UC_10_H_IN        (PORT_INPUT4_MODE)
#define    PORT165_EMIOS1_E1UC_4_H_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT165_EMIOS0_E0UC_10_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT166_GPIO        (PORT_GPIO_MODE)
#define    PORT166_FlexCAN_2_TX        (PORT_ALT1_FUNC_MODE)
#define    PORT166_LIN_2_LIN2TX        (PORT_ALT2_FUNC_MODE)
#define    PORT166_EMIOS1_E1UC_5_H_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT166_EMIOS0_E0UC_11_H_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT166_EMIOS1_E1UC_5_H_IN        (PORT_INPUT1_MODE)
#define    PORT166_EMIOS0_E0UC_11_H_IN        (PORT_INPUT2_MODE)
#define    PORT166_EMIOS1_E1UC_5_H_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT166_EMIOS0_E0UC_11_H_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT167_GPIO        (PORT_GPIO_MODE)
#define    PORT167_EMIOS1_E1UC_6_H_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT167_EMIOS0_E0UC_12_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT167_EMIOS1_E1UC_6_H_IN        (PORT_INPUT1_MODE)
#define    PORT167_FlexCAN_3_RX        (PORT_INPUT2_MODE)
#define    PORT167_LIN_3_LIN3RX        (PORT_INPUT3_MODE)
#define    PORT167_EMIOS0_E0UC_12_H_IN        (PORT_INPUT4_MODE)
#define    PORT167_EMIOS1_E1UC_6_H_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT167_EMIOS0_E0UC_12_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT168_GPIO        (PORT_GPIO_MODE)
#define    PORT168_FlexCAN_3_TX        (PORT_ALT1_FUNC_MODE)
#define    PORT168_LIN_3_LIN3TX        (PORT_ALT2_FUNC_MODE)
#define    PORT168_EMIOS1_E1UC_7_H_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT168_EMIOS0_E0UC_13_H_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT168_EMIOS1_E1UC_7_H_IN        (PORT_INPUT1_MODE)
#define    PORT168_EMIOS0_E0UC_13_H_IN        (PORT_INPUT2_MODE)
#define    PORT168_EMIOS1_E1UC_7_H_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT168_EMIOS0_E0UC_13_H_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT169_GPIO        (PORT_GPIO_MODE)
#define    PORT169_EMIOS1_E1UC_29_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT169_EMIOS1_E1UC_29_Y_IN        (PORT_INPUT1_MODE)
#define    PORT169_LIN_15_LIN15RX        (PORT_INPUT2_MODE)
#define    PORT169_SPI_0_SIN_0        (PORT_INPUT3_MODE)
#define    PORT169_GLITCH_FILTER2_INP        (PORT_INPUT4_MODE)
#define    PORT169_EMIOS1_E1UC_29_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT170_GPIO        (PORT_GPIO_MODE)
#define    PORT170_SPI_0_SOUT_0        (PORT_ALT1_FUNC_MODE)
#define    PORT170_EMIOS1_E1UC_30_Y_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT170_LIN_15_LIN15TX        (PORT_ALT3_FUNC_MODE)
#define    PORT170_EMIOS1_E1UC_30_Y_IN        (PORT_INPUT1_MODE)
#define    PORT170_GLITCH_FILTER3_INP        (PORT_INPUT2_MODE)
#define    PORT170_EMIOS1_E1UC_30_Y_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT171_GPIO        (PORT_GPIO_MODE)
#define    PORT171_SPI_0_SCLK_0_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT171_EMIOS1_E1UC_31_Y_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT171_LIN_14_LIN14TX        (PORT_ALT3_FUNC_MODE)
#define    PORT171_EMIOS1_E1UC_31_Y_IN        (PORT_INPUT1_MODE)
#define    PORT171_SPI_0_SCLK_0_IN        (PORT_INPUT2_MODE)
#define    PORT171_GLITCH_FILTER3_INP        (PORT_INPUT3_MODE)
#define    PORT171_SPI_0_SCLK_0_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT171_EMIOS1_E1UC_31_Y_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT172_GPIO        (PORT_GPIO_MODE)
#define    PORT172_SPI_0_CS0_0        (PORT_ALT1_FUNC_MODE)
#define    PORT172_EMIOS0_E0UC_0_X_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT172_EMIOS0_E0UC_0_X_IN        (PORT_INPUT1_MODE)
#define    PORT172_LIN_14_LIN14RX        (PORT_INPUT2_MODE)
#define    PORT172_SPI_0_SS_0        (PORT_INPUT3_MODE)
#define    PORT172_EMIOS0_E0UC_0_X_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT173_GPIO        (PORT_GPIO_MODE)
#define    PORT173_SPI_2_CS3_2        (PORT_ALT1_FUNC_MODE)
#define    PORT173_SPI_3_CS2_3        (PORT_ALT2_FUNC_MODE)
#define    PORT173_SPI_1_SCLK_1_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT173_EMIOS0_E0UC_1_G_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT173_EMIOS0_E0UC_1_G_IN        (PORT_INPUT1_MODE)
#define    PORT173_FlexCAN_3_RX        (PORT_INPUT2_MODE)
#define    PORT173_SPI_1_SCLK_1_IN        (PORT_INPUT3_MODE)
#define    PORT173_SPI_1_SCLK_1_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT173_EMIOS0_E0UC_1_G_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT174_GPIO        (PORT_GPIO_MODE)
#define    PORT174_FlexCAN_3_TX        (PORT_ALT1_FUNC_MODE)
#define    PORT174_SPI_3_CS3_3        (PORT_ALT2_FUNC_MODE)
#define    PORT174_SPI_1_CS0_1        (PORT_ALT3_FUNC_MODE)
#define    PORT174_EMIOS0_E0UC_2_G_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT174_EMIOS0_E0UC_2_G_IN        (PORT_INPUT1_MODE)
#define    PORT174_SPI_1_SS_1        (PORT_INPUT2_MODE)
#define    PORT174_EMIOS0_E0UC_2_G_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT175_GPIO        (PORT_GPIO_MODE)
#define    PORT175_SPI_0_CS2_0        (PORT_ALT1_FUNC_MODE)
#define    PORT175_EMIOS0_E0UC_3_G_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT175_LIN_13_LIN13TX        (PORT_ALT3_FUNC_MODE)
#define    PORT175_EMIOS0_E0UC_3_G_IN        (PORT_INPUT1_MODE)
#define    PORT175_SPI_1_SIN_1        (PORT_INPUT2_MODE)
#define    PORT175_SPI_3_SIN_3        (PORT_INPUT3_MODE)
#define    PORT175_EMIOS0_E0UC_3_G_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT176_GPIO        (PORT_GPIO_MODE)
#define    PORT176_SPI_1_SOUT_1        (PORT_ALT1_FUNC_MODE)
#define    PORT176_SPI_3_SOUT_3        (PORT_ALT2_FUNC_MODE)
#define    PORT176_SPI_0_CS3_0        (PORT_ALT3_FUNC_MODE)
#define    PORT176_EMIOS0_E0UC_4_G_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT176_EMIOS0_E0UC_4_G_IN        (PORT_INPUT1_MODE)
#define    PORT176_LIN_13_LIN13RX        (PORT_INPUT2_MODE)
#define    PORT176_EMIOS0_E0UC_4_G_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT177_GPIO        (PORT_GPIO_MODE)
#define    PORT177_SAI0_SAI0_D0_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT177_ADC_0_ADC0_S_47        (PORT_ANALOG_INPUT_MODE)
#define    PORT177_SAI0_SAI0_D0_IN        (PORT_INPUT1_MODE)
#define    PORT177_SAI0_SAI0_D0_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT195_GPIO        (PORT_GPIO_MODE)
#define    PORT195_SAI0_SAI0_D1_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT195_ENET0_ENET0_TMR2_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT195_ADC_0_ADC0_S_46        (PORT_ANALOG_INPUT_MODE)
#define    PORT195_SAI0_SAI0_D1_IN        (PORT_INPUT1_MODE)
#define    PORT195_ENET0_ENET0_TMR2_IN        (PORT_INPUT2_MODE)
#define    PORT195_SAI0_SAI0_D1_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT195_ENET0_ENET0_TMR2_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT196_GPIO        (PORT_GPIO_MODE)
#define    PORT196_SAI0_SAI0_D2_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT196_ADC_0_ADC0_S_45        (PORT_ANALOG_INPUT_MODE)
#define    PORT196_SAI0_SAI0_D2_IN        (PORT_INPUT1_MODE)
#define    PORT196_SAI0_SAI0_D2_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT197_GPIO        (PORT_GPIO_MODE)
#define    PORT197_SAI0_SAI0_D3_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT197_DCI_TCK_ALT        (PORT_ALT2_FUNC_MODE)
#define    PORT197_ADC_0_ADC0_S_44        (PORT_ANALOG_INPUT_MODE)
#define    PORT197_SAI0_SAI0_D3_IN        (PORT_INPUT1_MODE)
#define    PORT197_SAI0_SAI0_D3_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT206_GPIO        (PORT_GPIO_MODE)
#define    PORT206_SAI0_SAI0_MCLK_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT206_DCI_TMS_ALT_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT206_DCI_TMS_ALT_IN        (PORT_ONLY_INPUT_MODE)
#define    PORT206_DCI_TMS_ALT_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT206_ADC_1_ADC1_S_15        (PORT_ANALOG_INPUT_MODE)
#define    PORT206_SAI0_SAI0_MCLK_IN        (PORT_INPUT1_MODE)
#define    PORT206_SAI0_SAI0_MCLK_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT224_GPIO        (PORT_GPIO_MODE)
#define    PORT224_IIC_0_SDA0_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT224_LIN_12_LIN12TX        (PORT_ALT3_FUNC_MODE)
#define    PORT224_IIC_0_SDA0_IN        (PORT_INPUT1_MODE)
#define    PORT224_IIC_0_SDA0_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT225_GPIO        (PORT_GPIO_MODE)
#define    PORT225_IIC_0_SCL0_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT225_LIN_12_LIN12RX        (PORT_INPUT1_MODE)
#define    PORT225_IIC_0_SCL0_IN        (PORT_INPUT2_MODE)
#define    PORT225_IIC_0_SCL0_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT252_GPIO        (PORT_GPIO_MODE)
#define    PORT252_SPI_2_CS0_2        (PORT_ALT1_FUNC_MODE)
#define    PORT252_DSPI_0_dCS4        (PORT_ALT2_FUNC_MODE)
#define    PORT252_EMIOS1_E1UC_24_X_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT252_EMIOS1_E1UC_24_X_IN        (PORT_INPUT1_MODE)
#define    PORT252_SPI_2_SS_2        (PORT_INPUT2_MODE)
#define    PORT252_EMIOS1_E1UC_24_X_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT253_GPIO        (PORT_GPIO_MODE)
#define    PORT253_SPI_2_SOUT_2        (PORT_ALT1_FUNC_MODE)
#define    PORT253_EMIOS1_E1UC_23_X_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT253_EMIOS1_E1UC_23_X_IN        (PORT_INPUT1_MODE)
#define    PORT253_EMIOS1_E1UC_23_X_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT254_GPIO        (PORT_GPIO_MODE)
#define    PORT254_SPI_2_SCLK_2_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT254_EMIOS1_E1UC_22_X_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT254_EMIOS1_E1UC_22_X_IN        (PORT_INPUT1_MODE)
#define    PORT254_SPI_2_SCLK_2_IN        (PORT_INPUT2_MODE)
#define    PORT254_SPI_2_SCLK_2_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT254_EMIOS1_E1UC_22_X_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT255_GPIO        (PORT_GPIO_MODE)
#define    PORT255_EMIOS1_E1UC_21_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT255_EMIOS1_E1UC_21_Y_IN        (PORT_INPUT1_MODE)
#define    PORT255_SPI_2_SIN_2        (PORT_INPUT2_MODE)
#define    PORT255_EMIOS1_E1UC_21_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT256_GPIO        (PORT_GPIO_MODE)
#define    PORT256_DSPI_0_dCS1        (PORT_ALT1_FUNC_MODE)
#define    PORT257_GPIO        (PORT_GPIO_MODE)
#define    PORT257_DSPI_0_dCS0        (PORT_ALT1_FUNC_MODE)
#define    PORT257_DSPI_0_dSS        (PORT_INPUT1_MODE)
#define    PORT258_GPIO        (PORT_GPIO_MODE)
#define    PORT258_DSPI_0_dSCLK_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT258_DSPI_0_dSCLK_IN        (PORT_INPUT1_MODE)
#define    PORT258_DSPI_0_dSCLK_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT259_GPIO        (PORT_GPIO_MODE)
#define    PORT259_DSPI_0_dSIN        (PORT_INPUT1_MODE)
#define    PORT260_GPIO        (PORT_GPIO_MODE)
#define    PORT260_DSPI_0_dSOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT260_EMIOS1_E1UC_28_Y_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT260_EMIOS1_E1UC_28_Y_IN        (PORT_INPUT1_MODE)
#define    PORT260_GLITCH_FILTER2_INP        (PORT_INPUT2_MODE)
#define    PORT260_EMIOS1_E1UC_28_Y_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT261_GPIO        (PORT_GPIO_MODE)
#define    PORT261_SPI_2_CS3_2        (PORT_ALT1_FUNC_MODE)
#define    PORT261_DSPI_0_dCS3        (PORT_ALT2_FUNC_MODE)
#define    PORT261_EMIOS1_E1UC_27_Y_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT261_EMIOS1_E1UC_27_Y_IN        (PORT_INPUT1_MODE)
#define    PORT261_EMIOS1_E1UC_27_Y_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT262_GPIO        (PORT_GPIO_MODE)
#define    PORT262_SPI_2_CS2_2        (PORT_ALT1_FUNC_MODE)
#define    PORT262_DSPI_0_dCS2        (PORT_ALT2_FUNC_MODE)
#define    PORT262_EMIOS1_E1UC_26_Y_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT262_EMIOS1_E1UC_26_Y_IN        (PORT_INPUT1_MODE)
#define    PORT262_EMIOS1_E1UC_26_Y_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT263_GPIO        (PORT_GPIO_MODE)
#define    PORT263_SPI_2_CS1_2        (PORT_ALT1_FUNC_MODE)
#define    PORT263_DSPI_0_dCS5        (PORT_ALT2_FUNC_MODE)
#define    PORT263_EMIOS1_E1UC_25_Y_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT263_EMIOS1_E1UC_25_Y_IN        (PORT_INPUT1_MODE)
#define    PORT263_EMIOS1_E1UC_25_Y_IN_OUT        (PORT_INOUT3_MODE)
[!ENDVAR!]




[!VAR "PinAbstractionModes_4"!]

#define    PORT0_GPIO        (PORT_GPIO_MODE)
#define    PORT0_EMIOS0_E0UC_0_X_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT0_CGM_CLKOUT0        (PORT_ALT2_FUNC_MODE)
#define    PORT0_EMIOS0_E0UC_13_H_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT0_WKPU_WKPU_19        (PORT_ONLY_INPUT_MODE)
#define    PORT0_EMIOS0_E0UC_0_X_IN        (PORT_INPUT1_MODE)
#define    PORT0_EMIOS0_E0UC_13_H_IN        (PORT_INPUT2_MODE)
#define    PORT0_EMIOS0_E0UC_0_X_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT0_EMIOS0_E0UC_13_H_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT0_FlexCAN_1_RX        (PORT_INPUT3_MODE)
#define    PORT1_GPIO        (PORT_GPIO_MODE)
#define    PORT1_EMIOS0_E0UC_1_G_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT1_WKPU_WKPU_2        (PORT_ONLY_INPUT_MODE)
#define    PORT1_WKPU_NMI_0        (PORT_ONLY_INPUT_MODE)
#define    PORT1_EMIOS0_E0UC_1_G_IN        (PORT_INPUT1_MODE)
#define    PORT1_FlexCAN_3_RX        (PORT_INPUT2_MODE)
#define    PORT1_EMIOS0_E0UC_1_G_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT2_GPIO        (PORT_GPIO_MODE)
#define    PORT2_EMIOS0_E0UC_2_G_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT2_ADC_0_ADC0_MA_2        (PORT_ALT3_FUNC_MODE)
#define    PORT2_WKPU_WKPU_3        (PORT_ONLY_INPUT_MODE)
#define    PORT2_EMIOS0_E0UC_2_G_IN        (PORT_INPUT1_MODE)
#define    PORT2_EMIOS0_E0UC_2_G_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT3_GPIO        (PORT_GPIO_MODE)
#define    PORT3_EMIOS0_E0UC_3_G_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT3_LIN_5_LIN5TX        (PORT_ALT2_FUNC_MODE)
#define    PORT3_DSPI_1_dCS4        (PORT_ALT3_FUNC_MODE)
#define    PORT3_ADC_1_ADC1_S_0        (PORT_ANALOG_INPUT_MODE)
#define    PORT3_EMIOS0_E0UC_3_G_IN        (PORT_INPUT1_MODE)
#define    PORT3_SIUL2_EIRQ0        (PORT_INPUT2_MODE)
#define    PORT3_ENET0_MII_0_RX_CLK        (PORT_INPUT3_MODE)
#define    PORT3_EMIOS0_E0UC_3_G_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT4_GPIO        (PORT_GPIO_MODE)
#define    PORT4_EMIOS0_E0UC_4_G_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT4_DSPI_1_dCS0        (PORT_ALT2_FUNC_MODE)
#define    PORT4_EMIOS0_E0UC_24_X_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT4_WKPU_WKPU_9        (PORT_ONLY_INPUT_MODE)
#define    PORT4_CMP1_CMP1_13        (PORT_ANALOG_INPUT_MODE)
#define    PORT4_EMIOS0_E0UC_4_G_IN        (PORT_INPUT1_MODE)
#define    PORT4_LIN_5_LIN5RX        (PORT_INPUT2_MODE)
#define    PORT4_DSPI_1_dSS        (PORT_INPUT3_MODE)
#define    PORT4_EMIOS0_E0UC_24_X_IN        (PORT_INPUT4_MODE)
#define    PORT4_EMIOS0_E0UC_4_G_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT4_EMIOS0_E0UC_24_X_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT5_GPIO        (PORT_GPIO_MODE)
#define    PORT5_EMIOS0_E0UC_5_G_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT5_LIN_4_LIN4TX        (PORT_ALT2_FUNC_MODE)
#define    PORT5_EMIOS0_E0UC_5_G_IN        (PORT_INPUT1_MODE)
#define    PORT5_EMIOS0_E0UC_5_G_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT6_GPIO        (PORT_GPIO_MODE)
#define    PORT6_EMIOS0_E0UC_6_G_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT6_DSPI_1_dCS1        (PORT_ALT2_FUNC_MODE)
#define    PORT6_EMIOS0_E0UC_6_G_IN        (PORT_INPUT1_MODE)
#define    PORT6_SIUL2_EIRQ1        (PORT_INPUT2_MODE)
#define    PORT6_LIN_4_LIN4RX        (PORT_INPUT3_MODE)
#define    PORT6_EMIOS0_E0UC_6_G_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT7_GPIO        (PORT_GPIO_MODE)
#define    PORT7_EMIOS0_E0UC_7_G_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT7_LIN_3_LIN3TX        (PORT_ALT2_FUNC_MODE)
#define    PORT7_ADC_1_ADC1_S_8        (PORT_ANALOG_INPUT_MODE)
#define    PORT7_EMIOS0_E0UC_7_G_IN        (PORT_INPUT1_MODE)
#define    PORT7_SIUL2_EIRQ2        (PORT_INPUT2_MODE)
#define    PORT7_ENET0_MII_0_RXD_2        (PORT_INPUT3_MODE)
#define    PORT7_EMIOS0_E0UC_7_G_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT8_GPIO        (PORT_GPIO_MODE)
#define    PORT8_EMIOS0_E0UC_8_X_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT8_EMIOS0_E0UC_14_H_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT8_ADC_1_ADC1_S_9        (PORT_ANALOG_INPUT_MODE)
#define    PORT8_EMIOS0_E0UC_8_X_IN        (PORT_INPUT1_MODE)
#define    PORT8_EMIOS0_E0UC_14_H_IN        (PORT_INPUT2_MODE)
#define    PORT8_SIUL2_EIRQ3        (PORT_INPUT3_MODE)
#define    PORT8_LIN_3_LIN3RX        (PORT_INPUT4_MODE)
#define    PORT8_ENET0_MII_RMII_0_RXD_1        (PORT_INPUT5_MODE)
#define    PORT8_EMIOS0_E0UC_8_X_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT8_EMIOS0_E0UC_14_H_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT9_GPIO        (PORT_GPIO_MODE)
#define    PORT9_EMIOS0_E0UC_9_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT9_DSPI_1_dCS2        (PORT_ALT2_FUNC_MODE)
#define    PORT9_ADC_1_ADC1_S_10        (PORT_ANALOG_INPUT_MODE)
#define    PORT9_EMIOS0_E0UC_9_H_IN        (PORT_INPUT1_MODE)
#define    PORT9_ENET0_MII_RMII_0_RXD_0        (PORT_INPUT2_MODE)
#define    PORT9_EMIOS0_E0UC_9_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT10_GPIO        (PORT_GPIO_MODE)
#define    PORT10_EMIOS0_E0UC_10_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT10_IIC_0_SDA0_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT10_LIN_2_LIN2TX        (PORT_ALT3_FUNC_MODE)
#define    PORT10_ADC_1_ADC1_S_11        (PORT_ANALOG_INPUT_MODE)
#define    PORT10_EMIOS0_E0UC_10_H_IN        (PORT_INPUT1_MODE)
#define    PORT10_IIC_0_SDA0_IN        (PORT_INPUT2_MODE)
#define    PORT10_DSPI_1_dSIN        (PORT_INPUT3_MODE)
#define    PORT10_ENET0_MII_0_COL        (PORT_INPUT4_MODE)
#define    PORT10_EMIOS0_E0UC_10_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT10_IIC_0_SDA0_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT11_GPIO        (PORT_GPIO_MODE)
#define    PORT11_EMIOS0_E0UC_11_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT11_IIC_0_SCL0_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT11_ADC_1_ADC1_S_12        (PORT_ANALOG_INPUT_MODE)
#define    PORT11_EMIOS0_E0UC_11_H_IN        (PORT_INPUT1_MODE)
#define    PORT11_SIUL2_EIRQ16        (PORT_INPUT2_MODE)
#define    PORT11_LIN_2_LIN2RX        (PORT_INPUT3_MODE)
#define    PORT11_IIC_0_SCL0_IN        (PORT_INPUT4_MODE)
#define    PORT11_ENET0_MII_RMII_0_RX_ER        (PORT_INPUT5_MODE)
#define    PORT11_EMIOS0_E0UC_11_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT11_IIC_0_SCL0_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT12_GPIO        (PORT_GPIO_MODE)
#define    PORT12_EMIOS0_E0UC_28_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT12_DSPI_1_dCS3        (PORT_ALT2_FUNC_MODE)
#define    PORT12_EMIOS0_E0UC_26_Y_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT12_CMP1_CMP1_15        (PORT_ANALOG_INPUT_MODE)
#define    PORT12_EMIOS0_E0UC_28_Y_IN        (PORT_INPUT1_MODE)
#define    PORT12_SIUL2_EIRQ17        (PORT_INPUT2_MODE)
#define    PORT12_DSPI_0_dSIN        (PORT_INPUT3_MODE)
#define    PORT12_EMIOS0_E0UC_26_Y_IN        (PORT_INPUT4_MODE)
#define    PORT12_GLITCH_FILTER0_INP        (PORT_INPUT5_MODE)
#define    PORT12_EMIOS0_E0UC_28_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT12_EMIOS0_E0UC_26_Y_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT13_GPIO        (PORT_GPIO_MODE)
#define    PORT13_DSPI_0_dSOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT13_EMIOS0_E0UC_29_Y_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT13_FlexCAN_0_TX        (PORT_ALT4_FUNC_MODE)
#define    PORT13_EMIOS0_E0UC_25_Y_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT13_CMP1_CMP1_14        (PORT_ANALOG_INPUT_MODE)
#define    PORT13_EMIOS0_E0UC_29_Y_IN        (PORT_INPUT1_MODE)
#define    PORT13_EMIOS0_E0UC_25_Y_IN        (PORT_INPUT2_MODE)
#define    PORT13_GLITCH_FILTER0_INP        (PORT_INPUT3_MODE)
#define    PORT13_EMIOS0_E0UC_29_Y_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT13_EMIOS0_E0UC_25_Y_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT14_GPIO        (PORT_GPIO_MODE)
#define    PORT14_DSPI_0_dSCLK_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT14_DSPI_0_dCS0        (PORT_ALT2_FUNC_MODE)
#define    PORT14_EMIOS0_E0UC_0_X_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT14_EMIOS0_E0UC_23_X_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT14_CMP1_CMP1_12        (PORT_ANALOG_INPUT_MODE)
#define    PORT14_EMIOS0_E0UC_0_X_IN        (PORT_INPUT1_MODE)
#define    PORT14_SIUL2_EIRQ4        (PORT_INPUT2_MODE)
#define    PORT14_DSPI_0_dSCLK_IN        (PORT_INPUT3_MODE)
#define    PORT14_DSPI_0_dSS        (PORT_INPUT4_MODE)
#define    PORT14_EMIOS0_E0UC_23_X_IN        (PORT_INPUT5_MODE)
#define    PORT14_DSPI_0_dSCLK_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT14_EMIOS0_E0UC_0_X_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT14_EMIOS0_E0UC_23_X_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT15_GPIO        (PORT_GPIO_MODE)
#define    PORT15_DSPI_0_dCS0        (PORT_ALT1_FUNC_MODE)
#define    PORT15_DSPI_0_dSCLK_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT15_EMIOS0_E0UC_1_G_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT15_EMIOS0_E0UC_21_Y_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT15_WKPU_WKPU_10        (PORT_ONLY_INPUT_MODE)
#define    PORT15_CMP1_CMP1_10        (PORT_ANALOG_INPUT_MODE)
#define    PORT15_EMIOS0_E0UC_1_G_IN        (PORT_INPUT1_MODE)
#define    PORT15_FlexCAN_0_RX        (PORT_INPUT2_MODE)
#define    PORT15_DSPI_0_dSCLK_IN        (PORT_INPUT3_MODE)
#define    PORT15_DSPI_0_dSS        (PORT_INPUT4_MODE)
#define    PORT15_EMIOS0_E0UC_21_Y_IN        (PORT_INPUT5_MODE)
#define    PORT15_DSPI_0_dSCLK_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT15_EMIOS0_E0UC_1_G_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT15_EMIOS0_E0UC_21_Y_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT16_GPIO        (PORT_GPIO_MODE)
#define    PORT16_FlexCAN_0_TX        (PORT_ALT1_FUNC_MODE)
#define    PORT16_EMIOS0_E0UC_30_Y_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT16_LIN_0_LIN0TX        (PORT_ALT3_FUNC_MODE)
#define    PORT16_EMIOS0_E0UC_4_G_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT16_CMP0_CMP0_2        (PORT_ANALOG_INPUT_MODE)
#define    PORT16_EMIOS0_E0UC_30_Y_IN        (PORT_INPUT1_MODE)
#define    PORT16_EMIOS0_E0UC_4_G_IN        (PORT_INPUT2_MODE)
#define    PORT16_GLITCH_FILTER1_INP        (PORT_INPUT3_MODE)
#define    PORT16_EMIOS0_E0UC_30_Y_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT16_EMIOS0_E0UC_4_G_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT17_GPIO        (PORT_GPIO_MODE)
#define    PORT17_EMIOS0_E0UC_31_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT17_EMIOS0_E0UC_5_G_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT17_WKPU_WKPU_4        (PORT_ONLY_INPUT_MODE)
#define    PORT17_CMP0_CMP0_3        (PORT_ANALOG_INPUT_MODE)
#define    PORT17_EMIOS0_E0UC_31_Y_IN        (PORT_INPUT1_MODE)
#define    PORT17_FlexCAN_0_RX        (PORT_INPUT2_MODE)
#define    PORT17_LIN_0_LIN0RX        (PORT_INPUT3_MODE)
#define    PORT17_EMIOS0_E0UC_5_G_IN        (PORT_INPUT4_MODE)
#define    PORT17_GLITCH_FILTER1_INP        (PORT_INPUT5_MODE)
#define    PORT17_EMIOS0_E0UC_31_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT17_EMIOS0_E0UC_5_G_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT18_GPIO        (PORT_GPIO_MODE)
#define    PORT18_LIN_0_LIN0TX        (PORT_ALT1_FUNC_MODE)
#define    PORT18_IIC_0_SDA0_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT18_EMIOS0_E0UC_30_Y_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT18_EMIOS0_E0UC_30_Y_IN        (PORT_INPUT1_MODE)
#define    PORT18_IIC_0_SDA0_IN        (PORT_INPUT2_MODE)
#define    PORT18_GLITCH_FILTER1_INP        (PORT_INPUT3_MODE)
#define    PORT18_IIC_0_SDA0_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT18_EMIOS0_E0UC_30_Y_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT19_GPIO        (PORT_GPIO_MODE)
#define    PORT19_EMIOS0_E0UC_31_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT19_IIC_0_SCL0_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT19_EMIOS0_E0UC_8_X_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT19_WKPU_WKPU_11        (PORT_ONLY_INPUT_MODE)
#define    PORT19_EMIOS0_E0UC_31_Y_IN        (PORT_INPUT1_MODE)
#define    PORT19_LIN_0_LIN0RX        (PORT_INPUT2_MODE)
#define    PORT19_IIC_0_SCL0_IN        (PORT_INPUT3_MODE)
#define    PORT19_EMIOS0_E0UC_8_X_IN        (PORT_INPUT4_MODE)
#define    PORT19_GLITCH_FILTER1_INP        (PORT_INPUT5_MODE)
#define    PORT19_EMIOS0_E0UC_31_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT19_IIC_0_SCL0_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT19_EMIOS0_E0UC_8_X_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT20_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT20_ADC_1_ADC1_P_0        (PORT_ANALOG_INPUT_MODE)
#define    PORT21_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT21_ADC_1_ADC1_P_1        (PORT_ANALOG_INPUT_MODE)
#define    PORT22_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT22_ADC_1_ADC1_P_2        (PORT_ANALOG_INPUT_MODE)
#define    PORT23_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT23_ADC_1_ADC1_P_3        (PORT_ANALOG_INPUT_MODE)
#define    PORT24_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT24_ADC_0_ADC0_S_0        (PORT_ANALOG_INPUT_MODE)
#define    PORT24_WKPU_WKPU_25        (PORT_ONLY_INPUT_MODE)
#define    PORT24_XOSC_OSC32K_XTAL        (PORT_ONLY_INPUT_MODE)
#define    PORT25_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT25_ADC_0_ADC0_S_1        (PORT_ANALOG_INPUT_MODE)
#define    PORT25_WKPU_WKPU_26        (PORT_ONLY_INPUT_MODE)
#define    PORT25_XOSC_OSC32K_EXTAL        (PORT_ONLY_INPUT_MODE)
#define    PORT26_GPIO        (PORT_GPIO_MODE)
#define    PORT26_DSPI_1_dSOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT26_FlexCAN_3_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT26_CMP2_CMP2_O        (PORT_ALT3_FUNC_MODE)
#define    PORT26_SAI0_SAI0_SYNC_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT26_EMIOS0_E0UC_29_Y_OUT        (PORT_ALT5_FUNC_MODE)
#define    PORT26_ADC_0_ADC0_S_2        (PORT_ANALOG_INPUT_MODE)
#define    PORT26_WKPU_WKPU_8        (PORT_ONLY_INPUT_MODE)
#define    PORT26_FlexCAN_6_RX        (PORT_INPUT1_MODE)
#define    PORT26_SAI0_SAI0_SYNC_IN        (PORT_INPUT2_MODE)
#define    PORT26_EMIOS0_E0UC_29_Y_IN        (PORT_INPUT3_MODE)
#define    PORT26_SAI0_SAI0_SYNC_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT26_EMIOS0_E0UC_29_Y_IN_OUT        (PORT_INOUT5_MODE)
#define    PORT27_GPIO        (PORT_GPIO_MODE)
#define    PORT27_EMIOS0_E0UC_3_G_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT27_DSPI_0_dCS0        (PORT_ALT2_FUNC_MODE)
#define    PORT27_ADC_0_ADC0_S_3        (PORT_ANALOG_INPUT_MODE)
#define    PORT27_EMIOS0_E0UC_3_G_IN        (PORT_INPUT1_MODE)
#define    PORT27_DSPI_0_dSS        (PORT_INPUT2_MODE)
#define    PORT27_EMIOS0_E0UC_3_G_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT28_GPIO        (PORT_GPIO_MODE)
#define    PORT28_EMIOS0_E0UC_4_G_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT28_DSPI_0_dCS1        (PORT_ALT2_FUNC_MODE)
#define    PORT28_HSM_DO1        (PORT_ALT3_FUNC_MODE)
#define    PORT28_ADC_0_ADC0_X_0        (PORT_ANALOG_INPUT_MODE)
#define    PORT28_EMIOS0_E0UC_4_G_IN        (PORT_INPUT1_MODE)
#define    PORT28_EMIOS0_E0UC_4_G_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT29_GPIO        (PORT_GPIO_MODE)
#define    PORT29_EMIOS0_E0UC_5_G_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT29_DSPI_0_dCS2        (PORT_ALT2_FUNC_MODE)
#define    PORT29_ADC_0_ADC0_X_1        (PORT_ANALOG_INPUT_MODE)
#define    PORT29_EMIOS0_E0UC_5_G_IN        (PORT_INPUT1_MODE)
#define    PORT29_EMIOS0_E0UC_5_G_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT30_GPIO        (PORT_GPIO_MODE)
#define    PORT30_EMIOS0_E0UC_6_G_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT30_DSPI_0_dCS3        (PORT_ALT2_FUNC_MODE)
#define    PORT30_FlexRay_FR_DBG_1        (PORT_ALT3_FUNC_MODE)
#define    PORT30_ADC_0_ADC0_X_2        (PORT_ANALOG_INPUT_MODE)
#define    PORT30_EMIOS0_E0UC_6_G_IN        (PORT_INPUT1_MODE)
#define    PORT30_EMIOS0_E0UC_6_G_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT31_GPIO        (PORT_GPIO_MODE)
#define    PORT31_EMIOS0_E0UC_7_G_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT31_DSPI_0_dCS4        (PORT_ALT2_FUNC_MODE)
#define    PORT31_ADC_0_ADC0_X_3        (PORT_ANALOG_INPUT_MODE)
#define    PORT31_EMIOS0_E0UC_7_G_IN        (PORT_INPUT1_MODE)
#define    PORT31_EMIOS0_E0UC_7_G_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT32_GPIO        (PORT_GPIO_MODE)
#define    PORT32_DCI_TDI        (PORT_ALT1_FUNC_MODE)
#define    PORT33_GPIO        (PORT_GPIO_MODE)
#define    PORT33_DCI_TDO        (PORT_ALT1_FUNC_MODE)
#define    PORT34_GPIO        (PORT_GPIO_MODE)
#define    PORT34_DSPI_1_dSCLK_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT34_FlexCAN_4_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT34_SSCM_SSCM_DBG_0        (PORT_ALT4_FUNC_MODE)
#define    PORT34_SIUL2_EIRQ5        (PORT_INPUT1_MODE)
#define    PORT34_DSPI_1_dSCLK_IN        (PORT_INPUT2_MODE)
#define    PORT34_DSPI_1_dSCLK_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT35_GPIO        (PORT_GPIO_MODE)
#define    PORT35_DSPI_1_dCS0        (PORT_ALT1_FUNC_MODE)
#define    PORT35_ADC_0_ADC0_MA_0        (PORT_ALT2_FUNC_MODE)
#define    PORT35_SSCM_SSCM_DBG_1        (PORT_ALT4_FUNC_MODE)
#define    PORT35_SIUL2_EIRQ6        (PORT_INPUT1_MODE)
#define    PORT35_FlexCAN_1_RX        (PORT_INPUT2_MODE)
#define    PORT35_FlexCAN_4_RX        (PORT_INPUT3_MODE)
#define    PORT35_DSPI_1_dSS        (PORT_INPUT4_MODE)
#define    PORT36_GPIO        (PORT_GPIO_MODE)
#define    PORT36_EMIOS1_E1UC_31_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT36_FlexRay_FR_B_TX_EN        (PORT_ALT2_FUNC_MODE)
#define    PORT36_SSCM_SSCM_DBG_2        (PORT_ALT5_FUNC_MODE)
#define    PORT36_EMIOS1_E1UC_31_Y_IN        (PORT_INPUT1_MODE)
#define    PORT36_SIUL2_EIRQ18        (PORT_INPUT2_MODE)
#define    PORT36_FlexCAN_3_RX        (PORT_INPUT3_MODE)
#define    PORT36_DSPI_1_dSIN        (PORT_INPUT4_MODE)
#define    PORT36_GLITCH_FILTER3_INP        (PORT_INPUT5_MODE)
#define    PORT36_EMIOS1_E1UC_31_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT37_GPIO        (PORT_GPIO_MODE)
#define    PORT37_DSPI_1_dSOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT37_FlexCAN_3_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT37_FlexRay_FR_A_TX        (PORT_ALT4_FUNC_MODE)
#define    PORT37_SSCM_SSCM_DBG_3        (PORT_ALT7_FUNC_MODE)
#define    PORT37_SIUL2_EIRQ7        (PORT_INPUT1_MODE)
#define    PORT38_GPIO        (PORT_GPIO_MODE)
#define    PORT38_LIN_1_LIN1TX        (PORT_ALT1_FUNC_MODE)
#define    PORT38_EMIOS1_E1UC_28_Y_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT38_SSCM_SSCM_DBG_4        (PORT_ALT4_FUNC_MODE)
#define    PORT38_EMIOS0_E0UC_17_Y_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT38_CMP0_CMP0_7        (PORT_ANALOG_INPUT_MODE)
#define    PORT38_EMIOS1_E1UC_28_Y_IN        (PORT_INPUT1_MODE)
#define    PORT38_EMIOS0_E0UC_17_Y_IN        (PORT_INPUT2_MODE)
#define    PORT38_GLITCH_FILTER2_INP        (PORT_INPUT3_MODE)
#define    PORT38_EMIOS1_E1UC_28_Y_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT38_EMIOS0_E0UC_17_Y_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT39_GPIO        (PORT_GPIO_MODE)
#define    PORT39_EMIOS1_E1UC_29_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT39_CMP1_CMP1_O        (PORT_ALT2_FUNC_MODE)
#define    PORT39_SSCM_SSCM_DBG_5        (PORT_ALT4_FUNC_MODE)
#define    PORT39_EMIOS0_E0UC_18_Y_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT39_WKPU_WKPU_12        (PORT_ONLY_INPUT_MODE)
#define    PORT39_EMIOS1_E1UC_29_Y_IN        (PORT_INPUT1_MODE)
#define    PORT39_LIN_1_LIN1RX        (PORT_INPUT2_MODE)
#define    PORT39_EMIOS0_E0UC_18_Y_IN        (PORT_INPUT3_MODE)
#define    PORT39_GLITCH_FILTER2_INP        (PORT_INPUT4_MODE)
#define    PORT39_EMIOS1_E1UC_29_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT39_EMIOS0_E0UC_18_Y_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT40_GPIO        (PORT_GPIO_MODE)
#define    PORT40_LIN_2_LIN2TX        (PORT_ALT1_FUNC_MODE)
#define    PORT40_EMIOS0_E0UC_3_G_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT40_SSCM_SSCM_DBG_6        (PORT_ALT4_FUNC_MODE)
#define    PORT40_EMIOS0_E0UC_3_G_IN        (PORT_INPUT1_MODE)
#define    PORT40_EMIOS0_E0UC_3_G_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT41_GPIO        (PORT_GPIO_MODE)
#define    PORT41_EMIOS0_E0UC_7_G_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT41_SSCM_SSCM_DBG_7        (PORT_ALT3_FUNC_MODE)
#define    PORT41_WKPU_WKPU_13        (PORT_ONLY_INPUT_MODE)
#define    PORT41_EMIOS0_E0UC_7_G_IN        (PORT_INPUT1_MODE)
#define    PORT41_LIN_2_LIN2RX        (PORT_INPUT2_MODE)
#define    PORT41_EMIOS0_E0UC_7_G_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT42_GPIO        (PORT_GPIO_MODE)
#define    PORT42_FlexCAN_1_TX        (PORT_ALT1_FUNC_MODE)
#define    PORT42_FlexCAN_4_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT42_ADC_0_ADC0_MA_1        (PORT_ALT3_FUNC_MODE)
#define    PORT42_CMP0_CMP0_O        (PORT_ALT4_FUNC_MODE)
#define    PORT42_LIN_6_LIN6TX        (PORT_ALT6_FUNC_MODE)
#define    PORT43_GPIO        (PORT_GPIO_MODE)
#define    PORT43_ADC_0_ADC0_MA_2        (PORT_ALT1_FUNC_MODE)
#define    PORT43_EMIOS0_E0UC_1_G_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT43_WKPU_WKPU_5        (PORT_ONLY_INPUT_MODE)
#define    PORT43_FlexCAN_1_RX        (PORT_INPUT1_MODE)
#define    PORT43_FlexCAN_4_RX        (PORT_INPUT2_MODE)
#define    PORT43_EMIOS0_E0UC_1_G_IN        (PORT_INPUT3_MODE)
#define    PORT43_EMIOS0_E0UC_1_G_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT44_GPIO        (PORT_GPIO_MODE)
#define    PORT44_EMIOS0_E0UC_12_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT44_FlexRay_FR_DBG_0        (PORT_ALT2_FUNC_MODE)
#define    PORT44_EMIOS0_E0UC_12_H_IN        (PORT_INPUT1_MODE)
#define    PORT44_SIUL2_EIRQ19        (PORT_INPUT2_MODE)
#define    PORT44_DSPI_2_dSIN        (PORT_INPUT3_MODE)
#define    PORT44_EMIOS0_E0UC_12_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT45_GPIO        (PORT_GPIO_MODE)
#define    PORT45_EMIOS0_E0UC_13_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT45_DSPI_2_dSOUT        (PORT_ALT2_FUNC_MODE)
#define    PORT45_FlexRay_FR_DBG_1        (PORT_ALT3_FUNC_MODE)
#define    PORT45_EMIOS0_E0UC_13_H_IN        (PORT_INPUT1_MODE)
#define    PORT45_EMIOS0_E0UC_13_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT46_GPIO        (PORT_GPIO_MODE)
#define    PORT46_EMIOS0_E0UC_14_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT46_DSPI_2_dSCLK_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT46_FlexRay_FR_DBG_2        (PORT_ALT4_FUNC_MODE)
#define    PORT46_FlexCAN_4_TX        (PORT_ALT5_FUNC_MODE)
#define    PORT46_EMIOS0_E0UC_14_H_IN        (PORT_INPUT1_MODE)
#define    PORT46_SIUL2_EIRQ8        (PORT_INPUT2_MODE)
#define    PORT46_DSPI_2_dSCLK_IN        (PORT_INPUT3_MODE)
#define    PORT46_EMIOS0_E0UC_14_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT46_DSPI_2_dSCLK_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT47_GPIO        (PORT_GPIO_MODE)
#define    PORT47_EMIOS0_E0UC_15_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT47_DSPI_2_dCS0        (PORT_ALT2_FUNC_MODE)
#define    PORT47_FlexRay_FR_DBG_3        (PORT_ALT4_FUNC_MODE)
#define    PORT47_EMIOS0_E0UC_15_H_IN        (PORT_INPUT1_MODE)
#define    PORT47_SIUL2_EIRQ20        (PORT_INPUT2_MODE)
#define    PORT47_DSPI_2_dSS        (PORT_INPUT3_MODE)
#define    PORT47_FlexCAN_4_RX        (PORT_INPUT4_MODE)
#define    PORT47_EMIOS0_E0UC_15_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT48_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT48_ADC_1_ADC1_P_4        (PORT_ANALOG_INPUT_MODE)
#define    PORT48_WKPU_WKPU_27        (PORT_ONLY_INPUT_MODE)
#define    PORT49_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT49_ADC_1_ADC1_P_5        (PORT_ANALOG_INPUT_MODE)
#define    PORT49_WKPU_WKPU_28        (PORT_ONLY_INPUT_MODE)
#define    PORT50_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT50_ADC_1_ADC1_P_6        (PORT_ANALOG_INPUT_MODE)
#define    PORT51_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT51_ADC_1_ADC1_P_7        (PORT_ANALOG_INPUT_MODE)
#define    PORT52_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT52_ADC_1_ADC1_P_8        (PORT_ANALOG_INPUT_MODE)
#define    PORT53_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT53_ADC_1_ADC1_P_9        (PORT_ANALOG_INPUT_MODE)
#define    PORT54_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT54_ADC_1_ADC1_P_10        (PORT_ANALOG_INPUT_MODE)
#define    PORT55_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT55_ADC_1_ADC1_P_11        (PORT_ANALOG_INPUT_MODE)
#define    PORT56_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT56_ADC_1_ADC1_P_12        (PORT_ANALOG_INPUT_MODE)
#define    PORT57_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT57_ADC_1_ADC1_P_13        (PORT_ANALOG_INPUT_MODE)
#define    PORT58_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT58_ADC_1_ADC1_P_14        (PORT_ANALOG_INPUT_MODE)
#define    PORT59_GPI        (PORT_ONLY_INPUT_MODE)
#define    PORT59_ADC_1_ADC1_P_15        (PORT_ANALOG_INPUT_MODE)
#define    PORT60_GPIO        (PORT_GPIO_MODE)
#define    PORT60_DSPI_0_dCS5        (PORT_ALT1_FUNC_MODE)
#define    PORT60_EMIOS0_E0UC_24_X_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT60_HSM_DO0        (PORT_ALT3_FUNC_MODE)
#define    PORT60_ADC_0_ADC0_S_4        (PORT_ANALOG_INPUT_MODE)
#define    PORT60_EMIOS0_E0UC_24_X_IN        (PORT_INPUT1_MODE)
#define    PORT60_EMIOS0_E0UC_24_X_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT61_GPIO        (PORT_GPIO_MODE)
#define    PORT61_DSPI_1_dCS0        (PORT_ALT1_FUNC_MODE)
#define    PORT61_EMIOS0_E0UC_25_Y_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT61_ENET0_ENET0_TMR0_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT61_ADC_0_ADC0_S_5        (PORT_ANALOG_INPUT_MODE)
#define    PORT61_EMIOS0_E0UC_25_Y_IN        (PORT_INPUT1_MODE)
#define    PORT61_DSPI_1_dSS        (PORT_INPUT2_MODE)
#define    PORT61_ENET0_ENET0_TMR0_IN        (PORT_INPUT3_MODE)
#define    PORT61_EMIOS0_E0UC_25_Y_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT61_ENET0_ENET0_TMR0_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT62_GPIO        (PORT_GPIO_MODE)
#define    PORT62_DSPI_1_dCS1        (PORT_ALT1_FUNC_MODE)
#define    PORT62_EMIOS0_E0UC_26_Y_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT62_FlexRay_FR_DBG_0        (PORT_ALT3_FUNC_MODE)
#define    PORT62_ADC_0_ADC0_S_6        (PORT_ANALOG_INPUT_MODE)
#define    PORT62_EMIOS0_E0UC_26_Y_IN        (PORT_INPUT1_MODE)
#define    PORT62_EMIOS0_E0UC_26_Y_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT63_GPIO        (PORT_GPIO_MODE)
#define    PORT63_DSPI_1_dCS2        (PORT_ALT1_FUNC_MODE)
#define    PORT63_EMIOS0_E0UC_27_Y_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT63_FlexRay_FR_DBG_1        (PORT_ALT3_FUNC_MODE)
#define    PORT63_ADC_0_ADC0_S_7        (PORT_ANALOG_INPUT_MODE)
#define    PORT63_EMIOS0_E0UC_27_Y_IN        (PORT_INPUT1_MODE)
#define    PORT63_EMIOS0_E0UC_27_Y_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT64_GPIO        (PORT_GPIO_MODE)
#define    PORT64_EMIOS0_E0UC_16_X_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT64_IIC_1_SCL1_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT64_WKPU_WKPU_6        (PORT_ONLY_INPUT_MODE)
#define    PORT64_EMIOS0_E0UC_16_X_IN        (PORT_INPUT1_MODE)
#define    PORT64_FlexCAN_5_RX        (PORT_INPUT2_MODE)
#define    PORT64_LIN_11_LIN11RX        (PORT_INPUT3_MODE)
#define    PORT64_IIC_1_SCL1_IN        (PORT_INPUT4_MODE)
#define    PORT64_EMIOS0_E0UC_16_X_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT64_IIC_1_SCL1_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT65_GPIO        (PORT_GPIO_MODE)
#define    PORT65_EMIOS0_E0UC_17_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT65_FlexCAN_5_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT65_IIC_1_SDA1_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT65_EMIOS0_E0UC_17_Y_IN        (PORT_INPUT1_MODE)
#define    PORT65_IIC_1_SDA1_IN        (PORT_INPUT2_MODE)
#define    PORT65_EMIOS0_E0UC_17_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT65_IIC_1_SDA1_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT66_GPIO        (PORT_GPIO_MODE)
#define    PORT66_EMIOS0_E0UC_18_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT66_FlexRay_FR_A_TX_EN        (PORT_ALT2_FUNC_MODE)
#define    PORT66_EMIOS0_E0UC_18_Y_IN        (PORT_INPUT1_MODE)
#define    PORT66_SIUL2_EIRQ21        (PORT_INPUT2_MODE)
#define    PORT66_DSPI_1_dSIN        (PORT_INPUT3_MODE)
#define    PORT66_EMIOS0_E0UC_18_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT67_GPIO        (PORT_GPIO_MODE)
#define    PORT67_EMIOS0_E0UC_19_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT67_DSPI_1_dSOUT        (PORT_ALT2_FUNC_MODE)
#define    PORT67_WKPU_WKPU_29        (PORT_ONLY_INPUT_MODE)
#define    PORT67_EMIOS0_E0UC_19_Y_IN        (PORT_INPUT1_MODE)
#define    PORT67_FlexRay_FR_A_RX        (PORT_INPUT2_MODE)
#define    PORT67_EMIOS0_E0UC_19_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT68_GPIO        (PORT_GPIO_MODE)
#define    PORT68_EMIOS0_E0UC_20_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT68_DSPI_1_dSCLK_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT68_FlexRay_FR_B_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT68_EMIOS0_E0UC_20_Y_IN        (PORT_INPUT1_MODE)
#define    PORT68_SIUL2_EIRQ9        (PORT_INPUT2_MODE)
#define    PORT68_DSPI_1_dSCLK_IN        (PORT_INPUT3_MODE)
#define    PORT68_EMIOS0_E0UC_20_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT68_DSPI_1_dSCLK_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT69_GPIO        (PORT_GPIO_MODE)
#define    PORT69_EMIOS0_E0UC_21_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT69_DSPI_1_dCS0        (PORT_ALT2_FUNC_MODE)
#define    PORT69_ADC_0_ADC0_MA_2        (PORT_ALT3_FUNC_MODE)
#define    PORT69_WKPU_WKPU_30        (PORT_ONLY_INPUT_MODE)
#define    PORT69_EMIOS0_E0UC_21_Y_IN        (PORT_INPUT1_MODE)
#define    PORT69_FlexRay_FR_B_RX        (PORT_INPUT2_MODE)
#define    PORT69_DSPI_1_dSS        (PORT_INPUT3_MODE)
#define    PORT69_EMIOS0_E0UC_21_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT70_GPIO        (PORT_GPIO_MODE)
#define    PORT70_EMIOS0_E0UC_22_X_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT70_DSPI_0_dCS3        (PORT_ALT2_FUNC_MODE)
#define    PORT70_ADC_0_ADC0_MA_1        (PORT_ALT3_FUNC_MODE)
#define    PORT70_ADC_1_ADC1_MA_1        (PORT_ALT4_FUNC_MODE)
#define    PORT70_EMIOS0_E0UC_22_X_IN        (PORT_INPUT1_MODE)
#define    PORT70_SIUL2_EIRQ22        (PORT_INPUT2_MODE)
#define    PORT70_EMIOS0_E0UC_22_X_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT71_GPIO        (PORT_GPIO_MODE)
#define    PORT71_EMIOS0_E0UC_23_X_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT71_DSPI_0_dCS2        (PORT_ALT2_FUNC_MODE)
#define    PORT71_ADC_0_ADC0_MA_0        (PORT_ALT3_FUNC_MODE)
#define    PORT71_ADC_1_ADC1_MA_0        (PORT_ALT4_FUNC_MODE)
#define    PORT71_EMIOS0_E0UC_23_X_IN        (PORT_INPUT1_MODE)
#define    PORT71_SIUL2_EIRQ23        (PORT_INPUT2_MODE)
#define    PORT71_EMIOS0_E0UC_23_X_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT72_GPIO        (PORT_GPIO_MODE)
#define    PORT72_FlexCAN_2_TX        (PORT_ALT1_FUNC_MODE)
#define    PORT72_EMIOS0_E0UC_22_X_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT72_FlexCAN_3_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT72_IIC_2_SDA2_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT72_LIN_6_LIN6TX        (PORT_ALT5_FUNC_MODE)
#define    PORT72_EMIOS0_E0UC_22_X_IN        (PORT_INPUT1_MODE)
#define    PORT72_IIC_2_SDA2_IN        (PORT_INPUT2_MODE)
#define    PORT72_EMIOS0_E0UC_22_X_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT72_IIC_2_SDA2_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT73_GPIO        (PORT_GPIO_MODE)
#define    PORT73_EMIOS0_E0UC_23_X_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT73_IIC_2_SCL2_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT73_WKPU_WKPU_7        (PORT_ONLY_INPUT_MODE)
#define    PORT73_EMIOS0_E0UC_23_X_IN        (PORT_INPUT1_MODE)
#define    PORT73_FlexCAN_2_RX        (PORT_INPUT2_MODE)
#define    PORT73_FlexCAN_3_RX        (PORT_INPUT3_MODE)
#define    PORT73_IIC_2_SCL2_IN        (PORT_INPUT4_MODE)
#define    PORT73_EMIOS0_E0UC_23_X_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT73_IIC_2_SCL2_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT74_GPIO        (PORT_GPIO_MODE)
#define    PORT74_LIN_3_LIN3TX        (PORT_ALT1_FUNC_MODE)
#define    PORT74_DSPI_1_dCS3        (PORT_ALT2_FUNC_MODE)
#define    PORT74_EMIOS1_E1UC_30_Y_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT74_IIC_3_SDA3_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT74_EMIOS1_E1UC_30_Y_IN        (PORT_INPUT1_MODE)
#define    PORT74_SIUL2_EIRQ10        (PORT_INPUT2_MODE)
#define    PORT74_IIC_3_SDA3_IN        (PORT_INPUT3_MODE)
#define    PORT74_GLITCH_FILTER3_INP        (PORT_INPUT4_MODE)
#define    PORT74_EMIOS1_E1UC_30_Y_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT74_IIC_3_SDA3_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT75_GPIO        (PORT_GPIO_MODE)
#define    PORT75_EMIOS0_E0UC_24_X_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT75_DSPI_1_dCS4        (PORT_ALT2_FUNC_MODE)
#define    PORT75_CGM_CLKOUT1        (PORT_ALT3_FUNC_MODE)
#define    PORT75_IIC_3_SCL3_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT75_WKPU_WKPU_14        (PORT_ONLY_INPUT_MODE)
#define    PORT75_EMIOS0_E0UC_24_X_IN        (PORT_INPUT1_MODE)
#define    PORT75_LIN_3_LIN3RX        (PORT_INPUT2_MODE)
#define    PORT75_IIC_3_SCL3_IN        (PORT_INPUT3_MODE)
#define    PORT75_EMIOS0_E0UC_24_X_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT75_IIC_3_SCL3_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT76_GPIO        (PORT_GPIO_MODE)
#define    PORT76_EMIOS1_E1UC_19_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT76_ADC_1_ADC1_S_13        (PORT_ANALOG_INPUT_MODE)
#define    PORT76_EMIOS1_E1UC_19_Y_IN        (PORT_INPUT1_MODE)
#define    PORT76_SIUL2_EIRQ11        (PORT_INPUT2_MODE)
#define    PORT76_DSPI_2_dSIN        (PORT_INPUT3_MODE)
#define    PORT76_ENET0_MII_0_CRS        (PORT_INPUT4_MODE)
#define    PORT76_EMIOS1_E1UC_19_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT77_GPIO        (PORT_GPIO_MODE)
#define    PORT77_DSPI_2_dSOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT77_EMIOS1_E1UC_20_Y_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT77_ADC_1_ADC1_X_3        (PORT_ANALOG_INPUT_MODE)
#define    PORT77_EMIOS1_E1UC_20_Y_IN        (PORT_INPUT1_MODE)
#define    PORT77_ENET0_MII_0_RXD_3        (PORT_INPUT2_MODE)
#define    PORT77_EMIOS1_E1UC_20_Y_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT78_GPIO        (PORT_GPIO_MODE)
#define    PORT78_DSPI_2_dSCLK_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT78_EMIOS1_E1UC_21_Y_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT78_EMIOS1_E1UC_21_Y_IN        (PORT_INPUT1_MODE)
#define    PORT78_SIUL2_EIRQ12        (PORT_INPUT2_MODE)
#define    PORT78_DSPI_2_dSCLK_IN        (PORT_INPUT3_MODE)
#define    PORT78_DSPI_2_dSCLK_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT78_EMIOS1_E1UC_21_Y_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT79_GPIO        (PORT_GPIO_MODE)
#define    PORT79_DSPI_2_dCS0        (PORT_ALT1_FUNC_MODE)
#define    PORT79_EMIOS1_E1UC_22_X_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT79_SPI_2_SCLK_2_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT79_EMIOS1_E1UC_22_X_IN        (PORT_INPUT1_MODE)
#define    PORT79_DSPI_2_dSS        (PORT_INPUT2_MODE)
#define    PORT79_SPI_2_SCLK_2_IN        (PORT_INPUT3_MODE)
#define    PORT79_EMIOS1_E1UC_22_X_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT79_SPI_2_SCLK_2_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT80_GPIO        (PORT_GPIO_MODE)
#define    PORT80_EMIOS0_E0UC_10_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT80_DSPI_1_dCS3        (PORT_ALT2_FUNC_MODE)
#define    PORT80_FlexCAN_6_TX        (PORT_ALT4_FUNC_MODE)
#define    PORT80_ADC_0_ADC0_S_8        (PORT_ANALOG_INPUT_MODE)
#define    PORT80_CMP2_CMP2_16        (PORT_ANALOG_INPUT_MODE)
#define    PORT80_SAI0_SAI0_MCLK_OUT        (PORT_ALT7_FUNC_MODE)
#define    PORT80_EMIOS0_E0UC_10_H_IN        (PORT_INPUT1_MODE)
#define    PORT80_SAI0_SAI0_MCLK_IN        (PORT_INPUT2_MODE)
#define    PORT80_EMIOS0_E0UC_10_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT80_SAI0_SAI0_MCLK_IN_OUT        (PORT_INOUT7_MODE)
#define    PORT81_GPIO        (PORT_GPIO_MODE)
#define    PORT81_EMIOS0_E0UC_11_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT81_DSPI_1_dCS4        (PORT_ALT2_FUNC_MODE)
#define    PORT81_SPI_0_CS3_0        (PORT_ALT3_FUNC_MODE)
#define    PORT81_SAI0_SAI0_BCLK_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT81_ADC_0_ADC0_S_9        (PORT_ANALOG_INPUT_MODE)
#define    PORT81_CMP2_CMP2_17        (PORT_ANALOG_INPUT_MODE)
#define    PORT81_EMIOS0_E0UC_11_H_IN        (PORT_INPUT1_MODE)
#define    PORT81_SAI0_SAI0_BCLK_IN        (PORT_INPUT2_MODE)
#define    PORT81_EMIOS0_E0UC_11_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT81_SAI0_SAI0_BCLK_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT82_GPIO        (PORT_GPIO_MODE)
#define    PORT82_EMIOS0_E0UC_12_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT82_DSPI_2_dCS0        (PORT_ALT2_FUNC_MODE)
#define    PORT82_SAI0_SAI0_D3_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT82_ADC_0_ADC0_S_10        (PORT_ANALOG_INPUT_MODE)
#define    PORT82_CMP2_CMP2_18        (PORT_ANALOG_INPUT_MODE)
#define    PORT82_EMIOS0_E0UC_12_H_IN        (PORT_INPUT1_MODE)
#define    PORT82_DSPI_2_dSS        (PORT_INPUT2_MODE)
#define    PORT82_SAI0_SAI0_D3_IN        (PORT_INPUT3_MODE)
#define    PORT82_GLITCH_FILTER0_INP        (PORT_INPUT4_MODE)
#define    PORT82_EMIOS0_E0UC_12_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT82_SAI0_SAI0_D3_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT83_GPIO        (PORT_GPIO_MODE)
#define    PORT83_EMIOS0_E0UC_13_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT83_DSPI_2_dCS1        (PORT_ALT2_FUNC_MODE)
#define    PORT83_SAI0_SAI0_D2_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT83_ADC_0_ADC0_S_11        (PORT_ANALOG_INPUT_MODE)
#define    PORT83_CMP2_CMP2_19        (PORT_ANALOG_INPUT_MODE)
#define    PORT83_EMIOS0_E0UC_13_H_IN        (PORT_INPUT1_MODE)
#define    PORT83_SAI0_SAI0_D2_IN        (PORT_INPUT2_MODE)
#define    PORT83_GLITCH_FILTER1_INP        (PORT_INPUT3_MODE)
#define    PORT83_EMIOS0_E0UC_13_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT83_SAI0_SAI0_D2_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT84_GPIO        (PORT_GPIO_MODE)
#define    PORT84_EMIOS0_E0UC_14_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT84_DSPI_2_dCS2        (PORT_ALT2_FUNC_MODE)
#define    PORT84_SAI0_SAI0_D1_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT84_ADC_0_ADC0_S_12        (PORT_ANALOG_INPUT_MODE)
#define    PORT84_CMP2_CMP2_20        (PORT_ANALOG_INPUT_MODE)
#define    PORT84_EMIOS0_E0UC_14_H_IN        (PORT_INPUT1_MODE)
#define    PORT84_SAI0_SAI0_D1_IN        (PORT_INPUT2_MODE)
#define    PORT84_GLITCH_FILTER2_INP        (PORT_INPUT3_MODE)
#define    PORT84_EMIOS0_E0UC_14_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT84_SAI0_SAI0_D1_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT85_GPIO        (PORT_GPIO_MODE)
#define    PORT85_EMIOS0_E0UC_22_X_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT85_DSPI_2_dCS3        (PORT_ALT2_FUNC_MODE)
#define    PORT85_SPI_0_CS2_0        (PORT_ALT3_FUNC_MODE)
#define    PORT85_SAI0_SAI0_D0_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT85_ADC_0_ADC0_S_13        (PORT_ANALOG_INPUT_MODE)
#define    PORT85_CMP2_CMP2_21        (PORT_ANALOG_INPUT_MODE)
#define    PORT85_EMIOS0_E0UC_22_X_IN        (PORT_INPUT1_MODE)
#define    PORT85_SAI0_SAI0_D0_IN        (PORT_INPUT2_MODE)
#define    PORT85_GLITCH_FILTER3_INP        (PORT_INPUT3_MODE)
#define    PORT85_EMIOS0_E0UC_22_X_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT85_SAI0_SAI0_D0_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT86_GPIO        (PORT_GPIO_MODE)
#define    PORT86_EMIOS0_E0UC_23_X_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT86_DSPI_1_dCS1        (PORT_ALT2_FUNC_MODE)
#define    PORT86_SAI1_SAI1_SYNC_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT86_EMIOS0_E0UC_30_Y_OUT        (PORT_ALT5_FUNC_MODE)
#define    PORT86_ADC_0_ADC0_S_14        (PORT_ANALOG_INPUT_MODE)
#define    PORT86_CMP2_CMP2_22        (PORT_ANALOG_INPUT_MODE)
#define    PORT86_EMIOS0_E0UC_23_X_IN        (PORT_INPUT1_MODE)
#define    PORT86_SAI1_SAI1_SYNC_IN        (PORT_INPUT2_MODE)
#define    PORT86_EMIOS0_E0UC_30_Y_IN        (PORT_INPUT3_MODE)
#define    PORT86_EMIOS0_E0UC_23_X_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT86_SAI1_SAI1_SYNC_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT86_EMIOS0_E0UC_30_Y_IN_OUT        (PORT_INOUT5_MODE)
#define    PORT87_GPIO        (PORT_GPIO_MODE)
#define    PORT87_SPI_0_SCLK_0_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT87_DSPI_1_dCS2        (PORT_ALT2_FUNC_MODE)
#define    PORT87_ADC_0_ADC0_S_15        (PORT_ANALOG_INPUT_MODE)
#define    PORT87_CMP2_CMP2_23        (PORT_ANALOG_INPUT_MODE)
#define    PORT87_SAI1_SAI1_MCLK_OUT        (PORT_ALT6_FUNC_MODE)
#define    PORT87_SPI_0_SCLK_0_IN        (PORT_INPUT1_MODE)
#define    PORT87_SAI1_SAI1_MCLK_IN        (PORT_INPUT2_MODE)
#define    PORT87_SPI_0_SCLK_0_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT87_SAI1_SAI1_MCLK_IN_OUT        (PORT_INOUT6_MODE)
#define    PORT88_GPIO        (PORT_GPIO_MODE)
#define    PORT88_FlexCAN_3_TX        (PORT_ALT1_FUNC_MODE)
#define    PORT88_DSPI_0_dCS4        (PORT_ALT2_FUNC_MODE)
#define    PORT88_FlexCAN_2_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT88_EMIOS0_E0UC_15_H_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT88_CMP0_CMP0_5        (PORT_ANALOG_INPUT_MODE)
#define    PORT88_EMIOS0_E0UC_15_H_IN        (PORT_INPUT1_MODE)
#define    PORT88_EMIOS0_E0UC_15_H_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT89_GPIO        (PORT_GPIO_MODE)
#define    PORT89_EMIOS1_E1UC_1_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT89_DSPI_0_dCS5        (PORT_ALT2_FUNC_MODE)
#define    PORT89_EMIOS0_E0UC_14_H_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT89_WKPU_WKPU_22        (PORT_ONLY_INPUT_MODE)
#define    PORT89_CMP0_CMP0_4        (PORT_ANALOG_INPUT_MODE)
#define    PORT89_EMIOS1_E1UC_1_H_IN        (PORT_INPUT1_MODE)
#define    PORT89_FlexCAN_2_RX        (PORT_INPUT2_MODE)
#define    PORT89_FlexCAN_3_RX        (PORT_INPUT3_MODE)
#define    PORT89_EMIOS0_E0UC_14_H_IN        (PORT_INPUT4_MODE)
#define    PORT89_EMIOS1_E1UC_1_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT89_EMIOS0_E0UC_14_H_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT90_GPIO        (PORT_GPIO_MODE)
#define    PORT90_DSPI_0_dCS1        (PORT_ALT1_FUNC_MODE)
#define    PORT90_LIN_4_LIN4TX        (PORT_ALT2_FUNC_MODE)
#define    PORT90_EMIOS1_E1UC_2_H_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT90_FCCU_EOUT0_OUT        (PORT_ALT5_FUNC_MODE)
#define    PORT90_FCCU_EOUT0_IN        (PORT_ONLY_INPUT_MODE)
#define    PORT90_FCCU_EOUT0_IN_OUT        (PORT_INOUT5_MODE)
#define    PORT90_EMIOS0_E0UC_19_Y_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT90_CMP1_CMP1_8        (PORT_ANALOG_INPUT_MODE)
#define    PORT90_EMIOS1_E1UC_2_H_IN        (PORT_INPUT1_MODE)
#define    PORT90_EMIOS0_E0UC_19_Y_IN        (PORT_INPUT2_MODE)
#define    PORT90_EMIOS1_E1UC_2_H_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT90_EMIOS0_E0UC_19_Y_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT91_GPIO        (PORT_GPIO_MODE)
#define    PORT91_DSPI_0_dCS2        (PORT_ALT1_FUNC_MODE)
#define    PORT91_EMIOS1_E1UC_3_H_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT91_EMIOS0_E0UC_20_Y_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT91_WKPU_WKPU_15        (PORT_ONLY_INPUT_MODE)
#define    PORT91_CMP1_CMP1_9        (PORT_ANALOG_INPUT_MODE)
#define    PORT91_EMIOS1_E1UC_3_H_IN        (PORT_INPUT1_MODE)
#define    PORT91_LIN_4_LIN4RX        (PORT_INPUT2_MODE)
#define    PORT91_EMIOS0_E0UC_20_Y_IN        (PORT_INPUT3_MODE)
#define    PORT91_EMIOS1_E1UC_3_H_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT91_EMIOS0_E0UC_20_Y_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT92_GPIO        (PORT_GPIO_MODE)
#define    PORT92_EMIOS1_E1UC_25_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT92_LIN_5_LIN5TX        (PORT_ALT2_FUNC_MODE)
#define    PORT92_FCCU_EOUT1_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT92_FCCU_EOUT1_IN        (PORT_ONLY_INPUT_MODE)
#define    PORT92_FCCU_EOUT1_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT92_EMIOS0_E0UC_16_X_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT92_CMP0_CMP0_6        (PORT_ANALOG_INPUT_MODE)
#define    PORT92_EMIOS1_E1UC_25_Y_IN        (PORT_INPUT1_MODE)
#define    PORT92_EMIOS0_E0UC_16_X_IN        (PORT_INPUT2_MODE)
#define    PORT92_EMIOS1_E1UC_25_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT92_EMIOS0_E0UC_16_X_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT93_GPIO        (PORT_GPIO_MODE)
#define    PORT93_EMIOS1_E1UC_26_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT93_EMIOS0_E0UC_22_X_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT93_WKPU_WKPU_16        (PORT_ONLY_INPUT_MODE)
#define    PORT93_CMP1_CMP1_11        (PORT_ANALOG_INPUT_MODE)
#define    PORT93_EMIOS1_E1UC_26_Y_IN        (PORT_INPUT1_MODE)
#define    PORT93_LIN_5_LIN5RX        (PORT_INPUT2_MODE)
#define    PORT93_EMIOS0_E0UC_22_X_IN        (PORT_INPUT3_MODE)
#define    PORT93_EMIOS1_E1UC_26_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT93_EMIOS0_E0UC_22_X_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT94_GPIO        (PORT_GPIO_MODE)
#define    PORT94_FlexCAN_4_TX        (PORT_ALT1_FUNC_MODE)
#define    PORT94_EMIOS1_E1UC_27_Y_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT94_FlexCAN_1_TX        (PORT_ALT3_FUNC_MODE)
/**
* @violates @ref PORT_CFG_H_REF_1 MISRA 2004 Rule 1.4, The compiler/linker shall be checked to
*  ensure that 31 character significance and case sensitivity are supported for external ids
*/
#define    PORT94_ENET0_MII_RMII_0_MDIO_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT94_ADC_1_ADC1_X_2        (PORT_ANALOG_INPUT_MODE)
#define    PORT94_EMIOS1_E1UC_27_Y_IN        (PORT_INPUT1_MODE)
#define    PORT94_ENET0_MII_RMII_0_MDIO_IN        (PORT_INPUT2_MODE)
#define    PORT94_EMIOS1_E1UC_27_Y_IN_OUT        (PORT_INOUT2_MODE)
/**
* @violates @ref PORT_CFG_H_REF_1 MISRA 2004 Rule 1.4, The compiler/linker shall be checked to
*  ensure that 31 character significance and case sensitivity are supported for external ids
*/
#define    PORT94_ENET0_MII_RMII_0_MDIO_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT95_GPIO        (PORT_GPIO_MODE)
#define    PORT95_EMIOS1_E1UC_4_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT95_ADC_1_ADC1_X_1        (PORT_ANALOG_INPUT_MODE)
#define    PORT95_EMIOS1_E1UC_4_H_IN        (PORT_INPUT1_MODE)
#define    PORT95_SIUL2_EIRQ13        (PORT_INPUT2_MODE)
#define    PORT95_FlexCAN_1_RX        (PORT_INPUT3_MODE)
#define    PORT95_FlexCAN_4_RX        (PORT_INPUT4_MODE)
#define    PORT95_ENET0_MII_RMII_0_RX_DV        (PORT_INPUT5_MODE)
#define    PORT95_EMIOS1_E1UC_4_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT96_GPIO        (PORT_GPIO_MODE)
#define    PORT96_FlexCAN_5_TX        (PORT_ALT1_FUNC_MODE)
#define    PORT96_EMIOS1_E1UC_23_X_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT96_ENET0_MII_RMII_0_MDC        (PORT_ALT3_FUNC_MODE)
#define    PORT96_ADC_1_ADC1_X_0        (PORT_ANALOG_INPUT_MODE)
#define    PORT96_EMIOS1_E1UC_23_X_IN        (PORT_INPUT1_MODE)
#define    PORT96_EMIOS1_E1UC_23_X_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT97_GPIO        (PORT_GPIO_MODE)
#define    PORT97_EMIOS1_E1UC_24_X_OUT        (PORT_ALT1_FUNC_MODE)
/**
* @violates @ref PORT_CFG_H_REF_1 MISRA 2004 Rule 1.4, The compiler/linker shall be checked to
*  ensure that 31 character significance and case sensitivity are supported for external ids
*/
#define    PORT97_ENET0_MII_RMII_0_TX_CLK_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT97_ADC_1_ADC1_S_7        (PORT_ANALOG_INPUT_MODE)
#define    PORT97_EMIOS1_E1UC_24_X_IN        (PORT_INPUT1_MODE)
#define    PORT97_SIUL2_EIRQ14        (PORT_INPUT2_MODE)
#define    PORT97_FlexCAN_5_RX        (PORT_INPUT3_MODE)
/**
* @violates @ref PORT_CFG_H_REF_1 MISRA 2004 Rule 1.4, The compiler/linker shall be checked to
*  ensure that 31 character significance and case sensitivity are supported for external ids
*/
#define    PORT97_ENET0_MII_RMII_0_TX_CLK_IN        (PORT_INPUT4_MODE)
#define    PORT97_EMIOS1_E1UC_24_X_IN_OUT        (PORT_INOUT1_MODE)
/**
* @violates @ref PORT_CFG_H_REF_1 MISRA 2004 Rule 1.4, The compiler/linker shall be checked to
*  ensure that 31 character significance and case sensitivity are supported for external ids
*/
#define    PORT97_ENET0_MII_RMII_0_TX_CLK_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT98_GPIO        (PORT_GPIO_MODE)
#define    PORT98_EMIOS1_E1UC_11_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT98_DSPI_3_dSOUT        (PORT_ALT2_FUNC_MODE)
#define    PORT98_FlexCAN_7_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT98_LIN_11_LIN11TX        (PORT_ALT4_FUNC_MODE)
#define    PORT98_EMIOS1_E1UC_11_H_IN        (PORT_INPUT1_MODE)
#define    PORT98_EMIOS1_E1UC_11_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT99_GPIO        (PORT_GPIO_MODE)
#define    PORT99_EMIOS1_E1UC_12_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT99_DSPI_3_dCS0        (PORT_ALT2_FUNC_MODE)
#define    PORT99_WKPU_WKPU_17        (PORT_ONLY_INPUT_MODE)
#define    PORT99_EMIOS1_E1UC_12_H_IN        (PORT_INPUT1_MODE)
#define    PORT99_FlexCAN_7_RX        (PORT_INPUT2_MODE)
#define    PORT99_DSPI_3_dSS        (PORT_INPUT3_MODE)
#define    PORT99_EMIOS1_E1UC_12_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT100_GPIO        (PORT_GPIO_MODE)
#define    PORT100_EMIOS1_E1UC_13_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT100_DSPI_3_dSCLK_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT100_LIN_10_LIN10TX        (PORT_ALT3_FUNC_MODE)
#define    PORT100_EMIOS1_E1UC_13_H_IN        (PORT_INPUT1_MODE)
#define    PORT100_DSPI_3_dSCLK_IN        (PORT_INPUT2_MODE)
#define    PORT100_EMIOS1_E1UC_13_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT100_DSPI_3_dSCLK_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT101_GPIO        (PORT_GPIO_MODE)
#define    PORT101_EMIOS1_E1UC_14_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT101_EMIOS0_E0UC_2_G_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT101_WKPU_WKPU_18        (PORT_ONLY_INPUT_MODE)
#define    PORT101_EMIOS1_E1UC_14_H_IN        (PORT_INPUT1_MODE)
#define    PORT101_LIN_10_LIN10RX        (PORT_INPUT2_MODE)
#define    PORT101_DSPI_3_dSIN        (PORT_INPUT3_MODE)
#define    PORT101_EMIOS0_E0UC_2_G_IN        (PORT_INPUT4_MODE)
#define    PORT101_EMIOS1_E1UC_14_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT101_EMIOS0_E0UC_2_G_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT102_GPIO        (PORT_GPIO_MODE)
#define    PORT102_EMIOS1_E1UC_15_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT102_LIN_6_LIN6TX        (PORT_ALT2_FUNC_MODE)
#define    PORT102_CGM_CLKOUT1        (PORT_ALT3_FUNC_MODE)
#define    PORT102_EMIOS0_E0UC_3_G_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT102_CMP0_CMP0_1        (PORT_ANALOG_INPUT_MODE)
#define    PORT102_PMCDIG_EXTREGC        (PORT_ONLY_OUTPUT_MODE)
#define    PORT102_EMIOS1_E1UC_15_H_IN        (PORT_INPUT1_MODE)
#define    PORT102_EMIOS0_E0UC_3_G_IN        (PORT_INPUT2_MODE)
#define    PORT102_EMIOS1_E1UC_15_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT102_EMIOS0_E0UC_3_G_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT103_GPIO        (PORT_GPIO_MODE)
#define    PORT103_EMIOS1_E1UC_16_X_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT103_EMIOS1_E1UC_30_Y_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT103_CGM_CLKOUT0        (PORT_ALT3_FUNC_MODE)
#define    PORT103_WKPU_WKPU_20        (PORT_ONLY_INPUT_MODE)
#define    PORT103_CMP0_CMP0_0        (PORT_ANALOG_INPUT_MODE)
#define    PORT103_EMIOS1_E1UC_16_X_IN        (PORT_INPUT1_MODE)
#define    PORT103_EMIOS1_E1UC_30_Y_IN        (PORT_INPUT2_MODE)
#define    PORT103_LIN_6_LIN6RX        (PORT_INPUT3_MODE)
#define    PORT103_GLITCH_FILTER3_INP        (PORT_INPUT4_MODE)
#define    PORT103_EMIOS1_E1UC_16_X_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT103_EMIOS1_E1UC_30_Y_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT104_GPIO        (PORT_GPIO_MODE)
#define    PORT104_EMIOS1_E1UC_17_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT104_LIN_7_LIN7TX        (PORT_ALT2_FUNC_MODE)
#define    PORT104_DSPI_2_dCS0        (PORT_ALT3_FUNC_MODE)
#define    PORT104_FlexCAN_7_TX        (PORT_ALT4_FUNC_MODE)
#define    PORT104_EMIOS1_E1UC_17_Y_IN        (PORT_INPUT1_MODE)
#define    PORT104_SIUL2_EIRQ15        (PORT_INPUT2_MODE)
#define    PORT104_DSPI_2_dSS        (PORT_INPUT3_MODE)
#define    PORT104_EMIOS1_E1UC_17_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT105_GPIO        (PORT_GPIO_MODE)
#define    PORT105_EMIOS1_E1UC_18_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT105_DSPI_2_dSCLK_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT105_EMIOS0_E0UC_0_X_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT105_WKPU_WKPU_21        (PORT_ONLY_INPUT_MODE)
#define    PORT105_EMIOS1_E1UC_18_Y_IN        (PORT_INPUT1_MODE)
#define    PORT105_FlexCAN_7_RX        (PORT_INPUT2_MODE)
#define    PORT105_LIN_7_LIN7RX        (PORT_INPUT3_MODE)
#define    PORT105_DSPI_2_dSCLK_IN        (PORT_INPUT4_MODE)
#define    PORT105_EMIOS0_E0UC_0_X_IN        (PORT_INPUT5_MODE)
#define    PORT105_EMIOS1_E1UC_18_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT105_DSPI_2_dSCLK_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT105_EMIOS0_E0UC_0_X_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT106_GPIO        (PORT_GPIO_MODE)
#define    PORT106_EMIOS0_E0UC_24_X_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT106_EMIOS1_E1UC_31_Y_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT106_EMIOS0_E0UC_24_X_IN        (PORT_INPUT1_MODE)
#define    PORT106_EMIOS1_E1UC_31_Y_IN        (PORT_INPUT2_MODE)
#define    PORT106_SPI_0_SIN_0        (PORT_INPUT3_MODE)
#define    PORT106_GLITCH_FILTER3_INP        (PORT_INPUT4_MODE)
#define    PORT106_EMIOS0_E0UC_24_X_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT106_EMIOS1_E1UC_31_Y_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT107_GPIO        (PORT_GPIO_MODE)
#define    PORT107_EMIOS0_E0UC_25_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT107_SPI_0_CS0_0        (PORT_ALT2_FUNC_MODE)
#define    PORT107_SPI_2_CS0_2        (PORT_ALT3_FUNC_MODE)
#define    PORT107_EMIOS0_E0UC_25_Y_IN        (PORT_INPUT1_MODE)
#define    PORT107_SPI_0_SS_0        (PORT_INPUT2_MODE)
#define    PORT107_SPI_2_SS_2        (PORT_INPUT3_MODE)
#define    PORT107_EMIOS0_E0UC_25_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT108_GPIO        (PORT_GPIO_MODE)
#define    PORT108_EMIOS0_E0UC_26_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT108_SPI_0_SOUT_0        (PORT_ALT2_FUNC_MODE)
#define    PORT108_ENET0_MII_0_TXD_2        (PORT_ALT4_FUNC_MODE)
#define    PORT108_ADC_1_ADC1_S_2        (PORT_ANALOG_INPUT_MODE)
#define    PORT108_EMIOS0_E0UC_26_Y_IN        (PORT_INPUT1_MODE)
#define    PORT108_EMIOS0_E0UC_26_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT109_GPIO        (PORT_GPIO_MODE)
#define    PORT109_EMIOS0_E0UC_27_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT109_SPI_0_SCLK_0_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT109_ENET0_MII_0_TXD_3        (PORT_ALT4_FUNC_MODE)
#define    PORT109_ADC_1_ADC1_S_1        (PORT_ANALOG_INPUT_MODE)
#define    PORT109_EMIOS0_E0UC_27_Y_IN        (PORT_INPUT1_MODE)
#define    PORT109_SPI_0_SCLK_0_IN        (PORT_INPUT2_MODE)
#define    PORT109_EMIOS0_E0UC_27_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT109_SPI_0_SCLK_0_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT110_GPIO        (PORT_GPIO_MODE)
#define    PORT110_EMIOS1_E1UC_0_X_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT110_LIN_8_LIN8TX        (PORT_ALT2_FUNC_MODE)
#define    PORT110_EMIOS1_E1UC_0_X_IN        (PORT_INPUT1_MODE)
#define    PORT110_SPI_2_SIN_2        (PORT_INPUT2_MODE)
#define    PORT110_EMIOS1_E1UC_0_X_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT111_GPIO        (PORT_GPIO_MODE)
#define    PORT111_EMIOS1_E1UC_1_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT111_SPI_2_SOUT_2        (PORT_ALT2_FUNC_MODE)
#define    PORT111_EMIOS1_E1UC_1_H_IN        (PORT_INPUT1_MODE)
#define    PORT111_LIN_8_LIN8RX        (PORT_INPUT2_MODE)
#define    PORT111_EMIOS1_E1UC_1_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT112_GPIO        (PORT_GPIO_MODE)
#define    PORT112_EMIOS1_E1UC_2_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT112_ENET0_MII_RMII_0_TXD_1        (PORT_ALT3_FUNC_MODE)
#define    PORT112_ADC_1_ADC1_S_3        (PORT_ANALOG_INPUT_MODE)
#define    PORT112_EMIOS1_E1UC_2_H_IN        (PORT_INPUT1_MODE)
#define    PORT112_DSPI_1_dSIN        (PORT_INPUT2_MODE)
#define    PORT112_EMIOS1_E1UC_2_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT113_GPIO        (PORT_GPIO_MODE)
#define    PORT113_EMIOS1_E1UC_3_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT113_DSPI_1_dSOUT        (PORT_ALT2_FUNC_MODE)
#define    PORT113_ENET0_MII_RMII_0_TXD_0        (PORT_ALT4_FUNC_MODE)
#define    PORT113_ADC_1_ADC1_S_4        (PORT_ANALOG_INPUT_MODE)
#define    PORT113_EMIOS1_E1UC_3_H_IN        (PORT_INPUT1_MODE)
#define    PORT113_EMIOS1_E1UC_3_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT114_GPIO        (PORT_GPIO_MODE)
#define    PORT114_EMIOS1_E1UC_4_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT114_DSPI_1_dSCLK_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT114_ENET0_MII_RMII_0_TX_EN        (PORT_ALT4_FUNC_MODE)
#define    PORT114_ADC_1_ADC1_S_5        (PORT_ANALOG_INPUT_MODE)
#define    PORT114_EMIOS1_E1UC_4_H_IN        (PORT_INPUT1_MODE)
#define    PORT114_DSPI_1_dSCLK_IN        (PORT_INPUT2_MODE)
#define    PORT114_EMIOS1_E1UC_4_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT114_DSPI_1_dSCLK_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT115_GPIO        (PORT_GPIO_MODE)
#define    PORT115_EMIOS1_E1UC_5_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT115_DSPI_1_dCS0        (PORT_ALT2_FUNC_MODE)
#define    PORT115_ENET0_MII_0_TX_ER        (PORT_ALT3_FUNC_MODE)
#define    PORT115_ADC_1_ADC1_S_6        (PORT_ANALOG_INPUT_MODE)
#define    PORT115_EMIOS1_E1UC_5_H_IN        (PORT_INPUT1_MODE)
#define    PORT115_DSPI_1_dSS        (PORT_INPUT2_MODE)
#define    PORT115_EMIOS1_E1UC_5_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT116_GPIO        (PORT_GPIO_MODE)
#define    PORT116_EMIOS1_E1UC_6_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT116_SPI_3_SOUT_3        (PORT_ALT2_FUNC_MODE)
#define    PORT116_IIC_3_SCL3_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT116_EMIOS1_E1UC_6_H_IN        (PORT_INPUT1_MODE)
#define    PORT116_IIC_3_SCL3_IN        (PORT_INPUT2_MODE)
#define    PORT116_EMIOS1_E1UC_6_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT116_IIC_3_SCL3_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT117_GPIO        (PORT_GPIO_MODE)
#define    PORT117_EMIOS1_E1UC_7_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT117_IIC_3_SDA3_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT117_EMIOS1_E1UC_7_H_IN        (PORT_INPUT1_MODE)
#define    PORT117_IIC_3_SDA3_IN        (PORT_INPUT2_MODE)
#define    PORT117_SPI_3_SIN_3        (PORT_INPUT3_MODE)
#define    PORT117_EMIOS1_E1UC_7_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT117_IIC_3_SDA3_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT118_GPIO        (PORT_GPIO_MODE)
#define    PORT118_EMIOS1_E1UC_8_X_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT118_SPI_3_SCLK_3_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT118_ADC_0_ADC0_MA_2        (PORT_ALT3_FUNC_MODE)
#define    PORT118_ADC_1_ADC1_MA_2        (PORT_ALT4_FUNC_MODE)
#define    PORT118_EMIOS1_E1UC_8_X_IN        (PORT_INPUT1_MODE)
#define    PORT118_SPI_3_SCLK_3_IN        (PORT_INPUT2_MODE)
#define    PORT118_EMIOS1_E1UC_8_X_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT118_SPI_3_SCLK_3_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT119_GPIO        (PORT_GPIO_MODE)
#define    PORT119_EMIOS1_E1UC_9_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT119_DSPI_2_dCS3        (PORT_ALT2_FUNC_MODE)
#define    PORT119_ADC_0_ADC0_MA_1        (PORT_ALT3_FUNC_MODE)
#define    PORT119_SPI_3_CS0_3        (PORT_ALT4_FUNC_MODE)
#define    PORT119_ADC_1_ADC1_MA_1        (PORT_ALT5_FUNC_MODE)
#define    PORT119_EMIOS1_E1UC_9_H_IN        (PORT_INPUT1_MODE)
#define    PORT119_SPI_3_SS_3        (PORT_INPUT2_MODE)
#define    PORT119_EMIOS1_E1UC_9_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT120_GPIO        (PORT_GPIO_MODE)
#define    PORT120_EMIOS1_E1UC_10_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT120_DSPI_2_dCS2        (PORT_ALT2_FUNC_MODE)
#define    PORT120_ADC_0_ADC0_MA_0        (PORT_ALT3_FUNC_MODE)
#define    PORT120_ADC_1_ADC1_MA_0        (PORT_ALT4_FUNC_MODE)
#define    PORT120_EMIOS1_E1UC_10_H_IN        (PORT_INPUT1_MODE)
#define    PORT120_EMIOS1_E1UC_10_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT121_GPIO        (PORT_GPIO_MODE)
#define    PORT121_DCI_TCK        (PORT_ALT1_FUNC_MODE)
#define    PORT122_GPIO        (PORT_GPIO_MODE)
#define    PORT122_DCI_TMS_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT122_DCI_TMS_IN        (PORT_ONLY_INPUT_MODE)
#define    PORT122_DCI_TMS_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT123_GPIO        (PORT_GPIO_MODE)
#define    PORT123_DSPI_3_dSOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT123_SPI_0_CS0_0        (PORT_ALT2_FUNC_MODE)
#define    PORT123_EMIOS1_E1UC_5_H_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT123_EMIOS1_E1UC_5_H_IN        (PORT_INPUT1_MODE)
#define    PORT123_SPI_0_SS_0        (PORT_INPUT2_MODE)
#define    PORT123_EMIOS1_E1UC_5_H_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT124_GPIO        (PORT_GPIO_MODE)
#define    PORT124_DSPI_3_dSCLK_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT124_SPI_0_CS1_0        (PORT_ALT2_FUNC_MODE)
#define    PORT124_EMIOS1_E1UC_25_Y_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT124_EMIOS1_E1UC_25_Y_IN        (PORT_INPUT1_MODE)
#define    PORT124_DSPI_3_dSCLK_IN        (PORT_INPUT2_MODE)
#define    PORT124_DSPI_3_dSCLK_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT124_EMIOS1_E1UC_25_Y_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT125_GPIO        (PORT_GPIO_MODE)
#define    PORT125_SPI_0_SOUT_0        (PORT_ALT1_FUNC_MODE)
#define    PORT125_DSPI_3_dCS0        (PORT_ALT2_FUNC_MODE)
#define    PORT125_EMIOS1_E1UC_26_Y_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT125_FCCU_EOUT1_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT125_FCCU_EOUT1_IN        (PORT_ONLY_INPUT_MODE)
#define    PORT125_FCCU_EOUT1_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT125_EMIOS1_E1UC_26_Y_IN        (PORT_INPUT1_MODE)
#define    PORT125_DSPI_3_dSS        (PORT_INPUT2_MODE)
#define    PORT125_EMIOS1_E1UC_26_Y_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT126_GPIO        (PORT_GPIO_MODE)
#define    PORT126_SPI_0_SCLK_0_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT126_DSPI_3_dCS1        (PORT_ALT2_FUNC_MODE)
#define    PORT126_EMIOS1_E1UC_27_Y_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT126_EMIOS1_E1UC_27_Y_IN        (PORT_INPUT1_MODE)
#define    PORT126_SPI_0_SCLK_0_IN        (PORT_INPUT2_MODE)
#define    PORT126_FCCU_EIN_ERR        (PORT_INPUT3_MODE)
#define    PORT126_SPI_0_SCLK_0_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT126_EMIOS1_E1UC_27_Y_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT127_GPIO        (PORT_GPIO_MODE)
#define    PORT127_SPI_1_SOUT_1        (PORT_ALT1_FUNC_MODE)
#define    PORT127_EMIOS1_E1UC_17_Y_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT127_FCCU_EOUT0_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT127_FCCU_EOUT0_IN        (PORT_ONLY_INPUT_MODE)
#define    PORT127_FCCU_EOUT0_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT127_EMIOS1_E1UC_17_Y_IN        (PORT_INPUT1_MODE)
#define    PORT127_EMIOS1_E1UC_17_Y_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT128_GPIO        (PORT_GPIO_MODE)
#define    PORT128_EMIOS0_E0UC_28_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT128_LIN_8_LIN8TX        (PORT_ALT2_FUNC_MODE)
#define    PORT128_IIC_1_SDA1_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT128_EMIOS0_E0UC_28_Y_IN        (PORT_INPUT1_MODE)
#define    PORT128_IIC_1_SDA1_IN        (PORT_INPUT2_MODE)
#define    PORT128_GLITCH_FILTER0_INP        (PORT_INPUT3_MODE)
#define    PORT128_EMIOS0_E0UC_28_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT128_IIC_1_SDA1_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT129_GPIO        (PORT_GPIO_MODE)
#define    PORT129_EMIOS0_E0UC_29_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT129_IIC_1_SCL1_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT129_WKPU_WKPU_24        (PORT_ONLY_INPUT_MODE)
#define    PORT129_EMIOS0_E0UC_29_Y_IN        (PORT_INPUT1_MODE)
#define    PORT129_LIN_8_LIN8RX        (PORT_INPUT2_MODE)
#define    PORT129_IIC_1_SCL1_IN        (PORT_INPUT3_MODE)
#define    PORT129_GLITCH_FILTER0_INP        (PORT_INPUT4_MODE)
#define    PORT129_EMIOS0_E0UC_29_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT129_IIC_1_SCL1_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT130_GPIO        (PORT_GPIO_MODE)
#define    PORT130_EMIOS0_E0UC_30_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT130_LIN_9_LIN9TX        (PORT_ALT2_FUNC_MODE)
#define    PORT130_IIC_2_SDA2_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT130_EMIOS0_E0UC_30_Y_IN        (PORT_INPUT1_MODE)
#define    PORT130_IIC_2_SDA2_IN        (PORT_INPUT2_MODE)
#define    PORT130_GLITCH_FILTER1_INP        (PORT_INPUT3_MODE)
#define    PORT130_EMIOS0_E0UC_30_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT130_IIC_2_SDA2_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT131_GPIO        (PORT_GPIO_MODE)
#define    PORT131_EMIOS0_E0UC_31_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT131_IIC_2_SCL2_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT131_WKPU_WKPU_23        (PORT_ONLY_INPUT_MODE)
#define    PORT131_EMIOS0_E0UC_31_Y_IN        (PORT_INPUT1_MODE)
#define    PORT131_LIN_9_LIN9RX        (PORT_INPUT2_MODE)
#define    PORT131_IIC_2_SCL2_IN        (PORT_INPUT3_MODE)
#define    PORT131_GLITCH_FILTER1_INP        (PORT_INPUT4_MODE)
#define    PORT131_EMIOS0_E0UC_31_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT131_IIC_2_SCL2_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT132_GPIO        (PORT_GPIO_MODE)
#define    PORT132_EMIOS1_E1UC_28_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT132_SPI_0_SOUT_0        (PORT_ALT2_FUNC_MODE)
#define    PORT132_EMIOS1_E1UC_28_Y_IN        (PORT_INPUT1_MODE)
#define    PORT132_GLITCH_FILTER2_INP        (PORT_INPUT2_MODE)
#define    PORT132_EMIOS1_E1UC_28_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT133_GPIO        (PORT_GPIO_MODE)
#define    PORT133_EMIOS1_E1UC_29_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT133_SPI_0_SCLK_0_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT133_SPI_1_CS2_1        (PORT_ALT3_FUNC_MODE)
#define    PORT133_SPI_2_CS2_2        (PORT_ALT4_FUNC_MODE)
#define    PORT133_EMIOS1_E1UC_29_Y_IN        (PORT_INPUT1_MODE)
#define    PORT133_SPI_0_SCLK_0_IN        (PORT_INPUT2_MODE)
#define    PORT133_GLITCH_FILTER2_INP        (PORT_INPUT3_MODE)
#define    PORT133_EMIOS1_E1UC_29_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT133_SPI_0_SCLK_0_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT134_GPIO        (PORT_GPIO_MODE)
#define    PORT134_EMIOS1_E1UC_30_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT134_SPI_0_CS0_0        (PORT_ALT2_FUNC_MODE)
#define    PORT134_SPI_1_CS0_1        (PORT_ALT3_FUNC_MODE)
#define    PORT134_SPI_2_CS0_2        (PORT_ALT4_FUNC_MODE)
#define    PORT134_HSM_DO0        (PORT_ALT5_FUNC_MODE)
#define    PORT134_EMIOS1_E1UC_30_Y_IN        (PORT_INPUT1_MODE)
#define    PORT134_SPI_0_SS_0        (PORT_INPUT2_MODE)
#define    PORT134_SPI_1_SS_1        (PORT_INPUT3_MODE)
#define    PORT134_SPI_2_SS_2        (PORT_INPUT4_MODE)
#define    PORT134_GLITCH_FILTER3_INP        (PORT_INPUT5_MODE)
#define    PORT134_EMIOS1_E1UC_30_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT135_GPIO        (PORT_GPIO_MODE)
#define    PORT135_EMIOS1_E1UC_31_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT135_SPI_0_CS1_0        (PORT_ALT2_FUNC_MODE)
#define    PORT135_SPI_1_CS1_1        (PORT_ALT3_FUNC_MODE)
#define    PORT135_SPI_2_CS1_2        (PORT_ALT4_FUNC_MODE)
#define    PORT135_HSM_DO1        (PORT_ALT5_FUNC_MODE)
#define    PORT135_EMIOS1_E1UC_31_Y_IN        (PORT_INPUT1_MODE)
#define    PORT135_GLITCH_FILTER3_INP        (PORT_INPUT2_MODE)
#define    PORT135_EMIOS1_E1UC_31_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT136_GPIO        (PORT_GPIO_MODE)
#define    PORT136_ADC_0_ADC0_S_16        (PORT_ANALOG_INPUT_MODE)
#define    PORT137_GPIO        (PORT_GPIO_MODE)
#define    PORT137_ADC_0_ADC0_S_17        (PORT_ANALOG_INPUT_MODE)
#define    PORT138_GPIO        (PORT_GPIO_MODE)
#define    PORT138_ADC_0_ADC0_S_18        (PORT_ANALOG_INPUT_MODE)
#define    PORT139_GPIO        (PORT_GPIO_MODE)
#define    PORT139_ENET0_ENET0_TMR1_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT139_ADC_0_ADC0_S_19        (PORT_ANALOG_INPUT_MODE)
#define    PORT139_DSPI_3_dSIN        (PORT_INPUT1_MODE)
#define    PORT139_ENET0_ENET0_TMR1_IN        (PORT_INPUT2_MODE)
#define    PORT139_ENET0_ENET0_TMR1_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT140_GPIO        (PORT_GPIO_MODE)
#define    PORT140_DSPI_3_dCS0        (PORT_ALT1_FUNC_MODE)
#define    PORT140_DSPI_2_dCS0        (PORT_ALT2_FUNC_MODE)
#define    PORT140_ADC_0_ADC0_S_20        (PORT_ANALOG_INPUT_MODE)
#define    PORT140_DSPI_2_dSS        (PORT_INPUT1_MODE)
#define    PORT140_DSPI_3_dSS        (PORT_INPUT2_MODE)
#define    PORT141_GPIO        (PORT_GPIO_MODE)
#define    PORT141_DSPI_3_dCS1        (PORT_ALT1_FUNC_MODE)
#define    PORT141_DSPI_2_dCS1        (PORT_ALT2_FUNC_MODE)
#define    PORT141_ADC_0_ADC0_S_21        (PORT_ANALOG_INPUT_MODE)
#define    PORT142_GPIO        (PORT_GPIO_MODE)
#define    PORT142_SAI2_SAI2_D0_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT142_ADC_0_ADC0_S_22        (PORT_ANALOG_INPUT_MODE)
#define    PORT142_SPI_0_SIN_0        (PORT_INPUT1_MODE)
#define    PORT142_SAI2_SAI2_D0_IN        (PORT_INPUT2_MODE)
#define    PORT142_SAI2_SAI2_D0_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT143_GPIO        (PORT_GPIO_MODE)
#define    PORT143_SPI_0_CS0_0        (PORT_ALT1_FUNC_MODE)
#define    PORT143_DSPI_2_dCS2        (PORT_ALT2_FUNC_MODE)
#define    PORT143_SAI2_SAI2_MCLK_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT143_ADC_0_ADC0_S_23        (PORT_ANALOG_INPUT_MODE)
#define    PORT143_SPI_0_SS_0        (PORT_INPUT1_MODE)
#define    PORT143_SAI2_SAI2_MCLK_IN        (PORT_INPUT2_MODE)
#define    PORT143_SAI2_SAI2_MCLK_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT144_GPIO        (PORT_GPIO_MODE)
#define    PORT144_SPI_0_CS1_0        (PORT_ALT1_FUNC_MODE)
#define    PORT144_DSPI_2_dCS3        (PORT_ALT2_FUNC_MODE)
#define    PORT144_SAI2_SAI2_SYNC_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT144_ADC_0_ADC0_S_24        (PORT_ANALOG_INPUT_MODE)
#define    PORT144_SAI2_SAI2_SYNC_IN        (PORT_INPUT1_MODE)
#define    PORT144_SAI2_SAI2_SYNC_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT145_GPIO        (PORT_GPIO_MODE)
#define    PORT145_SPI_0_SOUT_0        (PORT_ALT1_FUNC_MODE)
#define    PORT145_SAI2_SAI2_BCLK_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT145_ADC_0_ADC0_S_25        (PORT_ANALOG_INPUT_MODE)
#define    PORT145_SPI_1_SIN_1        (PORT_INPUT1_MODE)
#define    PORT145_SAI2_SAI2_BCLK_IN        (PORT_INPUT2_MODE)
#define    PORT145_SAI2_SAI2_BCLK_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT146_GPIO        (PORT_GPIO_MODE)
#define    PORT146_SPI_1_CS0_1        (PORT_ALT1_FUNC_MODE)
#define    PORT146_SPI_2_CS0_2        (PORT_ALT2_FUNC_MODE)
#define    PORT146_SPI_3_CS0_3        (PORT_ALT3_FUNC_MODE)
#define    PORT146_SAI1_SAI1_D0_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT146_ADC_0_ADC0_S_26        (PORT_ANALOG_INPUT_MODE)
#define    PORT146_SPI_1_SS_1        (PORT_INPUT1_MODE)
#define    PORT146_SPI_2_SS_2        (PORT_INPUT2_MODE)
#define    PORT146_SPI_3_SS_3        (PORT_INPUT3_MODE)
#define    PORT146_SAI1_SAI1_D0_IN        (PORT_INPUT4_MODE)
#define    PORT146_SAI1_SAI1_D0_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT147_GPIO        (PORT_GPIO_MODE)
#define    PORT147_SPI_1_CS1_1        (PORT_ALT1_FUNC_MODE)
#define    PORT147_SPI_2_CS1_2        (PORT_ALT2_FUNC_MODE)
#define    PORT147_SPI_3_CS1_3        (PORT_ALT3_FUNC_MODE)
#define    PORT147_SAI1_SAI1_BCLK_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT147_ADC_0_ADC0_S_27        (PORT_ANALOG_INPUT_MODE)
#define    PORT147_SAI1_SAI1_BCLK_IN        (PORT_INPUT1_MODE)
#define    PORT147_SAI1_SAI1_BCLK_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT148_GPIO        (PORT_GPIO_MODE)
#define    PORT148_SPI_1_SCLK_1_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT148_EMIOS1_E1UC_18_Y_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT148_EMIOS1_E1UC_18_Y_IN        (PORT_INPUT1_MODE)
#define    PORT148_SPI_1_SCLK_1_IN        (PORT_INPUT2_MODE)
#define    PORT148_FCCU_EIN_ERR        (PORT_INPUT3_MODE)
#define    PORT148_SPI_1_SCLK_1_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT148_EMIOS1_E1UC_18_Y_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT149_GPIO        (PORT_GPIO_MODE)
#define    PORT149_SAI2_SAI2_D0_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT149_ADC_0_ADC0_S_28        (PORT_ANALOG_INPUT_MODE)
#define    PORT149_SAI2_SAI2_D0_IN        (PORT_INPUT1_MODE)
#define    PORT149_SAI2_SAI2_D0_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT150_GPIO        (PORT_GPIO_MODE)
#define    PORT150_SAI2_SAI2_BCLK_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT150_ADC_0_ADC0_S_29        (PORT_ANALOG_INPUT_MODE)
#define    PORT150_SAI2_SAI2_BCLK_IN        (PORT_INPUT1_MODE)
#define    PORT150_SAI2_SAI2_BCLK_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT151_GPIO        (PORT_GPIO_MODE)
#define    PORT151_ADC_0_ADC0_S_30        (PORT_ANALOG_INPUT_MODE)
#define    PORT151_SAI2_SAI2_MCLK_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT151_SAI2_SAI2_MCLK_IN        (PORT_INPUT1_MODE)
#define    PORT151_SAI2_SAI2_MCLK_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT152_GPIO        (PORT_GPIO_MODE)
#define    PORT152_SAI2_SAI2_SYNC_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT152_ADC_0_ADC0_S_31        (PORT_ANALOG_INPUT_MODE)
#define    PORT152_SAI2_SAI2_SYNC_IN        (PORT_INPUT1_MODE)
#define    PORT152_SAI2_SAI2_SYNC_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT153_GPIO        (PORT_GPIO_MODE)
#define    PORT153_FlexCAN_4_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT153_EMIOS1_E1UC_17_Y_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT153_EMIOS1_E1UC_17_Y_IN        (PORT_INPUT1_MODE)
#define    PORT153_EMIOS1_E1UC_17_Y_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT154_GPIO        (PORT_GPIO_MODE)
#define    PORT154_EMIOS1_E1UC_16_X_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT154_EMIOS1_E1UC_16_X_IN        (PORT_INPUT1_MODE)
#define    PORT154_FlexCAN_4_RX        (PORT_INPUT2_MODE)
#define    PORT154_EMIOS1_E1UC_16_X_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT155_GPIO        (PORT_GPIO_MODE)
#define    PORT155_FlexCAN_2_TX        (PORT_ALT1_FUNC_MODE)
#define    PORT155_EMIOS1_E1UC_11_H_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT155_EMIOS1_E1UC_11_H_IN        (PORT_INPUT1_MODE)
#define    PORT155_EMIOS1_E1UC_11_H_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT156_GPIO        (PORT_GPIO_MODE)
#define    PORT156_EMIOS1_E1UC_10_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT156_EMIOS1_E1UC_10_H_IN        (PORT_INPUT1_MODE)
#define    PORT156_FlexCAN_2_RX        (PORT_INPUT2_MODE)
#define    PORT156_EMIOS1_E1UC_10_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT157_GPIO        (PORT_GPIO_MODE)
#define    PORT157_SPI_3_CS1_3        (PORT_ALT1_FUNC_MODE)
#define    PORT157_EMIOS1_E1UC_15_H_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT157_WKPU_WKPU_31        (PORT_ONLY_INPUT_MODE)
#define    PORT157_EMIOS1_E1UC_15_H_IN        (PORT_INPUT1_MODE)
#define    PORT157_FlexCAN_1_RX        (PORT_INPUT2_MODE)
#define    PORT157_FlexCAN_4_RX        (PORT_INPUT3_MODE)
#define    PORT157_FlexCAN_6_RX        (PORT_INPUT4_MODE)
#define    PORT157_EMIOS1_E1UC_15_H_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT158_GPIO        (PORT_GPIO_MODE)
#define    PORT158_FlexCAN_1_TX        (PORT_ALT1_FUNC_MODE)
#define    PORT158_FlexCAN_4_TX        (PORT_ALT2_FUNC_MODE)
#define    PORT158_SPI_3_CS2_3        (PORT_ALT3_FUNC_MODE)
#define    PORT158_FlexCAN_6_TX        (PORT_ALT4_FUNC_MODE)
#define    PORT158_EMIOS1_E1UC_14_H_OUT        (PORT_ALT6_FUNC_MODE)
#define    PORT158_EMIOS1_E1UC_14_H_IN        (PORT_INPUT1_MODE)
#define    PORT158_EMIOS1_E1UC_14_H_IN_OUT        (PORT_INOUT6_MODE)
#define    PORT159_GPIO        (PORT_GPIO_MODE)
#define    PORT159_SPI_2_CS1_2        (PORT_ALT1_FUNC_MODE)
#define    PORT159_EMIOS1_E1UC_13_H_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT159_EMIOS1_E1UC_13_H_IN        (PORT_INPUT1_MODE)
#define    PORT159_FlexCAN_1_RX        (PORT_INPUT2_MODE)
#define    PORT159_FlexCAN_3_RX        (PORT_INPUT3_MODE)
#define    PORT159_EMIOS1_E1UC_13_H_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT160_GPIO        (PORT_GPIO_MODE)
#define    PORT160_FlexCAN_1_TX        (PORT_ALT1_FUNC_MODE)
#define    PORT160_SPI_2_CS2_2        (PORT_ALT2_FUNC_MODE)
#define    PORT160_FlexCAN_3_TX        (PORT_ALT3_FUNC_MODE)
#define    PORT160_EMIOS1_E1UC_12_H_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT160_EMIOS1_E1UC_12_H_IN        (PORT_INPUT1_MODE)
#define    PORT160_EMIOS1_E1UC_12_H_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT161_GPIO        (PORT_GPIO_MODE)
#define    PORT161_SPI_2_CS3_2        (PORT_ALT1_FUNC_MODE)
#define    PORT161_EMIOS1_E1UC_1_H_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT161_EMIOS0_E0UC_6_G_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT161_EMIOS1_E1UC_1_H_IN        (PORT_INPUT1_MODE)
#define    PORT161_FlexCAN_4_RX        (PORT_INPUT2_MODE)
#define    PORT161_EMIOS0_E0UC_6_G_IN        (PORT_INPUT3_MODE)
#define    PORT161_EMIOS1_E1UC_1_H_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT161_EMIOS0_E0UC_6_G_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT162_GPIO        (PORT_GPIO_MODE)
#define    PORT162_FlexCAN_4_TX        (PORT_ALT1_FUNC_MODE)
#define    PORT162_EMIOS1_E1UC_2_H_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT162_EMIOS1_E1UC_2_H_IN        (PORT_INPUT1_MODE)
#define    PORT162_EMIOS1_E1UC_2_H_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT163_GPIO        (PORT_GPIO_MODE)
#define    PORT163_EMIOS1_E1UC_0_X_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT163_EMIOS1_E1UC_3_H_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT163_EMIOS1_E1UC_0_X_IN        (PORT_INPUT1_MODE)
#define    PORT163_EMIOS1_E1UC_3_H_IN        (PORT_INPUT2_MODE)
#define    PORT163_SIUL2_EIRQ31        (PORT_INPUT3_MODE)
#define    PORT163_FlexCAN_5_RX        (PORT_INPUT4_MODE)
#define    PORT163_LIN_8_LIN8RX        (PORT_INPUT5_MODE)
#define    PORT163_EMIOS1_E1UC_0_X_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT163_EMIOS1_E1UC_3_H_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT164_GPIO        (PORT_GPIO_MODE)
#define    PORT164_FlexCAN_5_TX        (PORT_ALT1_FUNC_MODE)
#define    PORT164_LIN_8_LIN8TX        (PORT_ALT2_FUNC_MODE)
#define    PORT164_EMIOS1_E1UC_1_H_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT164_EMIOS0_E0UC_9_H_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT164_EMIOS1_E1UC_1_H_IN        (PORT_INPUT1_MODE)
#define    PORT164_EMIOS0_E0UC_9_H_IN        (PORT_INPUT2_MODE)
#define    PORT164_EMIOS1_E1UC_1_H_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT164_EMIOS0_E0UC_9_H_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT165_GPIO        (PORT_GPIO_MODE)
#define    PORT165_EMIOS1_E1UC_4_H_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT165_EMIOS0_E0UC_10_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT165_EMIOS1_E1UC_4_H_IN        (PORT_INPUT1_MODE)
#define    PORT165_FlexCAN_2_RX        (PORT_INPUT2_MODE)
#define    PORT165_LIN_2_LIN2RX        (PORT_INPUT3_MODE)
#define    PORT165_EMIOS0_E0UC_10_H_IN        (PORT_INPUT4_MODE)
#define    PORT165_EMIOS1_E1UC_4_H_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT165_EMIOS0_E0UC_10_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT166_GPIO        (PORT_GPIO_MODE)
#define    PORT166_FlexCAN_2_TX        (PORT_ALT1_FUNC_MODE)
#define    PORT166_LIN_2_LIN2TX        (PORT_ALT2_FUNC_MODE)
#define    PORT166_EMIOS1_E1UC_5_H_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT166_EMIOS0_E0UC_11_H_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT166_EMIOS1_E1UC_5_H_IN        (PORT_INPUT1_MODE)
#define    PORT166_EMIOS0_E0UC_11_H_IN        (PORT_INPUT2_MODE)
#define    PORT166_EMIOS1_E1UC_5_H_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT166_EMIOS0_E0UC_11_H_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT167_GPIO        (PORT_GPIO_MODE)
#define    PORT167_EMIOS1_E1UC_6_H_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT167_EMIOS0_E0UC_12_H_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT167_EMIOS1_E1UC_6_H_IN        (PORT_INPUT1_MODE)
#define    PORT167_FlexCAN_3_RX        (PORT_INPUT2_MODE)
#define    PORT167_LIN_3_LIN3RX        (PORT_INPUT3_MODE)
#define    PORT167_EMIOS0_E0UC_12_H_IN        (PORT_INPUT4_MODE)
#define    PORT167_EMIOS1_E1UC_6_H_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT167_EMIOS0_E0UC_12_H_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT168_GPIO        (PORT_GPIO_MODE)
#define    PORT168_FlexCAN_3_TX        (PORT_ALT1_FUNC_MODE)
#define    PORT168_LIN_3_LIN3TX        (PORT_ALT2_FUNC_MODE)
#define    PORT168_EMIOS1_E1UC_7_H_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT168_EMIOS0_E0UC_13_H_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT168_EMIOS1_E1UC_7_H_IN        (PORT_INPUT1_MODE)
#define    PORT168_EMIOS0_E0UC_13_H_IN        (PORT_INPUT2_MODE)
#define    PORT168_EMIOS1_E1UC_7_H_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT168_EMIOS0_E0UC_13_H_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT169_GPIO        (PORT_GPIO_MODE)
#define    PORT169_EMIOS1_E1UC_29_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT169_EMIOS1_E1UC_29_Y_IN        (PORT_INPUT1_MODE)
#define    PORT169_LIN_15_LIN15RX        (PORT_INPUT2_MODE)
#define    PORT169_SPI_0_SIN_0        (PORT_INPUT3_MODE)
#define    PORT169_GLITCH_FILTER2_INP        (PORT_INPUT4_MODE)
#define    PORT169_EMIOS1_E1UC_29_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT170_GPIO        (PORT_GPIO_MODE)
#define    PORT170_SPI_0_SOUT_0        (PORT_ALT1_FUNC_MODE)
#define    PORT170_EMIOS1_E1UC_30_Y_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT170_LIN_15_LIN15TX        (PORT_ALT3_FUNC_MODE)
#define    PORT170_EMIOS1_E1UC_30_Y_IN        (PORT_INPUT1_MODE)
#define    PORT170_GLITCH_FILTER3_INP        (PORT_INPUT2_MODE)
#define    PORT170_EMIOS1_E1UC_30_Y_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT171_GPIO        (PORT_GPIO_MODE)
#define    PORT171_SPI_0_SCLK_0_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT171_EMIOS1_E1UC_31_Y_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT171_LIN_14_LIN14TX        (PORT_ALT3_FUNC_MODE)
#define    PORT171_EMIOS1_E1UC_31_Y_IN        (PORT_INPUT1_MODE)
#define    PORT171_SPI_0_SCLK_0_IN        (PORT_INPUT2_MODE)
#define    PORT171_GLITCH_FILTER3_INP        (PORT_INPUT3_MODE)
#define    PORT171_SPI_0_SCLK_0_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT171_EMIOS1_E1UC_31_Y_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT172_GPIO        (PORT_GPIO_MODE)
#define    PORT172_SPI_0_CS0_0        (PORT_ALT1_FUNC_MODE)
#define    PORT172_EMIOS0_E0UC_0_X_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT172_EMIOS0_E0UC_0_X_IN        (PORT_INPUT1_MODE)
#define    PORT172_LIN_14_LIN14RX        (PORT_INPUT2_MODE)
#define    PORT172_SPI_0_SS_0        (PORT_INPUT3_MODE)
#define    PORT172_EMIOS0_E0UC_0_X_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT173_GPIO        (PORT_GPIO_MODE)
#define    PORT173_SPI_2_CS3_2        (PORT_ALT1_FUNC_MODE)
#define    PORT173_SPI_3_CS2_3        (PORT_ALT2_FUNC_MODE)
#define    PORT173_SPI_1_SCLK_1_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT173_EMIOS0_E0UC_1_G_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT173_EMIOS0_E0UC_1_G_IN        (PORT_INPUT1_MODE)
#define    PORT173_FlexCAN_3_RX        (PORT_INPUT2_MODE)
#define    PORT173_SPI_1_SCLK_1_IN        (PORT_INPUT3_MODE)
#define    PORT173_SPI_1_SCLK_1_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT173_EMIOS0_E0UC_1_G_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT174_GPIO        (PORT_GPIO_MODE)
#define    PORT174_FlexCAN_3_TX        (PORT_ALT1_FUNC_MODE)
#define    PORT174_SPI_3_CS3_3        (PORT_ALT2_FUNC_MODE)
#define    PORT174_SPI_1_CS0_1        (PORT_ALT3_FUNC_MODE)
#define    PORT174_EMIOS0_E0UC_2_G_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT174_EMIOS0_E0UC_2_G_IN        (PORT_INPUT1_MODE)
#define    PORT174_SPI_1_SS_1        (PORT_INPUT2_MODE)
#define    PORT174_EMIOS0_E0UC_2_G_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT175_GPIO        (PORT_GPIO_MODE)
#define    PORT175_SPI_0_CS2_0        (PORT_ALT1_FUNC_MODE)
#define    PORT175_EMIOS0_E0UC_3_G_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT175_LIN_13_LIN13TX        (PORT_ALT3_FUNC_MODE)
#define    PORT175_EMIOS0_E0UC_3_G_IN        (PORT_INPUT1_MODE)
#define    PORT175_SPI_1_SIN_1        (PORT_INPUT2_MODE)
#define    PORT175_SPI_3_SIN_3        (PORT_INPUT3_MODE)
#define    PORT175_EMIOS0_E0UC_3_G_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT176_GPIO        (PORT_GPIO_MODE)
#define    PORT176_SPI_1_SOUT_1        (PORT_ALT1_FUNC_MODE)
#define    PORT176_SPI_3_SOUT_3        (PORT_ALT2_FUNC_MODE)
#define    PORT176_SPI_0_CS3_0        (PORT_ALT3_FUNC_MODE)
#define    PORT176_EMIOS0_E0UC_4_G_OUT        (PORT_ALT4_FUNC_MODE)
#define    PORT176_EMIOS0_E0UC_4_G_IN        (PORT_INPUT1_MODE)
#define    PORT176_LIN_13_LIN13RX        (PORT_INPUT2_MODE)
#define    PORT176_EMIOS0_E0UC_4_G_IN_OUT        (PORT_INOUT4_MODE)
#define    PORT177_GPIO        (PORT_GPIO_MODE)
#define    PORT177_SAI0_SAI0_D0_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT177_ADC_0_ADC0_S_47        (PORT_ANALOG_INPUT_MODE)
#define    PORT177_SAI0_SAI0_D0_IN        (PORT_INPUT1_MODE)
#define    PORT177_SAI0_SAI0_D0_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT178_GPIO        (PORT_GPIO_MODE)
#define    PORT178_DCI_MDO_0        (PORT_ALT1_FUNC_MODE)
#define    PORT179_GPIO        (PORT_GPIO_MODE)
#define    PORT179_DCI_MDO_1        (PORT_ALT1_FUNC_MODE)
#define    PORT180_GPIO        (PORT_GPIO_MODE)
#define    PORT180_DCI_MDO_2        (PORT_ALT1_FUNC_MODE)
#define    PORT181_GPIO        (PORT_GPIO_MODE)
#define    PORT181_DCI_MDO_3        (PORT_ALT1_FUNC_MODE)
#define    PORT182_GPIO        (PORT_GPIO_MODE)
#define    PORT182_DCI_MDO_4        (PORT_ALT1_FUNC_MODE)
#define    PORT183_GPIO        (PORT_GPIO_MODE)
#define    PORT183_DCI_MDO_5        (PORT_ALT1_FUNC_MODE)
#define    PORT184_GPIO        (PORT_GPIO_MODE)
#define    PORT184_DCI_EVTI        (PORT_ALT1_FUNC_MODE)
#define    PORT185_GPIO        (PORT_GPIO_MODE)
#define    PORT185_DCI_MSEO0        (PORT_ALT1_FUNC_MODE)
#define    PORT186_GPIO        (PORT_GPIO_MODE)
#define    PORT186_DCI_MCKO        (PORT_ALT1_FUNC_MODE)
#define    PORT187_GPIO        (PORT_GPIO_MODE)
#define    PORT187_DCI_MSEO1        (PORT_ALT1_FUNC_MODE)
#define    PORT188_GPIO        (PORT_GPIO_MODE)
#define    PORT188_DCI_EVTO        (PORT_ALT1_FUNC_MODE)
#define    PORT189_GPIO        (PORT_GPIO_MODE)
#define    PORT189_DCI_MDO_6        (PORT_ALT1_FUNC_MODE)
#define    PORT190_GPIO        (PORT_GPIO_MODE)
#define    PORT190_DCI_MDO_7        (PORT_ALT1_FUNC_MODE)
#define    PORT191_GPIO        (PORT_GPIO_MODE)
#define    PORT191_DCI_MDO_8        (PORT_ALT1_FUNC_MODE)
#define    PORT192_GPIO        (PORT_GPIO_MODE)
#define    PORT192_DCI_MDO_9        (PORT_ALT1_FUNC_MODE)
#define    PORT193_GPIO        (PORT_GPIO_MODE)
#define    PORT193_DCI_MDO_10        (PORT_ALT1_FUNC_MODE)
#define    PORT194_GPIO        (PORT_GPIO_MODE)
#define    PORT194_DCI_MDO_11        (PORT_ALT1_FUNC_MODE)
#define    PORT195_GPIO        (PORT_GPIO_MODE)
#define    PORT195_SAI0_SAI0_D1_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT195_ENET0_ENET0_TMR2_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT195_ADC_0_ADC0_S_46        (PORT_ANALOG_INPUT_MODE)
#define    PORT195_SAI0_SAI0_D1_IN        (PORT_INPUT1_MODE)
#define    PORT195_ENET0_ENET0_TMR2_IN        (PORT_INPUT2_MODE)
#define    PORT195_SAI0_SAI0_D1_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT195_ENET0_ENET0_TMR2_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT196_GPIO        (PORT_GPIO_MODE)
#define    PORT196_SAI0_SAI0_D2_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT196_ADC_0_ADC0_S_45        (PORT_ANALOG_INPUT_MODE)
#define    PORT196_SAI0_SAI0_D2_IN        (PORT_INPUT1_MODE)
#define    PORT196_SAI0_SAI0_D2_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT197_GPIO        (PORT_GPIO_MODE)
#define    PORT197_SAI0_SAI0_D3_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT197_DCI_TCK_ALT        (PORT_ALT2_FUNC_MODE)
#define    PORT197_ADC_0_ADC0_S_44        (PORT_ANALOG_INPUT_MODE)
#define    PORT197_SAI0_SAI0_D3_IN        (PORT_INPUT1_MODE)
#define    PORT197_SAI0_SAI0_D3_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT198_GPIO        (PORT_GPIO_MODE)
#define    PORT198_DCI_TDI_ALT        (PORT_ALT2_FUNC_MODE)
#define    PORT199_GPIO        (PORT_GPIO_MODE)
#define    PORT199_DCI_MDO_12        (PORT_ALT1_FUNC_MODE)
#define    PORT200_GPIO        (PORT_GPIO_MODE)
#define    PORT200_DCI_MDO_13        (PORT_ALT1_FUNC_MODE)
#define    PORT201_GPIO        (PORT_GPIO_MODE)
#define    PORT201_DCI_MDO_14        (PORT_ALT1_FUNC_MODE)
#define    PORT202_GPIO        (PORT_GPIO_MODE)
#define    PORT202_DCI_MDO_15        (PORT_ALT1_FUNC_MODE)
#define    PORT205_GPIO        (PORT_GPIO_MODE)
#define    PORT205_DCI_TDO_ALT        (PORT_ALT2_FUNC_MODE)
#define    PORT206_GPIO        (PORT_GPIO_MODE)
#define    PORT206_SAI0_SAI0_MCLK_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT206_DCI_TMS_ALT_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT206_DCI_TMS_ALT_IN        (PORT_ONLY_INPUT_MODE)
#define    PORT206_DCI_TMS_ALT_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT206_ADC_1_ADC1_S_15        (PORT_ANALOG_INPUT_MODE)
#define    PORT206_SAI0_SAI0_MCLK_IN        (PORT_INPUT1_MODE)
#define    PORT206_SAI0_SAI0_MCLK_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT224_GPIO        (PORT_GPIO_MODE)
#define    PORT224_IIC_0_SDA0_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT224_LIN_12_LIN12TX        (PORT_ALT3_FUNC_MODE)
#define    PORT224_IIC_0_SDA0_IN        (PORT_INPUT1_MODE)
#define    PORT224_IIC_0_SDA0_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT225_GPIO        (PORT_GPIO_MODE)
#define    PORT225_IIC_0_SCL0_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT225_LIN_12_LIN12RX        (PORT_INPUT1_MODE)
#define    PORT225_IIC_0_SCL0_IN        (PORT_INPUT2_MODE)
#define    PORT225_IIC_0_SCL0_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT252_GPIO        (PORT_GPIO_MODE)
#define    PORT252_SPI_2_CS0_2        (PORT_ALT1_FUNC_MODE)
#define    PORT252_DSPI_0_dCS4        (PORT_ALT2_FUNC_MODE)
#define    PORT252_EMIOS1_E1UC_24_X_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT252_EMIOS1_E1UC_24_X_IN        (PORT_INPUT1_MODE)
#define    PORT252_SPI_2_SS_2        (PORT_INPUT2_MODE)
#define    PORT252_EMIOS1_E1UC_24_X_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT253_GPIO        (PORT_GPIO_MODE)
#define    PORT253_SPI_2_SOUT_2        (PORT_ALT1_FUNC_MODE)
#define    PORT253_EMIOS1_E1UC_23_X_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT253_EMIOS1_E1UC_23_X_IN        (PORT_INPUT1_MODE)
#define    PORT253_EMIOS1_E1UC_23_X_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT254_GPIO        (PORT_GPIO_MODE)
#define    PORT254_SPI_2_SCLK_2_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT254_EMIOS1_E1UC_22_X_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT254_EMIOS1_E1UC_22_X_IN        (PORT_INPUT1_MODE)
#define    PORT254_SPI_2_SCLK_2_IN        (PORT_INPUT2_MODE)
#define    PORT254_SPI_2_SCLK_2_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT254_EMIOS1_E1UC_22_X_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT255_GPIO        (PORT_GPIO_MODE)
#define    PORT255_EMIOS1_E1UC_21_Y_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT255_EMIOS1_E1UC_21_Y_IN        (PORT_INPUT1_MODE)
#define    PORT255_SPI_2_SIN_2        (PORT_INPUT2_MODE)
#define    PORT255_EMIOS1_E1UC_21_Y_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT256_GPIO        (PORT_GPIO_MODE)
#define    PORT256_DSPI_0_dCS1        (PORT_ALT1_FUNC_MODE)
#define    PORT257_GPIO        (PORT_GPIO_MODE)
#define    PORT257_DSPI_0_dCS0        (PORT_ALT1_FUNC_MODE)
#define    PORT257_DSPI_0_dSS        (PORT_INPUT1_MODE)
#define    PORT258_GPIO        (PORT_GPIO_MODE)
#define    PORT258_DSPI_0_dSCLK_OUT        (PORT_ALT1_FUNC_MODE)
#define    PORT258_DSPI_0_dSCLK_IN        (PORT_INPUT1_MODE)
#define    PORT258_DSPI_0_dSCLK_IN_OUT        (PORT_INOUT1_MODE)
#define    PORT259_GPIO        (PORT_GPIO_MODE)
#define    PORT259_DSPI_0_dSIN        (PORT_INPUT1_MODE)
#define    PORT260_GPIO        (PORT_GPIO_MODE)
#define    PORT260_DSPI_0_dSOUT        (PORT_ALT1_FUNC_MODE)
#define    PORT260_EMIOS1_E1UC_28_Y_OUT        (PORT_ALT2_FUNC_MODE)
#define    PORT260_EMIOS1_E1UC_28_Y_IN        (PORT_INPUT1_MODE)
#define    PORT260_GLITCH_FILTER2_INP        (PORT_INPUT2_MODE)
#define    PORT260_EMIOS1_E1UC_28_Y_IN_OUT        (PORT_INOUT2_MODE)
#define    PORT261_GPIO        (PORT_GPIO_MODE)
#define    PORT261_SPI_2_CS3_2        (PORT_ALT1_FUNC_MODE)
#define    PORT261_DSPI_0_dCS3        (PORT_ALT2_FUNC_MODE)
#define    PORT261_EMIOS1_E1UC_27_Y_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT261_EMIOS1_E1UC_27_Y_IN        (PORT_INPUT1_MODE)
#define    PORT261_EMIOS1_E1UC_27_Y_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT262_GPIO        (PORT_GPIO_MODE)
#define    PORT262_SPI_2_CS2_2        (PORT_ALT1_FUNC_MODE)
#define    PORT262_DSPI_0_dCS2        (PORT_ALT2_FUNC_MODE)
#define    PORT262_EMIOS1_E1UC_26_Y_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT262_EMIOS1_E1UC_26_Y_IN        (PORT_INPUT1_MODE)
#define    PORT262_EMIOS1_E1UC_26_Y_IN_OUT        (PORT_INOUT3_MODE)
#define    PORT263_GPIO        (PORT_GPIO_MODE)
#define    PORT263_SPI_2_CS1_2        (PORT_ALT1_FUNC_MODE)
#define    PORT263_DSPI_0_dCS5        (PORT_ALT2_FUNC_MODE)
#define    PORT263_EMIOS1_E1UC_25_Y_OUT        (PORT_ALT3_FUNC_MODE)
#define    PORT263_EMIOS1_E1UC_25_Y_IN        (PORT_INPUT1_MODE)
#define    PORT263_EMIOS1_E1UC_25_Y_IN_OUT        (PORT_INOUT3_MODE)
[!ENDVAR!]




[!VAR "PinAbstractionModes_"!]

[!ENDVAR!]




[!VAR "INMUX0"!]
EMIOS0_E0UC_0_X_IN_PORT0;2:[!//
EMIOS0_E0UC_0_X_IN_OUT_PORT0;2:[!//
EMIOS0_E0UC_0_X_IN_PORT14;3:[!//
EMIOS0_E0UC_0_X_IN_OUT_PORT14;3:[!//
EMIOS0_E0UC_0_X_IN_PORT105;5:[!//
EMIOS0_E0UC_0_X_IN_OUT_PORT105;5:[!//
EMIOS0_E0UC_0_X_IN_PORT172;4:[!//
EMIOS0_E0UC_0_X_IN_OUT_PORT172;4:[!//
[!ENDVAR!]

[!VAR "INMUX1"!]
EMIOS0_E0UC_1_G_IN_PORT1;2:[!//
EMIOS0_E0UC_1_G_IN_OUT_PORT1;2:[!//
EMIOS0_E0UC_1_G_IN_PORT15;3:[!//
EMIOS0_E0UC_1_G_IN_OUT_PORT15;3:[!//
EMIOS0_E0UC_1_G_IN_PORT43;5:[!//
EMIOS0_E0UC_1_G_IN_OUT_PORT43;5:[!//
EMIOS0_E0UC_1_G_IN_PORT173;4:[!//
EMIOS0_E0UC_1_G_IN_OUT_PORT173;4:[!//
[!ENDVAR!]

[!VAR "INMUX2"!]
EMIOS0_E0UC_2_G_IN_PORT2;2:[!//
EMIOS0_E0UC_2_G_IN_OUT_PORT2;2:[!//
EMIOS0_E0UC_2_G_IN_PORT101;4:[!//
EMIOS0_E0UC_2_G_IN_OUT_PORT101;4:[!//
EMIOS0_E0UC_2_G_IN_PORT174;3:[!//
EMIOS0_E0UC_2_G_IN_OUT_PORT174;3:[!//
[!ENDVAR!]

[!VAR "INMUX3"!]
EMIOS0_E0UC_3_G_IN_PORT3;2:[!//
EMIOS0_E0UC_3_G_IN_OUT_PORT3;2:[!//
EMIOS0_E0UC_3_G_IN_PORT27;3:[!//
EMIOS0_E0UC_3_G_IN_OUT_PORT27;3:[!//
EMIOS0_E0UC_3_G_IN_PORT40;4:[!//
EMIOS0_E0UC_3_G_IN_OUT_PORT40;4:[!//
EMIOS0_E0UC_3_G_IN_PORT102;6:[!//
EMIOS0_E0UC_3_G_IN_OUT_PORT102;6:[!//
EMIOS0_E0UC_3_G_IN_PORT175;5:[!//
EMIOS0_E0UC_3_G_IN_OUT_PORT175;5:[!//
[!ENDVAR!]

[!VAR "INMUX4"!]
EMIOS0_E0UC_4_G_IN_PORT4;2:[!//
EMIOS0_E0UC_4_G_IN_OUT_PORT4;2:[!//
EMIOS0_E0UC_4_G_IN_PORT16;5:[!//
EMIOS0_E0UC_4_G_IN_OUT_PORT16;5:[!//
EMIOS0_E0UC_4_G_IN_PORT28;3:[!//
EMIOS0_E0UC_4_G_IN_OUT_PORT28;3:[!//
EMIOS0_E0UC_4_G_IN_PORT176;4:[!//
EMIOS0_E0UC_4_G_IN_OUT_PORT176;4:[!//
[!ENDVAR!]

[!VAR "INMUX5"!]
EMIOS0_E0UC_5_G_IN_PORT5;2:[!//
EMIOS0_E0UC_5_G_IN_OUT_PORT5;2:[!//
EMIOS0_E0UC_5_G_IN_PORT17;4:[!//
EMIOS0_E0UC_5_G_IN_OUT_PORT17;4:[!//
EMIOS0_E0UC_5_G_IN_PORT29;3:[!//
EMIOS0_E0UC_5_G_IN_OUT_PORT29;3:[!//
[!ENDVAR!]

[!VAR "INMUX6"!]
EMIOS0_E0UC_6_G_IN_PORT6;2:[!//
EMIOS0_E0UC_6_G_IN_OUT_PORT6;2:[!//
EMIOS0_E0UC_6_G_IN_PORT30;3:[!//
EMIOS0_E0UC_6_G_IN_OUT_PORT30;3:[!//
EMIOS0_E0UC_6_G_IN_PORT161;4:[!//
EMIOS0_E0UC_6_G_IN_OUT_PORT161;4:[!//
[!ENDVAR!]

[!VAR "INMUX7"!]
EMIOS0_E0UC_7_G_IN_PORT7;2:[!//
EMIOS0_E0UC_7_G_IN_OUT_PORT7;2:[!//
EMIOS0_E0UC_7_G_IN_PORT31;3:[!//
EMIOS0_E0UC_7_G_IN_OUT_PORT31;3:[!//
EMIOS0_E0UC_7_G_IN_PORT41;4:[!//
EMIOS0_E0UC_7_G_IN_OUT_PORT41;4:[!//
[!ENDVAR!]

[!VAR "INMUX8"!]
EMIOS0_E0UC_8_X_IN_PORT8;2:[!//
EMIOS0_E0UC_8_X_IN_OUT_PORT8;2:[!//
EMIOS0_E0UC_8_X_IN_PORT19;3:[!//
EMIOS0_E0UC_8_X_IN_OUT_PORT19;3:[!//
[!ENDVAR!]

[!VAR "INMUX9"!]
EMIOS0_E0UC_9_H_IN_PORT9;2:[!//
EMIOS0_E0UC_9_H_IN_OUT_PORT9;2:[!//
EMIOS0_E0UC_9_H_IN_PORT164;3:[!//
EMIOS0_E0UC_9_H_IN_OUT_PORT164;3:[!//
[!ENDVAR!]

[!VAR "INMUX10"!]
EMIOS0_E0UC_10_H_IN_PORT10;2:[!//
EMIOS0_E0UC_10_H_IN_OUT_PORT10;2:[!//
EMIOS0_E0UC_10_H_IN_PORT80;3:[!//
EMIOS0_E0UC_10_H_IN_OUT_PORT80;3:[!//
EMIOS0_E0UC_10_H_IN_PORT165;4:[!//
EMIOS0_E0UC_10_H_IN_OUT_PORT165;4:[!//
[!ENDVAR!]

[!VAR "INMUX11"!]
EMIOS0_E0UC_11_H_IN_PORT11;2:[!//
EMIOS0_E0UC_11_H_IN_OUT_PORT11;2:[!//
EMIOS0_E0UC_11_H_IN_PORT81;3:[!//
EMIOS0_E0UC_11_H_IN_OUT_PORT81;3:[!//
EMIOS0_E0UC_11_H_IN_PORT166;4:[!//
EMIOS0_E0UC_11_H_IN_OUT_PORT166;4:[!//
[!ENDVAR!]

[!VAR "INMUX12"!]
EMIOS0_E0UC_12_H_IN_PORT44;2:[!//
EMIOS0_E0UC_12_H_IN_OUT_PORT44;2:[!//
EMIOS0_E0UC_12_H_IN_PORT82;3:[!//
EMIOS0_E0UC_12_H_IN_OUT_PORT82;3:[!//
EMIOS0_E0UC_12_H_IN_PORT167;4:[!//
EMIOS0_E0UC_12_H_IN_OUT_PORT167;4:[!//
[!ENDVAR!]

[!VAR "INMUX13"!]
EMIOS0_E0UC_13_H_IN_PORT0;2:[!//
EMIOS0_E0UC_13_H_IN_OUT_PORT0;2:[!//
EMIOS0_E0UC_13_H_IN_PORT45;3:[!//
EMIOS0_E0UC_13_H_IN_OUT_PORT45;3:[!//
EMIOS0_E0UC_13_H_IN_PORT83;4:[!//
EMIOS0_E0UC_13_H_IN_OUT_PORT83;4:[!//
EMIOS0_E0UC_13_H_IN_PORT168;5:[!//
EMIOS0_E0UC_13_H_IN_OUT_PORT168;5:[!//
[!ENDVAR!]

[!VAR "INMUX14"!]
EMIOS0_E0UC_14_H_IN_PORT8;2:[!//
EMIOS0_E0UC_14_H_IN_OUT_PORT8;2:[!//
EMIOS0_E0UC_14_H_IN_PORT46;3:[!//
EMIOS0_E0UC_14_H_IN_OUT_PORT46;3:[!//
EMIOS0_E0UC_14_H_IN_PORT84;4:[!//
EMIOS0_E0UC_14_H_IN_OUT_PORT84;4:[!//
EMIOS0_E0UC_14_H_IN_PORT89;5:[!//
EMIOS0_E0UC_14_H_IN_OUT_PORT89;5:[!//
[!ENDVAR!]

[!VAR "INMUX15"!]
EMIOS0_E0UC_15_H_IN_PORT47;2:[!//
EMIOS0_E0UC_15_H_IN_OUT_PORT47;2:[!//
EMIOS0_E0UC_15_H_IN_PORT88;3:[!//
EMIOS0_E0UC_15_H_IN_OUT_PORT88;3:[!//
[!ENDVAR!]

[!VAR "INMUX16"!]
EMIOS0_E0UC_16_X_IN_PORT64;2:[!//
EMIOS0_E0UC_16_X_IN_OUT_PORT64;2:[!//
EMIOS0_E0UC_16_X_IN_PORT92;3:[!//
EMIOS0_E0UC_16_X_IN_OUT_PORT92;3:[!//
[!ENDVAR!]

[!VAR "INMUX17"!]
EMIOS0_E0UC_17_Y_IN_PORT38;3:[!//
EMIOS0_E0UC_17_Y_IN_OUT_PORT38;3:[!//
EMIOS0_E0UC_17_Y_IN_PORT65;2:[!//
EMIOS0_E0UC_17_Y_IN_OUT_PORT65;2:[!//
[!ENDVAR!]

[!VAR "INMUX18"!]
EMIOS0_E0UC_18_Y_IN_PORT39;3:[!//
EMIOS0_E0UC_18_Y_IN_OUT_PORT39;3:[!//
EMIOS0_E0UC_18_Y_IN_PORT66;2:[!//
EMIOS0_E0UC_18_Y_IN_OUT_PORT66;2:[!//
[!ENDVAR!]

[!VAR "INMUX19"!]
EMIOS0_E0UC_19_Y_IN_PORT67;2:[!//
EMIOS0_E0UC_19_Y_IN_OUT_PORT67;2:[!//
EMIOS0_E0UC_19_Y_IN_PORT90;3:[!//
EMIOS0_E0UC_19_Y_IN_OUT_PORT90;3:[!//
[!ENDVAR!]

[!VAR "INMUX20"!]
EMIOS0_E0UC_20_Y_IN_PORT68;2:[!//
EMIOS0_E0UC_20_Y_IN_OUT_PORT68;2:[!//
EMIOS0_E0UC_20_Y_IN_PORT91;3:[!//
EMIOS0_E0UC_20_Y_IN_OUT_PORT91;3:[!//
[!ENDVAR!]

[!VAR "INMUX21"!]
EMIOS0_E0UC_21_Y_IN_PORT15;3:[!//
EMIOS0_E0UC_21_Y_IN_OUT_PORT15;3:[!//
EMIOS0_E0UC_21_Y_IN_PORT69;2:[!//
EMIOS0_E0UC_21_Y_IN_OUT_PORT69;2:[!//
[!ENDVAR!]

[!VAR "INMUX22"!]
EMIOS0_E0UC_22_X_IN_PORT70;2:[!//
EMIOS0_E0UC_22_X_IN_OUT_PORT70;2:[!//
EMIOS0_E0UC_22_X_IN_PORT72;3:[!//
EMIOS0_E0UC_22_X_IN_OUT_PORT72;3:[!//
EMIOS0_E0UC_22_X_IN_PORT85;4:[!//
EMIOS0_E0UC_22_X_IN_OUT_PORT85;4:[!//
EMIOS0_E0UC_22_X_IN_PORT93;5:[!//
EMIOS0_E0UC_22_X_IN_OUT_PORT93;5:[!//
[!ENDVAR!]

[!VAR "INMUX23"!]
EMIOS0_E0UC_23_X_IN_PORT14;5:[!//
EMIOS0_E0UC_23_X_IN_OUT_PORT14;5:[!//
EMIOS0_E0UC_23_X_IN_PORT71;2:[!//
EMIOS0_E0UC_23_X_IN_OUT_PORT71;2:[!//
EMIOS0_E0UC_23_X_IN_PORT73;3:[!//
EMIOS0_E0UC_23_X_IN_OUT_PORT73;3:[!//
EMIOS0_E0UC_23_X_IN_PORT86;4:[!//
EMIOS0_E0UC_23_X_IN_OUT_PORT86;4:[!//
[!ENDVAR!]

[!VAR "INMUX24"!]
EMIOS0_E0UC_24_X_IN_PORT4;5:[!//
EMIOS0_E0UC_24_X_IN_OUT_PORT4;5:[!//
EMIOS0_E0UC_24_X_IN_PORT60;2:[!//
EMIOS0_E0UC_24_X_IN_OUT_PORT60;2:[!//
EMIOS0_E0UC_24_X_IN_PORT75;3:[!//
EMIOS0_E0UC_24_X_IN_OUT_PORT75;3:[!//
EMIOS0_E0UC_24_X_IN_PORT106;4:[!//
EMIOS0_E0UC_24_X_IN_OUT_PORT106;4:[!//
[!ENDVAR!]

[!VAR "INMUX25"!]
EMIOS0_E0UC_25_Y_IN_PORT13;4:[!//
EMIOS0_E0UC_25_Y_IN_OUT_PORT13;4:[!//
EMIOS0_E0UC_25_Y_IN_PORT61;2:[!//
EMIOS0_E0UC_25_Y_IN_OUT_PORT61;2:[!//
EMIOS0_E0UC_25_Y_IN_PORT107;3:[!//
EMIOS0_E0UC_25_Y_IN_OUT_PORT107;3:[!//
[!ENDVAR!]

[!VAR "INMUX26"!]
EMIOS0_E0UC_26_Y_IN_PORT12;4:[!//
EMIOS0_E0UC_26_Y_IN_OUT_PORT12;4:[!//
EMIOS0_E0UC_26_Y_IN_PORT62;2:[!//
EMIOS0_E0UC_26_Y_IN_OUT_PORT62;2:[!//
EMIOS0_E0UC_26_Y_IN_PORT108;3:[!//
EMIOS0_E0UC_26_Y_IN_OUT_PORT108;3:[!//
[!ENDVAR!]

[!VAR "INMUX27"!]
EMIOS0_E0UC_27_Y_IN_PORT63;2:[!//
EMIOS0_E0UC_27_Y_IN_OUT_PORT63;2:[!//
EMIOS0_E0UC_27_Y_IN_PORT109;3:[!//
EMIOS0_E0UC_27_Y_IN_OUT_PORT109;3:[!//
[!ENDVAR!]

[!VAR "INMUX28"!]
EMIOS0_E0UC_28_Y_IN_PORT12;2:[!//
EMIOS0_E0UC_28_Y_IN_OUT_PORT12;2:[!//
EMIOS0_E0UC_28_Y_IN_PORT128;3:[!//
EMIOS0_E0UC_28_Y_IN_OUT_PORT128;3:[!//
[!ENDVAR!]

[!VAR "INMUX29"!]
EMIOS0_E0UC_29_Y_IN_PORT13;2:[!//
EMIOS0_E0UC_29_Y_IN_OUT_PORT13;2:[!//
EMIOS0_E0UC_29_Y_IN_PORT26;4:[!//
EMIOS0_E0UC_29_Y_IN_OUT_PORT26;4:[!//
EMIOS0_E0UC_29_Y_IN_PORT129;3:[!//
EMIOS0_E0UC_29_Y_IN_OUT_PORT129;3:[!//
[!ENDVAR!]

[!VAR "INMUX30"!]
EMIOS0_E0UC_30_Y_IN_PORT16;2:[!//
EMIOS0_E0UC_30_Y_IN_OUT_PORT16;2:[!//
EMIOS0_E0UC_30_Y_IN_PORT18;3:[!//
EMIOS0_E0UC_30_Y_IN_OUT_PORT18;3:[!//
EMIOS0_E0UC_30_Y_IN_PORT86;5:[!//
EMIOS0_E0UC_30_Y_IN_OUT_PORT86;5:[!//
EMIOS0_E0UC_30_Y_IN_PORT130;4:[!//
EMIOS0_E0UC_30_Y_IN_OUT_PORT130;4:[!//
[!ENDVAR!]

[!VAR "INMUX31"!]
EMIOS0_E0UC_31_Y_IN_PORT17;2:[!//
EMIOS0_E0UC_31_Y_IN_OUT_PORT17;2:[!//
EMIOS0_E0UC_31_Y_IN_PORT19;3:[!//
EMIOS0_E0UC_31_Y_IN_OUT_PORT19;3:[!//
EMIOS0_E0UC_31_Y_IN_PORT131;4:[!//
EMIOS0_E0UC_31_Y_IN_OUT_PORT131;4:[!//
[!ENDVAR!]

[!VAR "INMUX32"!]
[!ENDVAR!]

[!VAR "INMUX33"!]
[!ENDVAR!]

[!VAR "INMUX34"!]
[!ENDVAR!]

[!VAR "INMUX35"!]
[!ENDVAR!]

[!VAR "INMUX36"!]
EMIOS1_E1UC_0_X_IN_PORT110;2:[!//
EMIOS1_E1UC_0_X_IN_OUT_PORT110;2:[!//
EMIOS1_E1UC_0_X_IN_PORT163;3:[!//
EMIOS1_E1UC_0_X_IN_OUT_PORT163;3:[!//
[!ENDVAR!]

[!VAR "INMUX37"!]
EMIOS1_E1UC_1_H_IN_PORT89;2:[!//
EMIOS1_E1UC_1_H_IN_OUT_PORT89;2:[!//
EMIOS1_E1UC_1_H_IN_PORT111;3:[!//
EMIOS1_E1UC_1_H_IN_OUT_PORT111;3:[!//
EMIOS1_E1UC_1_H_IN_PORT161;4:[!//
EMIOS1_E1UC_1_H_IN_OUT_PORT161;4:[!//
EMIOS1_E1UC_1_H_IN_PORT164;5:[!//
EMIOS1_E1UC_1_H_IN_OUT_PORT164;5:[!//
[!ENDVAR!]

[!VAR "INMUX38"!]
EMIOS1_E1UC_2_H_IN_PORT90;2:[!//
EMIOS1_E1UC_2_H_IN_OUT_PORT90;2:[!//
EMIOS1_E1UC_2_H_IN_PORT112;3:[!//
EMIOS1_E1UC_2_H_IN_OUT_PORT112;3:[!//
EMIOS1_E1UC_2_H_IN_PORT162;4:[!//
EMIOS1_E1UC_2_H_IN_OUT_PORT162;4:[!//
[!ENDVAR!]

[!VAR "INMUX39"!]
EMIOS1_E1UC_3_H_IN_PORT91;2:[!//
EMIOS1_E1UC_3_H_IN_OUT_PORT91;2:[!//
EMIOS1_E1UC_3_H_IN_PORT113;3:[!//
EMIOS1_E1UC_3_H_IN_OUT_PORT113;3:[!//
EMIOS1_E1UC_3_H_IN_PORT163;4:[!//
EMIOS1_E1UC_3_H_IN_OUT_PORT163;4:[!//
[!ENDVAR!]

[!VAR "INMUX40"!]
EMIOS1_E1UC_4_H_IN_PORT95;2:[!//
EMIOS1_E1UC_4_H_IN_OUT_PORT95;2:[!//
EMIOS1_E1UC_4_H_IN_PORT114;3:[!//
EMIOS1_E1UC_4_H_IN_OUT_PORT114;3:[!//
EMIOS1_E1UC_4_H_IN_PORT165;4:[!//
EMIOS1_E1UC_4_H_IN_OUT_PORT165;4:[!//
[!ENDVAR!]

[!VAR "INMUX41"!]
EMIOS1_E1UC_5_H_IN_PORT115;2:[!//
EMIOS1_E1UC_5_H_IN_OUT_PORT115;2:[!//
EMIOS1_E1UC_5_H_IN_PORT123;3:[!//
EMIOS1_E1UC_5_H_IN_OUT_PORT123;3:[!//
EMIOS1_E1UC_5_H_IN_PORT166;4:[!//
EMIOS1_E1UC_5_H_IN_OUT_PORT166;4:[!//
[!ENDVAR!]

[!VAR "INMUX42"!]
EMIOS1_E1UC_6_H_IN_PORT116;2:[!//
EMIOS1_E1UC_6_H_IN_OUT_PORT116;2:[!//
EMIOS1_E1UC_6_H_IN_PORT167;3:[!//
EMIOS1_E1UC_6_H_IN_OUT_PORT167;3:[!//
[!ENDVAR!]

[!VAR "INMUX43"!]
EMIOS1_E1UC_7_H_IN_PORT117;2:[!//
EMIOS1_E1UC_7_H_IN_OUT_PORT117;2:[!//
EMIOS1_E1UC_7_H_IN_PORT168;3:[!//
EMIOS1_E1UC_7_H_IN_OUT_PORT168;3:[!//
[!ENDVAR!]

[!VAR "INMUX44"!]
EMIOS1_E1UC_8_X_IN_PORT118;2:[!//
EMIOS1_E1UC_8_X_IN_OUT_PORT118;2:[!//
[!ENDVAR!]

[!VAR "INMUX45"!]
EMIOS1_E1UC_9_H_IN_PORT119;2:[!//
EMIOS1_E1UC_9_H_IN_OUT_PORT119;2:[!//
[!ENDVAR!]

[!VAR "INMUX46"!]
EMIOS1_E1UC_10_H_IN_PORT120;2:[!//
EMIOS1_E1UC_10_H_IN_OUT_PORT120;2:[!//
EMIOS1_E1UC_10_H_IN_PORT156;3:[!//
EMIOS1_E1UC_10_H_IN_OUT_PORT156;3:[!//
[!ENDVAR!]

[!VAR "INMUX47"!]
EMIOS1_E1UC_11_H_IN_PORT98;2:[!//
EMIOS1_E1UC_11_H_IN_OUT_PORT98;2:[!//
EMIOS1_E1UC_11_H_IN_PORT155;3:[!//
EMIOS1_E1UC_11_H_IN_OUT_PORT155;3:[!//
[!ENDVAR!]

[!VAR "INMUX48"!]
EMIOS1_E1UC_12_H_IN_PORT99;2:[!//
EMIOS1_E1UC_12_H_IN_OUT_PORT99;2:[!//
EMIOS1_E1UC_12_H_IN_PORT160;3:[!//
EMIOS1_E1UC_12_H_IN_OUT_PORT160;3:[!//
[!ENDVAR!]

[!VAR "INMUX49"!]
EMIOS1_E1UC_13_H_IN_PORT100;2:[!//
EMIOS1_E1UC_13_H_IN_OUT_PORT100;2:[!//
EMIOS1_E1UC_13_H_IN_PORT159;3:[!//
EMIOS1_E1UC_13_H_IN_OUT_PORT159;3:[!//
[!ENDVAR!]

[!VAR "INMUX50"!]
EMIOS1_E1UC_14_H_IN_PORT101;2:[!//
EMIOS1_E1UC_14_H_IN_OUT_PORT101;2:[!//
EMIOS1_E1UC_14_H_IN_PORT158;3:[!//
EMIOS1_E1UC_14_H_IN_OUT_PORT158;3:[!//
[!ENDVAR!]

[!VAR "INMUX51"!]
EMIOS1_E1UC_15_H_IN_PORT102;2:[!//
EMIOS1_E1UC_15_H_IN_OUT_PORT102;2:[!//
EMIOS1_E1UC_15_H_IN_PORT157;3:[!//
EMIOS1_E1UC_15_H_IN_OUT_PORT157;3:[!//
[!ENDVAR!]

[!VAR "INMUX52"!]
EMIOS1_E1UC_16_X_IN_PORT103;2:[!//
EMIOS1_E1UC_16_X_IN_OUT_PORT103;2:[!//
EMIOS1_E1UC_16_X_IN_PORT154;3:[!//
EMIOS1_E1UC_16_X_IN_OUT_PORT154;3:[!//
[!ENDVAR!]

[!VAR "INMUX53"!]
EMIOS1_E1UC_17_Y_IN_PORT104;2:[!//
EMIOS1_E1UC_17_Y_IN_OUT_PORT104;2:[!//
EMIOS1_E1UC_17_Y_IN_PORT127;3:[!//
EMIOS1_E1UC_17_Y_IN_OUT_PORT127;3:[!//
EMIOS1_E1UC_17_Y_IN_PORT153;4:[!//
EMIOS1_E1UC_17_Y_IN_OUT_PORT153;4:[!//
[!ENDVAR!]

[!VAR "INMUX54"!]
EMIOS1_E1UC_18_Y_IN_PORT105;2:[!//
EMIOS1_E1UC_18_Y_IN_OUT_PORT105;2:[!//
EMIOS1_E1UC_18_Y_IN_PORT148;3:[!//
EMIOS1_E1UC_18_Y_IN_OUT_PORT148;3:[!//
[!ENDVAR!]

[!VAR "INMUX55"!]
EMIOS1_E1UC_19_Y_IN_PORT76;2:[!//
EMIOS1_E1UC_19_Y_IN_OUT_PORT76;2:[!//
[!ENDVAR!]

[!VAR "INMUX56"!]
EMIOS1_E1UC_20_Y_IN_PORT77;2:[!//
EMIOS1_E1UC_20_Y_IN_OUT_PORT77;2:[!//
[!ENDVAR!]

[!VAR "INMUX57"!]
EMIOS1_E1UC_21_Y_IN_PORT78;2:[!//
EMIOS1_E1UC_21_Y_IN_OUT_PORT78;2:[!//
EMIOS1_E1UC_21_Y_IN_PORT255;3:[!//
EMIOS1_E1UC_21_Y_IN_OUT_PORT255;3:[!//
[!ENDVAR!]

[!VAR "INMUX58"!]
EMIOS1_E1UC_22_X_IN_PORT79;2:[!//
EMIOS1_E1UC_22_X_IN_OUT_PORT79;2:[!//
EMIOS1_E1UC_22_X_IN_PORT254;3:[!//
EMIOS1_E1UC_22_X_IN_OUT_PORT254;3:[!//
[!ENDVAR!]

[!VAR "INMUX59"!]
EMIOS1_E1UC_23_X_IN_PORT96;2:[!//
EMIOS1_E1UC_23_X_IN_OUT_PORT96;2:[!//
EMIOS1_E1UC_23_X_IN_PORT253;3:[!//
EMIOS1_E1UC_23_X_IN_OUT_PORT253;3:[!//
[!ENDVAR!]

[!VAR "INMUX60"!]
EMIOS1_E1UC_24_X_IN_PORT97;2:[!//
EMIOS1_E1UC_24_X_IN_OUT_PORT97;2:[!//
EMIOS1_E1UC_24_X_IN_PORT252;3:[!//
EMIOS1_E1UC_24_X_IN_OUT_PORT252;3:[!//
[!ENDVAR!]

[!VAR "INMUX61"!]
EMIOS1_E1UC_25_Y_IN_PORT92;2:[!//
EMIOS1_E1UC_25_Y_IN_OUT_PORT92;2:[!//
EMIOS1_E1UC_25_Y_IN_PORT124;3:[!//
EMIOS1_E1UC_25_Y_IN_OUT_PORT124;3:[!//
EMIOS1_E1UC_25_Y_IN_PORT263;4:[!//
EMIOS1_E1UC_25_Y_IN_OUT_PORT263;4:[!//
[!ENDVAR!]

[!VAR "INMUX62"!]
EMIOS1_E1UC_26_Y_IN_PORT93;2:[!//
EMIOS1_E1UC_26_Y_IN_OUT_PORT93;2:[!//
EMIOS1_E1UC_26_Y_IN_PORT125;3:[!//
EMIOS1_E1UC_26_Y_IN_OUT_PORT125;3:[!//
EMIOS1_E1UC_26_Y_IN_PORT262;4:[!//
EMIOS1_E1UC_26_Y_IN_OUT_PORT262;4:[!//
[!ENDVAR!]

[!VAR "INMUX63"!]
EMIOS1_E1UC_27_Y_IN_PORT94;2:[!//
EMIOS1_E1UC_27_Y_IN_OUT_PORT94;2:[!//
EMIOS1_E1UC_27_Y_IN_PORT126;3:[!//
EMIOS1_E1UC_27_Y_IN_OUT_PORT126;3:[!//
EMIOS1_E1UC_27_Y_IN_PORT261;4:[!//
EMIOS1_E1UC_27_Y_IN_OUT_PORT261;4:[!//
[!ENDVAR!]

[!VAR "INMUX64"!]
EMIOS1_E1UC_28_Y_IN_PORT38;2:[!//
EMIOS1_E1UC_28_Y_IN_OUT_PORT38;2:[!//
EMIOS1_E1UC_28_Y_IN_PORT132;3:[!//
EMIOS1_E1UC_28_Y_IN_OUT_PORT132;3:[!//
EMIOS1_E1UC_28_Y_IN_PORT260;4:[!//
EMIOS1_E1UC_28_Y_IN_OUT_PORT260;4:[!//
[!ENDVAR!]

[!VAR "INMUX65"!]
EMIOS1_E1UC_29_Y_IN_PORT39;2:[!//
EMIOS1_E1UC_29_Y_IN_OUT_PORT39;2:[!//
EMIOS1_E1UC_29_Y_IN_PORT133;3:[!//
EMIOS1_E1UC_29_Y_IN_OUT_PORT133;3:[!//
EMIOS1_E1UC_29_Y_IN_PORT169;4:[!//
EMIOS1_E1UC_29_Y_IN_OUT_PORT169;4:[!//
[!ENDVAR!]

[!VAR "INMUX66"!]
EMIOS1_E1UC_30_Y_IN_PORT74;2:[!//
EMIOS1_E1UC_30_Y_IN_OUT_PORT74;2:[!//
EMIOS1_E1UC_30_Y_IN_PORT103;3:[!//
EMIOS1_E1UC_30_Y_IN_OUT_PORT103;3:[!//
EMIOS1_E1UC_30_Y_IN_PORT134;4:[!//
EMIOS1_E1UC_30_Y_IN_OUT_PORT134;4:[!//
EMIOS1_E1UC_30_Y_IN_PORT170;5:[!//
EMIOS1_E1UC_30_Y_IN_OUT_PORT170;5:[!//
[!ENDVAR!]

[!VAR "INMUX67"!]
EMIOS1_E1UC_31_Y_IN_PORT36;2:[!//
EMIOS1_E1UC_31_Y_IN_OUT_PORT36;2:[!//
EMIOS1_E1UC_31_Y_IN_PORT106;3:[!//
EMIOS1_E1UC_31_Y_IN_OUT_PORT106;3:[!//
EMIOS1_E1UC_31_Y_IN_PORT135;4:[!//
EMIOS1_E1UC_31_Y_IN_OUT_PORT135;4:[!//
EMIOS1_E1UC_31_Y_IN_PORT171;5:[!//
EMIOS1_E1UC_31_Y_IN_OUT_PORT171;5:[!//
[!ENDVAR!]

[!VAR "INMUX68"!]
[!ENDVAR!]

[!VAR "INMUX69"!]
[!ENDVAR!]

[!VAR "INMUX70"!]
[!ENDVAR!]

[!VAR "INMUX71"!]
[!ENDVAR!]

[!VAR "INMUX72"!]
[!ENDVAR!]

[!VAR "INMUX73"!]
[!ENDVAR!]

[!VAR "INMUX74"!]
[!ENDVAR!]

[!VAR "INMUX75"!]
[!ENDVAR!]

[!VAR "INMUX76"!]
[!ENDVAR!]

[!VAR "INMUX77"!]
[!ENDVAR!]

[!VAR "INMUX78"!]
[!ENDVAR!]

[!VAR "INMUX79"!]
[!ENDVAR!]

[!VAR "INMUX80"!]
[!ENDVAR!]

[!VAR "INMUX81"!]
[!ENDVAR!]

[!VAR "INMUX82"!]
[!ENDVAR!]

[!VAR "INMUX83"!]
[!ENDVAR!]

[!VAR "INMUX84"!]
[!ENDVAR!]

[!VAR "INMUX85"!]
[!ENDVAR!]

[!VAR "INMUX86"!]
[!ENDVAR!]

[!VAR "INMUX87"!]
[!ENDVAR!]

[!VAR "INMUX88"!]
[!ENDVAR!]

[!VAR "INMUX89"!]
[!ENDVAR!]

[!VAR "INMUX90"!]
[!ENDVAR!]

[!VAR "INMUX91"!]
[!ENDVAR!]

[!VAR "INMUX92"!]
[!ENDVAR!]

[!VAR "INMUX93"!]
[!ENDVAR!]

[!VAR "INMUX94"!]
[!ENDVAR!]

[!VAR "INMUX95"!]
[!ENDVAR!]

[!VAR "INMUX96"!]
[!ENDVAR!]

[!VAR "INMUX97"!]
[!ENDVAR!]

[!VAR "INMUX98"!]
[!ENDVAR!]

[!VAR "INMUX99"!]
[!ENDVAR!]

[!VAR "INMUX100"!]
[!ENDVAR!]

[!VAR "INMUX101"!]
[!ENDVAR!]

[!VAR "INMUX102"!]
[!ENDVAR!]

[!VAR "INMUX103"!]
[!ENDVAR!]

[!VAR "INMUX104"!]
[!ENDVAR!]

[!VAR "INMUX105"!]
[!ENDVAR!]

[!VAR "INMUX106"!]
[!ENDVAR!]

[!VAR "INMUX107"!]
[!ENDVAR!]

[!VAR "INMUX108"!]
[!ENDVAR!]

[!VAR "INMUX109"!]
[!ENDVAR!]

[!VAR "INMUX110"!]
[!ENDVAR!]

[!VAR "INMUX111"!]
[!ENDVAR!]

[!VAR "INMUX112"!]
[!ENDVAR!]

[!VAR "INMUX113"!]
[!ENDVAR!]

[!VAR "INMUX114"!]
[!ENDVAR!]

[!VAR "INMUX115"!]
[!ENDVAR!]

[!VAR "INMUX116"!]
[!ENDVAR!]

[!VAR "INMUX117"!]
[!ENDVAR!]

[!VAR "INMUX118"!]
[!ENDVAR!]

[!VAR "INMUX119"!]
[!ENDVAR!]

[!VAR "INMUX120"!]
[!ENDVAR!]

[!VAR "INMUX121"!]
[!ENDVAR!]

[!VAR "INMUX122"!]
[!ENDVAR!]

[!VAR "INMUX123"!]
[!ENDVAR!]

[!VAR "INMUX124"!]
[!ENDVAR!]

[!VAR "INMUX125"!]
[!ENDVAR!]

[!VAR "INMUX126"!]
[!ENDVAR!]

[!VAR "INMUX127"!]
[!ENDVAR!]

[!VAR "INMUX128"!]
[!ENDVAR!]

[!VAR "INMUX129"!]
[!ENDVAR!]

[!VAR "INMUX130"!]
[!ENDVAR!]

[!VAR "INMUX131"!]
[!ENDVAR!]

[!VAR "INMUX132"!]
[!ENDVAR!]

[!VAR "INMUX133"!]
[!ENDVAR!]

[!VAR "INMUX134"!]
[!ENDVAR!]

[!VAR "INMUX135"!]
[!ENDVAR!]

[!VAR "INMUX136"!]
[!ENDVAR!]

[!VAR "INMUX137"!]
[!ENDVAR!]

[!VAR "INMUX138"!]
[!ENDVAR!]

[!VAR "INMUX139"!]
[!ENDVAR!]

[!VAR "INMUX140"!]
[!ENDVAR!]

[!VAR "INMUX141"!]
[!ENDVAR!]

[!VAR "INMUX142"!]
[!ENDVAR!]

[!VAR "INMUX143"!]
[!ENDVAR!]

[!VAR "INMUX144"!]
SIUL2_EIRQ0_PORT3;1:[!//
[!ENDVAR!]

[!VAR "INMUX145"!]
SIUL2_EIRQ1_PORT6;1:[!//
[!ENDVAR!]

[!VAR "INMUX146"!]
SIUL2_EIRQ2_PORT7;1:[!//
[!ENDVAR!]

[!VAR "INMUX147"!]
SIUL2_EIRQ3_PORT8;1:[!//
[!ENDVAR!]

[!VAR "INMUX148"!]
SIUL2_EIRQ4_PORT14;1:[!//
[!ENDVAR!]

[!VAR "INMUX149"!]
SIUL2_EIRQ5_PORT34;1:[!//
[!ENDVAR!]

[!VAR "INMUX150"!]
SIUL2_EIRQ6_PORT35;1:[!//
[!ENDVAR!]

[!VAR "INMUX151"!]
SIUL2_EIRQ7_PORT37;1:[!//
[!ENDVAR!]

[!VAR "INMUX152"!]
SIUL2_EIRQ8_PORT46;1:[!//
[!ENDVAR!]

[!VAR "INMUX153"!]
SIUL2_EIRQ9_PORT68;1:[!//
[!ENDVAR!]

[!VAR "INMUX154"!]
SIUL2_EIRQ10_PORT74;1:[!//
[!ENDVAR!]

[!VAR "INMUX155"!]
SIUL2_EIRQ11_PORT76;1:[!//
[!ENDVAR!]

[!VAR "INMUX156"!]
SIUL2_EIRQ12_PORT78;1:[!//
[!ENDVAR!]

[!VAR "INMUX157"!]
SIUL2_EIRQ13_PORT95;1:[!//
[!ENDVAR!]

[!VAR "INMUX158"!]
SIUL2_EIRQ14_PORT97;1:[!//
[!ENDVAR!]

[!VAR "INMUX159"!]
SIUL2_EIRQ15_PORT104;1:[!//
[!ENDVAR!]

[!VAR "INMUX160"!]
SIUL2_EIRQ16_PORT11;1:[!//
[!ENDVAR!]

[!VAR "INMUX161"!]
SIUL2_EIRQ17_PORT12;1:[!//
[!ENDVAR!]

[!VAR "INMUX162"!]
SIUL2_EIRQ18_PORT36;1:[!//
[!ENDVAR!]

[!VAR "INMUX163"!]
SIUL2_EIRQ19_PORT44;1:[!//
[!ENDVAR!]

[!VAR "INMUX164"!]
SIUL2_EIRQ20_PORT47;1:[!//
[!ENDVAR!]

[!VAR "INMUX165"!]
SIUL2_EIRQ21_PORT66;1:[!//
[!ENDVAR!]

[!VAR "INMUX166"!]
SIUL2_EIRQ22_PORT70;1:[!//
[!ENDVAR!]

[!VAR "INMUX167"!]
SIUL2_EIRQ23_PORT71;1:[!//
[!ENDVAR!]

[!VAR "INMUX168"!]
[!ENDVAR!]

[!VAR "INMUX169"!]
[!ENDVAR!]

[!VAR "INMUX170"!]
[!ENDVAR!]

[!VAR "INMUX171"!]
[!ENDVAR!]

[!VAR "INMUX172"!]
[!ENDVAR!]

[!VAR "INMUX173"!]
[!ENDVAR!]

[!VAR "INMUX174"!]
[!ENDVAR!]

[!VAR "INMUX175"!]
SIUL2_EIRQ31_PORT163;1:[!//
[!ENDVAR!]

[!VAR "INMUX176"!]
[!ENDVAR!]

[!VAR "INMUX177"!]
[!ENDVAR!]

[!VAR "INMUX178"!]
[!ENDVAR!]

[!VAR "INMUX179"!]
[!ENDVAR!]

[!VAR "INMUX180"!]
[!ENDVAR!]

[!VAR "INMUX181"!]
[!ENDVAR!]

[!VAR "INMUX182"!]
[!ENDVAR!]

[!VAR "INMUX183"!]
[!ENDVAR!]

[!VAR "INMUX184"!]
[!ENDVAR!]

[!VAR "INMUX185"!]
[!ENDVAR!]

[!VAR "INMUX186"!]
[!ENDVAR!]

[!VAR "INMUX187"!]
[!ENDVAR!]

[!VAR "INMUX188"!]
FlexCAN_0_RX_PORT15;1:[!//
FlexCAN_0_RX_PORT17;2:[!//
[!ENDVAR!]

[!VAR "INMUX189"!]
FlexCAN_1_RX_PORT0;1:[!//
FlexCAN_1_RX_PORT35;2:[!//
FlexCAN_1_RX_PORT43;3:[!//
FlexCAN_1_RX_PORT95;4:[!//
FlexCAN_1_RX_PORT157;5:[!//
FlexCAN_1_RX_PORT159;6:[!//
[!ENDVAR!]

[!VAR "INMUX190"!]
FlexCAN_2_RX_PORT73;1:[!//
FlexCAN_2_RX_PORT89;2:[!//
FlexCAN_2_RX_PORT156;3:[!//
FlexCAN_2_RX_PORT165;4:[!//
[!ENDVAR!]

[!VAR "INMUX191"!]
FlexCAN_3_RX_PORT1;1:[!//
FlexCAN_3_RX_PORT36;2:[!//
FlexCAN_3_RX_PORT73;3:[!//
FlexCAN_3_RX_PORT89;4:[!//
FlexCAN_3_RX_PORT159;5:[!//
FlexCAN_3_RX_PORT167;6:[!//
FlexCAN_3_RX_PORT173;7:[!//
[!ENDVAR!]

[!VAR "INMUX192"!]
FlexCAN_4_RX_PORT35;1:[!//
FlexCAN_4_RX_PORT43;2:[!//
FlexCAN_4_RX_PORT47;7:[!//
FlexCAN_4_RX_PORT95;3:[!//
FlexCAN_4_RX_PORT154;4:[!//
FlexCAN_4_RX_PORT157;5:[!//
FlexCAN_4_RX_PORT161;6:[!//
[!ENDVAR!]

[!VAR "INMUX193"!]
FlexCAN_5_RX_PORT64;1:[!//
FlexCAN_5_RX_PORT97;2:[!//
FlexCAN_5_RX_PORT163;3:[!//
[!ENDVAR!]

[!VAR "INMUX194"!]
FlexCAN_6_RX_PORT26;1:[!//
FlexCAN_6_RX_PORT157;2:[!//
[!ENDVAR!]

[!VAR "INMUX195"!]
FlexCAN_7_RX_PORT99;1:[!//
FlexCAN_7_RX_PORT105;2:[!//
[!ENDVAR!]

[!VAR "INMUX196"!]
[!ENDVAR!]

[!VAR "INMUX197"!]
[!ENDVAR!]

[!VAR "INMUX198"!]
[!ENDVAR!]

[!VAR "INMUX199"!]
[!ENDVAR!]

[!VAR "INMUX200"!]
LIN_0_LIN0RX_PORT17;1:[!//
LIN_0_LIN0RX_PORT19;2:[!//
[!ENDVAR!]

[!VAR "INMUX201"!]
LIN_1_LIN1RX_PORT39;1:[!//
[!ENDVAR!]

[!VAR "INMUX202"!]
LIN_2_LIN2RX_PORT11;1:[!//
LIN_2_LIN2RX_PORT41;2:[!//
LIN_2_LIN2RX_PORT165;3:[!//
[!ENDVAR!]

[!VAR "INMUX203"!]
LIN_3_LIN3RX_PORT8;1:[!//
LIN_3_LIN3RX_PORT75;2:[!//
LIN_3_LIN3RX_PORT167;3:[!//
[!ENDVAR!]

[!VAR "INMUX204"!]
LIN_4_LIN4RX_PORT6;1:[!//
LIN_4_LIN4RX_PORT91;2:[!//
[!ENDVAR!]

[!VAR "INMUX205"!]
LIN_5_LIN5RX_PORT4;1:[!//
LIN_5_LIN5RX_PORT93;2:[!//
[!ENDVAR!]

[!VAR "INMUX206"!]
LIN_6_LIN6RX_PORT103;1:[!//
[!ENDVAR!]

[!VAR "INMUX207"!]
LIN_7_LIN7RX_PORT105;1:[!//
[!ENDVAR!]

[!VAR "INMUX208"!]
LIN_8_LIN8RX_PORT111;1:[!//
LIN_8_LIN8RX_PORT129;2:[!//
LIN_8_LIN8RX_PORT163;3:[!//
[!ENDVAR!]

[!VAR "INMUX209"!]
LIN_9_LIN9RX_PORT131;1:[!//
[!ENDVAR!]

[!VAR "INMUX210"!]
LIN_10_LIN10RX_PORT101;1:[!//
[!ENDVAR!]

[!VAR "INMUX211"!]
LIN_11_LIN11RX_PORT64;1:[!//
[!ENDVAR!]

[!VAR "INMUX212"!]
LIN_12_LIN12RX_PORT225;2:[!//
[!ENDVAR!]

[!VAR "INMUX213"!]
LIN_13_LIN13RX_PORT176;2:[!//
[!ENDVAR!]

[!VAR "INMUX214"!]
LIN_14_LIN14RX_PORT172;2:[!//
[!ENDVAR!]

[!VAR "INMUX215"!]
LIN_15_LIN15RX_PORT169;2:[!//
[!ENDVAR!]

[!VAR "INMUX216"!]
[!ENDVAR!]

[!VAR "INMUX217"!]
[!ENDVAR!]

[!VAR "INMUX218"!]
[!ENDVAR!]

[!VAR "INMUX219"!]
[!ENDVAR!]

[!VAR "INMUX220"!]
[!ENDVAR!]

[!VAR "INMUX221"!]
[!ENDVAR!]

[!VAR "INMUX222"!]
[!ENDVAR!]

[!VAR "INMUX223"!]
[!ENDVAR!]

[!VAR "INMUX224"!]
FlexRay_FR_A_RX_PORT67;1:[!//
[!ENDVAR!]

[!VAR "INMUX225"!]
FlexRay_FR_B_RX_PORT69;1:[!//
[!ENDVAR!]

[!VAR "INMUX226"!]
[!ENDVAR!]

[!VAR "INMUX227"!]
[!ENDVAR!]

[!VAR "INMUX228"!]
[!ENDVAR!]

[!VAR "INMUX229"!]
[!ENDVAR!]

[!VAR "INMUX230"!]
[!ENDVAR!]

[!VAR "INMUX231"!]
[!ENDVAR!]

[!VAR "INMUX232"!]
[!ENDVAR!]

[!VAR "INMUX233"!]
[!ENDVAR!]

[!VAR "INMUX234"!]
[!ENDVAR!]

[!VAR "INMUX235"!]
[!ENDVAR!]

[!VAR "INMUX236"!]
[!ENDVAR!]

[!VAR "INMUX237"!]
[!ENDVAR!]

[!VAR "INMUX238"!]
[!ENDVAR!]

[!VAR "INMUX239"!]
[!ENDVAR!]

[!VAR "INMUX240"!]
[!ENDVAR!]

[!VAR "INMUX241"!]
[!ENDVAR!]

[!VAR "INMUX242"!]
[!ENDVAR!]

[!VAR "INMUX243"!]
[!ENDVAR!]

[!VAR "INMUX244"!]
[!ENDVAR!]

[!VAR "INMUX245"!]
[!ENDVAR!]

[!VAR "INMUX246"!]
[!ENDVAR!]

[!VAR "INMUX247"!]
[!ENDVAR!]

[!VAR "INMUX248"!]
[!ENDVAR!]

[!VAR "INMUX249"!]
[!ENDVAR!]

[!VAR "INMUX250"!]
[!ENDVAR!]

[!VAR "INMUX251"!]
[!ENDVAR!]

[!VAR "INMUX252"!]
[!ENDVAR!]

[!VAR "INMUX253"!]
[!ENDVAR!]

[!VAR "INMUX254"!]
[!ENDVAR!]

[!VAR "INMUX255"!]
[!ENDVAR!]

[!VAR "INMUX256"!]
[!ENDVAR!]

[!VAR "INMUX257"!]
[!ENDVAR!]

[!VAR "INMUX258"!]
[!ENDVAR!]

[!VAR "INMUX259"!]
[!ENDVAR!]

[!VAR "INMUX260"!]
[!ENDVAR!]

[!VAR "INMUX261"!]
[!ENDVAR!]

[!VAR "INMUX262"!]
[!ENDVAR!]

[!VAR "INMUX263"!]
[!ENDVAR!]

[!VAR "INMUX264"!]
[!ENDVAR!]

[!VAR "INMUX265"!]
IIC_0_SCL0_IN_PORT11;1:[!//
IIC_0_SCL0_IN_OUT_PORT11;1:[!//
IIC_0_SCL0_IN_PORT19;2:[!//
IIC_0_SCL0_IN_OUT_PORT19;2:[!//
IIC_0_SCL0_IN_PORT225;3:[!//
IIC_0_SCL0_IN_OUT_PORT225;3:[!//
[!ENDVAR!]

[!VAR "INMUX266"!]
IIC_0_SDA0_IN_PORT10;1:[!//
IIC_0_SDA0_IN_OUT_PORT10;1:[!//
IIC_0_SDA0_IN_PORT18;2:[!//
IIC_0_SDA0_IN_OUT_PORT18;2:[!//
IIC_0_SDA0_IN_PORT224;3:[!//
IIC_0_SDA0_IN_OUT_PORT224;3:[!//
[!ENDVAR!]

[!VAR "INMUX267"!]
IIC_1_SCL1_IN_PORT64;1:[!//
IIC_1_SCL1_IN_OUT_PORT64;1:[!//
IIC_1_SCL1_IN_PORT129;2:[!//
IIC_1_SCL1_IN_OUT_PORT129;2:[!//
[!ENDVAR!]

[!VAR "INMUX268"!]
IIC_1_SDA1_IN_PORT65;1:[!//
IIC_1_SDA1_IN_OUT_PORT65;1:[!//
IIC_1_SDA1_IN_PORT128;2:[!//
IIC_1_SDA1_IN_OUT_PORT128;2:[!//
[!ENDVAR!]

[!VAR "INMUX269"!]
IIC_2_SCL2_IN_PORT73;1:[!//
IIC_2_SCL2_IN_OUT_PORT73;1:[!//
IIC_2_SCL2_IN_PORT131;2:[!//
IIC_2_SCL2_IN_OUT_PORT131;2:[!//
[!ENDVAR!]

[!VAR "INMUX270"!]
IIC_2_SDA2_IN_PORT72;1:[!//
IIC_2_SDA2_IN_OUT_PORT72;1:[!//
IIC_2_SDA2_IN_PORT130;2:[!//
IIC_2_SDA2_IN_OUT_PORT130;2:[!//
[!ENDVAR!]

[!VAR "INMUX271"!]
IIC_3_SCL3_IN_PORT75;1:[!//
IIC_3_SCL3_IN_OUT_PORT75;1:[!//
IIC_3_SCL3_IN_PORT116;2:[!//
IIC_3_SCL3_IN_OUT_PORT116;2:[!//
[!ENDVAR!]

[!VAR "INMUX272"!]
IIC_3_SDA3_IN_PORT74;1:[!//
IIC_3_SDA3_IN_OUT_PORT74;1:[!//
IIC_3_SDA3_IN_PORT117;2:[!//
IIC_3_SDA3_IN_OUT_PORT117;2:[!//
[!ENDVAR!]

[!VAR "INMUX273"!]
[!ENDVAR!]

[!VAR "INMUX274"!]
[!ENDVAR!]

[!VAR "INMUX275"!]
[!ENDVAR!]

[!VAR "INMUX276"!]
[!ENDVAR!]

[!VAR "INMUX277"!]
[!ENDVAR!]

[!VAR "INMUX278"!]
[!ENDVAR!]

[!VAR "INMUX279"!]
[!ENDVAR!]

[!VAR "INMUX280"!]
[!ENDVAR!]

[!VAR "INMUX281"!]
[!ENDVAR!]

[!VAR "INMUX282"!]
[!ENDVAR!]

[!VAR "INMUX283"!]
[!ENDVAR!]

[!VAR "INMUX284"!]
[!ENDVAR!]

[!VAR "INMUX285"!]
[!ENDVAR!]

[!VAR "INMUX286"!]
[!ENDVAR!]

[!VAR "INMUX287"!]
[!ENDVAR!]

[!VAR "INMUX288"!]
DSPI_0_dSIN_PORT12;1:[!//
DSPI_0_dSIN_PORT259;2:[!//
[!ENDVAR!]

[!VAR "INMUX289"!]
DSPI_0_dSCLK_IN_PORT14;1:[!//
DSPI_0_dSCLK_IN_OUT_PORT14;1:[!//
DSPI_0_dSCLK_IN_PORT15;2:[!//
DSPI_0_dSCLK_IN_OUT_PORT15;2:[!//
DSPI_0_dSCLK_IN_PORT258;3:[!//
DSPI_0_dSCLK_IN_OUT_PORT258;3:[!//
[!ENDVAR!]

[!VAR "INMUX290"!]
DSPI_0_dSS_PORT14;1:[!//
DSPI_0_dSS_PORT15;2:[!//
DSPI_0_dSS_PORT27;3:[!//
DSPI_0_dSS_PORT257;4:[!//
[!ENDVAR!]

[!VAR "INMUX291"!]
DSPI_1_dSIN_PORT10;1:[!//
DSPI_1_dSIN_PORT36;2:[!//
DSPI_1_dSIN_PORT66;3:[!//
DSPI_1_dSIN_PORT112;4:[!//
[!ENDVAR!]

[!VAR "INMUX292"!]
DSPI_1_dSCLK_IN_PORT34;1:[!//
DSPI_1_dSCLK_IN_OUT_PORT34;1:[!//
DSPI_1_dSCLK_IN_PORT68;2:[!//
DSPI_1_dSCLK_IN_OUT_PORT68;2:[!//
DSPI_1_dSCLK_IN_PORT114;3:[!//
DSPI_1_dSCLK_IN_OUT_PORT114;3:[!//
[!ENDVAR!]

[!VAR "INMUX293"!]
DSPI_1_dSS_PORT4;1:[!//
DSPI_1_dSS_PORT35;2:[!//
DSPI_1_dSS_PORT61;3:[!//
DSPI_1_dSS_PORT69;4:[!//
DSPI_1_dSS_PORT115;5:[!//
[!ENDVAR!]

[!VAR "INMUX294"!]
DSPI_2_dSIN_PORT44;1:[!//
DSPI_2_dSIN_PORT76;2:[!//
[!ENDVAR!]

[!VAR "INMUX295"!]
DSPI_2_dSCLK_IN_PORT46;1:[!//
DSPI_2_dSCLK_IN_OUT_PORT46;1:[!//
DSPI_2_dSCLK_IN_PORT78;2:[!//
DSPI_2_dSCLK_IN_OUT_PORT78;2:[!//
DSPI_2_dSCLK_IN_PORT105;3:[!//
DSPI_2_dSCLK_IN_OUT_PORT105;3:[!//
[!ENDVAR!]

[!VAR "INMUX296"!]
DSPI_2_dSS_PORT47;1:[!//
DSPI_2_dSS_PORT79;2:[!//
DSPI_2_dSS_PORT82;3:[!//
DSPI_2_dSS_PORT104;4:[!//
DSPI_2_dSS_PORT140;5:[!//
[!ENDVAR!]

[!VAR "INMUX297"!]
DSPI_3_dSIN_PORT101;1:[!//
DSPI_3_dSIN_PORT139;2:[!//
[!ENDVAR!]

[!VAR "INMUX298"!]
DSPI_3_dSCLK_IN_PORT100;1:[!//
DSPI_3_dSCLK_IN_OUT_PORT100;1:[!//
DSPI_3_dSCLK_IN_PORT124;2:[!//
DSPI_3_dSCLK_IN_OUT_PORT124;2:[!//
[!ENDVAR!]

[!VAR "INMUX299"!]
DSPI_3_dSS_PORT99;1:[!//
DSPI_3_dSS_PORT125;2:[!//
DSPI_3_dSS_PORT140;3:[!//
[!ENDVAR!]

[!VAR "INMUX300"!]
SPI_0_SIN_0_PORT106;1:[!//
SPI_0_SIN_0_PORT142;2:[!//
SPI_0_SIN_0_PORT169;3:[!//
[!ENDVAR!]

[!VAR "INMUX301"!]
SPI_0_SCLK_0_IN_PORT87;1:[!//
SPI_0_SCLK_0_IN_OUT_PORT87;1:[!//
SPI_0_SCLK_0_IN_PORT109;2:[!//
SPI_0_SCLK_0_IN_OUT_PORT109;2:[!//
SPI_0_SCLK_0_IN_PORT126;3:[!//
SPI_0_SCLK_0_IN_OUT_PORT126;3:[!//
SPI_0_SCLK_0_IN_PORT133;4:[!//
SPI_0_SCLK_0_IN_OUT_PORT133;4:[!//
SPI_0_SCLK_0_IN_PORT171;5:[!//
SPI_0_SCLK_0_IN_OUT_PORT171;5:[!//
[!ENDVAR!]

[!VAR "INMUX302"!]
SPI_0_SS_0_PORT107;1:[!//
SPI_0_SS_0_PORT123;2:[!//
SPI_0_SS_0_PORT134;3:[!//
SPI_0_SS_0_PORT143;4:[!//
SPI_0_SS_0_PORT172;5:[!//
[!ENDVAR!]

[!VAR "INMUX303"!]
SPI_1_SIN_1_PORT145;1:[!//
SPI_1_SIN_1_PORT175;2:[!//
[!ENDVAR!]

[!VAR "INMUX304"!]
SPI_1_SCLK_1_IN_PORT148;1:[!//
SPI_1_SCLK_1_IN_OUT_PORT148;1:[!//
SPI_1_SCLK_1_IN_PORT173;2:[!//
SPI_1_SCLK_1_IN_OUT_PORT173;2:[!//
[!ENDVAR!]

[!VAR "INMUX305"!]
SPI_1_SS_1_PORT134;1:[!//
SPI_1_SS_1_PORT146;2:[!//
SPI_1_SS_1_PORT174;3:[!//
[!ENDVAR!]

[!VAR "INMUX306"!]
SPI_2_SIN_2_PORT110;1:[!//
SPI_2_SIN_2_PORT255;2:[!//
[!ENDVAR!]

[!VAR "INMUX307"!]
SPI_2_SCLK_2_IN_PORT79;1:[!//
SPI_2_SCLK_2_IN_OUT_PORT79;1:[!//
SPI_2_SCLK_2_IN_PORT254;2:[!//
SPI_2_SCLK_2_IN_OUT_PORT254;2:[!//
[!ENDVAR!]

[!VAR "INMUX308"!]
SPI_2_SS_2_PORT107;1:[!//
SPI_2_SS_2_PORT134;2:[!//
SPI_2_SS_2_PORT146;3:[!//
SPI_2_SS_2_PORT252;4:[!//
[!ENDVAR!]

[!VAR "INMUX309"!]
SPI_3_SIN_3_PORT117;1:[!//
SPI_3_SIN_3_PORT175;2:[!//
[!ENDVAR!]

[!VAR "INMUX310"!]
SPI_3_SCLK_3_IN_PORT118;1:[!//
SPI_3_SCLK_3_IN_OUT_PORT118;1:[!//
[!ENDVAR!]

[!VAR "INMUX311"!]
SPI_3_SS_3_PORT119;1:[!//
SPI_3_SS_3_PORT146;2:[!//
[!ENDVAR!]

[!VAR "INMUX312"!]
[!ENDVAR!]

[!VAR "INMUX313"!]
[!ENDVAR!]

[!VAR "INMUX314"!]
[!ENDVAR!]

[!VAR "INMUX315"!]
[!ENDVAR!]

[!VAR "INMUX316"!]
[!ENDVAR!]

[!VAR "INMUX317"!]
[!ENDVAR!]

[!VAR "INMUX318"!]
[!ENDVAR!]

[!VAR "INMUX319"!]
[!ENDVAR!]

[!VAR "INMUX320"!]
[!ENDVAR!]

[!VAR "INMUX321"!]
[!ENDVAR!]

[!VAR "INMUX322"!]
[!ENDVAR!]

[!VAR "INMUX323"!]
[!ENDVAR!]

[!VAR "INMUX324"!]
[!ENDVAR!]

[!VAR "INMUX325"!]
[!ENDVAR!]

[!VAR "INMUX326"!]
[!ENDVAR!]

[!VAR "INMUX327"!]
[!ENDVAR!]

[!VAR "INMUX328"!]
[!ENDVAR!]

[!VAR "INMUX329"!]
ENET0_ENET0_TMR0_IN_PORT61;1:[!//
ENET0_ENET0_TMR0_IN_OUT_PORT61;1:[!//
[!ENDVAR!]

[!VAR "INMUX330"!]
ENET0_ENET0_TMR1_IN_PORT139;1:[!//
ENET0_ENET0_TMR1_IN_OUT_PORT139;1:[!//
[!ENDVAR!]

[!VAR "INMUX331"!]
ENET0_ENET0_TMR2_IN_PORT195;1:[!//
ENET0_ENET0_TMR2_IN_OUT_PORT195;1:[!//
[!ENDVAR!]

[!VAR "INMUX332"!]
[!ENDVAR!]

[!VAR "INMUX333"!]
[!ENDVAR!]

[!VAR "INMUX334"!]
[!ENDVAR!]

[!VAR "INMUX335"!]
[!ENDVAR!]

[!VAR "INMUX336"!]
[!ENDVAR!]

[!VAR "INMUX337"!]
[!ENDVAR!]

[!VAR "INMUX338"!]
[!ENDVAR!]

[!VAR "INMUX339"!]
[!ENDVAR!]

[!VAR "INMUX340"!]
[!ENDVAR!]

[!VAR "INMUX341"!]
[!ENDVAR!]

[!VAR "INMUX342"!]
[!ENDVAR!]

[!VAR "INMUX343"!]
[!ENDVAR!]

[!VAR "INMUX344"!]
[!ENDVAR!]

[!VAR "INMUX345"!]
[!ENDVAR!]

[!VAR "INMUX346"!]
[!ENDVAR!]

[!VAR "INMUX347"!]
[!ENDVAR!]

[!VAR "INMUX348"!]
[!ENDVAR!]

[!VAR "INMUX349"!]
[!ENDVAR!]

[!VAR "INMUX350"!]
[!ENDVAR!]

[!VAR "INMUX351"!]
[!ENDVAR!]

[!VAR "INMUX352"!]
[!ENDVAR!]

[!VAR "INMUX353"!]
[!ENDVAR!]

[!VAR "INMUX354"!]
[!ENDVAR!]

[!VAR "INMUX355"!]
[!ENDVAR!]

[!VAR "INMUX356"!]
[!ENDVAR!]

[!VAR "INMUX357"!]
[!ENDVAR!]

[!VAR "INMUX358"!]
[!ENDVAR!]

[!VAR "INMUX359"!]
[!ENDVAR!]

[!VAR "INMUX360"!]
[!ENDVAR!]

[!VAR "INMUX361"!]
[!ENDVAR!]

[!VAR "INMUX362"!]
[!ENDVAR!]

[!VAR "INMUX363"!]
[!ENDVAR!]

[!VAR "INMUX364"!]
[!ENDVAR!]

[!VAR "INMUX365"!]
[!ENDVAR!]

[!VAR "INMUX366"!]
[!ENDVAR!]

[!VAR "INMUX367"!]
[!ENDVAR!]

[!VAR "INMUX368"!]
[!ENDVAR!]

[!VAR "INMUX369"!]
[!ENDVAR!]

[!VAR "INMUX370"!]
[!ENDVAR!]

[!VAR "INMUX371"!]
[!ENDVAR!]

[!VAR "INMUX372"!]
[!ENDVAR!]

[!VAR "INMUX373"!]
[!ENDVAR!]

[!VAR "INMUX374"!]
[!ENDVAR!]

[!VAR "INMUX375"!]
[!ENDVAR!]

[!VAR "INMUX376"!]
[!ENDVAR!]

[!VAR "INMUX377"!]
[!ENDVAR!]

[!VAR "INMUX378"!]
[!ENDVAR!]

[!VAR "INMUX379"!]
[!ENDVAR!]

[!VAR "INMUX380"!]
[!ENDVAR!]

[!VAR "INMUX381"!]
[!ENDVAR!]

[!VAR "INMUX382"!]
[!ENDVAR!]

[!VAR "INMUX383"!]
[!ENDVAR!]

[!VAR "INMUX384"!]
[!ENDVAR!]

[!VAR "INMUX385"!]
[!ENDVAR!]

[!VAR "INMUX386"!]
[!ENDVAR!]

[!VAR "INMUX387"!]
[!ENDVAR!]

[!VAR "INMUX388"!]
[!ENDVAR!]

[!VAR "INMUX389"!]
[!ENDVAR!]

[!VAR "INMUX390"!]
[!ENDVAR!]

[!VAR "INMUX391"!]
[!ENDVAR!]

[!VAR "INMUX392"!]
[!ENDVAR!]

[!VAR "INMUX393"!]
[!ENDVAR!]

[!VAR "INMUX394"!]
[!ENDVAR!]

[!VAR "INMUX395"!]
[!ENDVAR!]

[!VAR "INMUX396"!]
[!ENDVAR!]

[!VAR "INMUX397"!]
[!ENDVAR!]

[!VAR "INMUX398"!]
[!ENDVAR!]

[!VAR "INMUX399"!]
[!ENDVAR!]

[!VAR "INMUX400"!]
[!ENDVAR!]

[!VAR "INMUX401"!]
[!ENDVAR!]

[!VAR "INMUX402"!]
[!ENDVAR!]

[!VAR "INMUX403"!]
[!ENDVAR!]

[!VAR "INMUX404"!]
[!ENDVAR!]

[!VAR "INMUX405"!]
[!ENDVAR!]

[!VAR "INMUX406"!]
[!ENDVAR!]

[!VAR "INMUX407"!]
[!ENDVAR!]

[!VAR "INMUX408"!]
[!ENDVAR!]

[!VAR "INMUX409"!]
[!ENDVAR!]

[!VAR "INMUX410"!]
[!ENDVAR!]

[!VAR "INMUX411"!]
[!ENDVAR!]

[!VAR "INMUX412"!]
[!ENDVAR!]

[!VAR "INMUX413"!]
[!ENDVAR!]

[!VAR "INMUX414"!]
[!ENDVAR!]

[!VAR "INMUX415"!]
[!ENDVAR!]

[!VAR "INMUX416"!]
[!ENDVAR!]

[!VAR "INMUX417"!]
[!ENDVAR!]

[!VAR "INMUX418"!]
[!ENDVAR!]

[!VAR "INMUX419"!]
[!ENDVAR!]

[!VAR "INMUX420"!]
[!ENDVAR!]

[!VAR "INMUX421"!]
[!ENDVAR!]

[!VAR "INMUX422"!]
[!ENDVAR!]

[!VAR "INMUX423"!]
[!ENDVAR!]

[!VAR "INMUX424"!]
[!ENDVAR!]

[!VAR "INMUX425"!]
[!ENDVAR!]

[!VAR "INMUX426"!]
[!ENDVAR!]

[!VAR "INMUX427"!]
[!ENDVAR!]

[!VAR "INMUX428"!]
[!ENDVAR!]

[!VAR "INMUX429"!]
[!ENDVAR!]

[!VAR "INMUX430"!]
[!ENDVAR!]

[!VAR "INMUX431"!]
[!ENDVAR!]

[!VAR "INMUX432"!]
[!ENDVAR!]

[!VAR "INMUX433"!]
[!ENDVAR!]

[!VAR "INMUX434"!]
[!ENDVAR!]

[!VAR "INMUX435"!]
[!ENDVAR!]

[!VAR "INMUX436"!]
[!ENDVAR!]

[!VAR "INMUX437"!]
[!ENDVAR!]

[!VAR "INMUX438"!]
[!ENDVAR!]

[!VAR "INMUX439"!]
[!ENDVAR!]

[!VAR "INMUX440"!]
[!ENDVAR!]

[!VAR "INMUX441"!]
[!ENDVAR!]

[!VAR "INMUX442"!]
[!ENDVAR!]

[!VAR "INMUX443"!]
[!ENDVAR!]

[!VAR "INMUX444"!]
[!ENDVAR!]

[!VAR "INMUX445"!]
[!ENDVAR!]

[!VAR "INMUX446"!]
[!ENDVAR!]

[!VAR "INMUX447"!]
[!ENDVAR!]

[!VAR "INMUX448"!]
ENET0_MII_0_RX_CLK_PORT3;1:[!//
[!ENDVAR!]

[!VAR "INMUX449"!]
ENET0_MII_RMII_0_TX_CLK_IN_PORT97;1:[!//
ENET0_MII_RMII_0_TX_CLK_IN_OUT_PORT97;1:[!//
[!ENDVAR!]

[!VAR "INMUX450"!]
ENET0_MII_RMII_0_MDIO_IN_PORT94;1:[!//
ENET0_MII_RMII_0_MDIO_IN_OUT_PORT94;1:[!//
[!ENDVAR!]

[!VAR "INMUX451"!]
ENET0_MII_RMII_0_RXD_0_PORT9;1:[!//
[!ENDVAR!]

[!VAR "INMUX452"!]
ENET0_MII_RMII_0_RXD_1_PORT8;1:[!//
[!ENDVAR!]

[!VAR "INMUX453"!]
ENET0_MII_0_RXD_2_PORT7;1:[!//
[!ENDVAR!]

[!VAR "INMUX454"!]
ENET0_MII_0_RXD_3_PORT77;1:[!//
[!ENDVAR!]

[!VAR "INMUX455"!]
ENET0_MII_RMII_0_RX_ER_PORT11;1:[!//
[!ENDVAR!]

[!VAR "INMUX456"!]
ENET0_MII_0_COL_PORT10;1:[!//
[!ENDVAR!]

[!VAR "INMUX457"!]
ENET0_MII_RMII_0_RX_DV_PORT95;1:[!//
[!ENDVAR!]

[!VAR "INMUX458"!]
ENET0_MII_0_CRS_PORT76;1:[!//
[!ENDVAR!]

[!VAR "INMUX459"!]
[!ENDVAR!]

[!VAR "INMUX460"!]
[!ENDVAR!]

[!VAR "INMUX461"!]
[!ENDVAR!]

[!VAR "INMUX462"!]
[!ENDVAR!]

[!VAR "INMUX463"!]
[!ENDVAR!]

[!VAR "INMUX464"!]
[!ENDVAR!]

[!VAR "INMUX465"!]
[!ENDVAR!]

[!VAR "INMUX466"!]
[!ENDVAR!]

[!VAR "INMUX467"!]
[!ENDVAR!]

[!VAR "INMUX468"!]
[!ENDVAR!]

[!VAR "INMUX469"!]
[!ENDVAR!]

[!VAR "INMUX470"!]
[!ENDVAR!]

[!VAR "INMUX471"!]
[!ENDVAR!]

[!VAR "INMUX472"!]
[!ENDVAR!]

[!VAR "INMUX473"!]
[!ENDVAR!]

[!VAR "INMUX474"!]
[!ENDVAR!]

[!VAR "INMUX475"!]
[!ENDVAR!]

[!VAR "INMUX476"!]
[!ENDVAR!]

[!VAR "INMUX477"!]
[!ENDVAR!]

[!VAR "INMUX478"!]
[!ENDVAR!]

[!VAR "INMUX479"!]
[!ENDVAR!]

[!VAR "INMUX480"!]
[!ENDVAR!]

[!VAR "INMUX481"!]
[!ENDVAR!]

[!VAR "INMUX482"!]
[!ENDVAR!]

[!VAR "INMUX483"!]
[!ENDVAR!]

[!VAR "INMUX484"!]
[!ENDVAR!]

[!VAR "INMUX485"!]
[!ENDVAR!]

[!VAR "INMUX486"!]
[!ENDVAR!]

[!VAR "INMUX487"!]
[!ENDVAR!]

[!VAR "INMUX488"!]
SAI0_SAI0_BCLK_IN_PORT81;1:[!//
SAI0_SAI0_BCLK_IN_OUT_PORT81;1:[!//
[!ENDVAR!]

[!VAR "INMUX489"!]
SAI0_SAI0_MCLK_IN_PORT80;1:[!//
SAI0_SAI0_MCLK_IN_OUT_PORT80;1:[!//
SAI0_SAI0_MCLK_IN_PORT206;3:[!//
SAI0_SAI0_MCLK_IN_OUT_PORT206;3:[!//
[!ENDVAR!]

[!VAR "INMUX490"!]
SAI0_SAI0_SYNC_IN_PORT26;1:[!//
SAI0_SAI0_SYNC_IN_OUT_PORT26;1:[!//
[!ENDVAR!]

[!VAR "INMUX491"!]
SAI0_SAI0_D0_IN_PORT85;1:[!//
SAI0_SAI0_D0_IN_OUT_PORT85;1:[!//
SAI0_SAI0_D0_IN_PORT177;2:[!//
SAI0_SAI0_D0_IN_OUT_PORT177;2:[!//
[!ENDVAR!]

[!VAR "INMUX492"!]
SAI0_SAI0_D1_IN_PORT84;1:[!//
SAI0_SAI0_D1_IN_OUT_PORT84;1:[!//
SAI0_SAI0_D1_IN_PORT195;3:[!//
SAI0_SAI0_D1_IN_OUT_PORT195;3:[!//
[!ENDVAR!]

[!VAR "INMUX493"!]
SAI0_SAI0_D2_IN_PORT83;1:[!//
SAI0_SAI0_D2_IN_OUT_PORT83;1:[!//
SAI0_SAI0_D2_IN_PORT196;3:[!//
SAI0_SAI0_D2_IN_OUT_PORT196;3:[!//
[!ENDVAR!]

[!VAR "INMUX494"!]
SAI0_SAI0_D3_IN_PORT82;1:[!//
SAI0_SAI0_D3_IN_OUT_PORT82;1:[!//
SAI0_SAI0_D3_IN_PORT197;3:[!//
SAI0_SAI0_D3_IN_OUT_PORT197;3:[!//
[!ENDVAR!]

[!VAR "INMUX495"!]
SAI1_SAI1_BCLK_IN_PORT147;1:[!//
SAI1_SAI1_BCLK_IN_OUT_PORT147;1:[!//
[!ENDVAR!]

[!VAR "INMUX496"!]
SAI1_SAI1_MCLK_IN_PORT87;1:[!//
SAI1_SAI1_MCLK_IN_OUT_PORT87;1:[!//
[!ENDVAR!]

[!VAR "INMUX497"!]
SAI1_SAI1_SYNC_IN_PORT86;1:[!//
SAI1_SAI1_SYNC_IN_OUT_PORT86;1:[!//
[!ENDVAR!]

[!VAR "INMUX498"!]
SAI1_SAI1_D0_IN_PORT146;1:[!//
SAI1_SAI1_D0_IN_OUT_PORT146;1:[!//
[!ENDVAR!]

[!VAR "INMUX499"!]
[!ENDVAR!]

[!VAR "INMUX500"!]
[!ENDVAR!]

[!VAR "INMUX501"!]
FCCU_EIN_ERR_PORT126;1:[!//
FCCU_EIN_ERR_PORT148;2:[!//
[!ENDVAR!]

[!VAR "INMUX502"!]
SAI2_SAI2_BCLK_IN_PORT145;1:[!//
SAI2_SAI2_BCLK_IN_OUT_PORT145;1:[!//
SAI2_SAI2_BCLK_IN_PORT150;2:[!//
SAI2_SAI2_BCLK_IN_OUT_PORT150;2:[!//
[!ENDVAR!]

[!VAR "INMUX503"!]
SAI2_SAI2_MCLK_IN_PORT143;2:[!//
SAI2_SAI2_MCLK_IN_OUT_PORT143;2:[!//
SAI2_SAI2_MCLK_IN_PORT151;1:[!//
SAI2_SAI2_MCLK_IN_OUT_PORT151;1:[!//
[!ENDVAR!]

[!VAR "INMUX504"!]
SAI2_SAI2_SYNC_IN_PORT144;2:[!//
SAI2_SAI2_SYNC_IN_OUT_PORT144;2:[!//
SAI2_SAI2_SYNC_IN_PORT152;1:[!//
SAI2_SAI2_SYNC_IN_OUT_PORT152;1:[!//
[!ENDVAR!]

[!VAR "INMUX505"!]
SAI2_SAI2_D0_IN_PORT142;2:[!//
SAI2_SAI2_D0_IN_OUT_PORT142;2:[!//
SAI2_SAI2_D0_IN_PORT149;1:[!//
SAI2_SAI2_D0_IN_OUT_PORT149;1:[!//
[!ENDVAR!]

[!VAR "INMUX506"!]
GLITCH_FILTER0_INP_PORT12;1:[!//
GLITCH_FILTER0_INP_PORT13;3:[!//
GLITCH_FILTER0_INP_PORT82;5:[!//
GLITCH_FILTER0_INP_PORT128;2:[!//
GLITCH_FILTER0_INP_PORT129;4:[!//
[!ENDVAR!]

[!VAR "INMUX507"!]
GLITCH_FILTER1_INP_PORT16;1:[!//
GLITCH_FILTER1_INP_PORT17;4:[!//
GLITCH_FILTER1_INP_PORT18;2:[!//
GLITCH_FILTER1_INP_PORT19;5:[!//
GLITCH_FILTER1_INP_PORT83;7:[!//
GLITCH_FILTER1_INP_PORT130;3:[!//
GLITCH_FILTER1_INP_PORT131;6:[!//
[!ENDVAR!]

[!VAR "INMUX508"!]
GLITCH_FILTER2_INP_PORT38;1:[!//
GLITCH_FILTER2_INP_PORT39;4:[!//
GLITCH_FILTER2_INP_PORT84;7:[!//
GLITCH_FILTER2_INP_PORT132;2:[!//
GLITCH_FILTER2_INP_PORT133;5:[!//
GLITCH_FILTER2_INP_PORT169;6:[!//
GLITCH_FILTER2_INP_PORT260;3:[!//
[!ENDVAR!]

[!VAR "INMUX509"!]
GLITCH_FILTER3_INP_PORT36;5:[!//
GLITCH_FILTER3_INP_PORT74;1:[!//
GLITCH_FILTER3_INP_PORT85;9:[!//
GLITCH_FILTER3_INP_PORT103;2:[!//
GLITCH_FILTER3_INP_PORT106;6:[!//
GLITCH_FILTER3_INP_PORT134;3:[!//
GLITCH_FILTER3_INP_PORT135;7:[!//
GLITCH_FILTER3_INP_PORT170;4:[!//
GLITCH_FILTER3_INP_PORT171;8:[!//
[!ENDVAR!]


[!VAR "CHECK_1"!]

/*  Mode PORT_GPIO_MODE: */
{
/* Pads   0 ...  15 : PORT0_GPIO |
PORT1_GPIO |
PORT2_GPIO |
PORT3_GPIO |
PORT4_GPIO |
PORT5_GPIO |
PORT6_GPIO |
PORT7_GPIO |
PORT8_GPIO |
PORT9_GPIO |
PORT10_GPIO |
PORT11_GPIO |
PORT12_GPIO |
PORT13_GPIO |
PORT14_GPIO |
PORT15_GPIO */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_GPIO |
PORT17_GPIO |
PORT26_GPIO */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(10)
          ),
/* Pads  32 ...  47 : PORT32_GPIO |
PORT33_GPIO |
PORT37_GPIO |
PORT42_GPIO |
PORT43_GPIO */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(5) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11)
          ),
/* Pads  48 ...  63 : PORT61_GPIO */
  (uint16)( SHL_PAD_U16(13)
          ),
/* Pads  64 ...  79 : PORT66_GPIO |
PORT67_GPIO |
PORT72_GPIO |
PORT73_GPIO |
PORT77_GPIO |
PORT79_GPIO */
  (uint16)( SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(13) |
SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT80_GPIO |
PORT85_GPIO |
PORT88_GPIO |
PORT89_GPIO |
PORT90_GPIO |
PORT94_GPIO |
PORT95_GPIO */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(5) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT96_GPIO |
PORT97_GPIO |
PORT98_GPIO |
PORT99_GPIO |
PORT102_GPIO |
PORT103_GPIO |
PORT107_GPIO |
PORT108_GPIO |
PORT109_GPIO |
PORT110_GPIO |
PORT111_GPIO */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 112 ... 127 : PORT112_GPIO |
PORT113_GPIO |
PORT114_GPIO |
PORT121_GPIO |
PORT122_GPIO |
PORT124_GPIO */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(12)
          ),
/* Pads 128 ... 143 : PORT128_GPIO |
PORT129_GPIO |
PORT130_GPIO |
PORT131_GPIO |
PORT142_GPIO */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(14)
          ),
/* Pads 144 ... 159 : PORT144_GPIO |
PORT145_GPIO |
PORT146_GPIO |
PORT157_GPIO |
PORT158_GPIO */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14)
          )
}
,
/*  Mode PORT_ALT1_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_EMIOS0_E0UC_0_X_OUT |
PORT1_EMIOS0_E0UC_1_G_OUT |
PORT2_EMIOS0_E0UC_2_G_OUT |
PORT3_EMIOS0_E0UC_3_G_OUT |
PORT4_EMIOS0_E0UC_4_G_OUT |
PORT5_EMIOS0_E0UC_5_G_OUT |
PORT6_EMIOS0_E0UC_6_G_OUT |
PORT7_EMIOS0_E0UC_7_G_OUT |
PORT8_EMIOS0_E0UC_8_X_OUT |
PORT9_EMIOS0_E0UC_9_H_OUT |
PORT10_EMIOS0_E0UC_10_H_OUT |
PORT11_EMIOS0_E0UC_11_H_OUT |
PORT12_EMIOS0_E0UC_28_Y_OUT |
PORT13_DSPI_0_dSOUT |
PORT14_DSPI_0_dSCLK_OUT |
PORT15_DSPI_0_dCS0 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_FlexCAN_0_TX |
PORT17_EMIOS0_E0UC_31_Y_OUT |
PORT26_DSPI_1_dSOUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(10)
          ),
/* Pads  32 ...  47 : PORT32_DCI_TDI |
PORT33_DCI_TDO |
PORT37_DSPI_1_dSOUT |
PORT42_FlexCAN_1_TX |
PORT43_ADC_0_ADC0_MA_2 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(5) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11)
          ),
/* Pads  48 ...  63 : PORT61_DSPI_1_dCS0 */
  (uint16)( SHL_PAD_U16(13)
          ),
/* Pads  64 ...  79 : PORT66_EMIOS0_E0UC_18_Y_OUT |
PORT67_EMIOS0_E0UC_19_Y_OUT |
PORT72_FlexCAN_2_TX |
PORT73_EMIOS0_E0UC_23_X_OUT |
PORT77_DSPI_2_dSOUT |
PORT79_DSPI_2_dCS0 */
  (uint16)( SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(13) |
SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT80_EMIOS0_E0UC_10_H_OUT |
PORT85_EMIOS0_E0UC_22_X_OUT |
PORT88_FlexCAN_3_TX |
PORT89_EMIOS1_E1UC_1_H_OUT |
PORT90_DSPI_0_dCS1 |
PORT94_FlexCAN_4_TX |
PORT95_EMIOS1_E1UC_4_H_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(5) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT96_FlexCAN_5_TX |
PORT97_EMIOS1_E1UC_24_X_OUT |
PORT98_EMIOS1_E1UC_11_H_OUT |
PORT99_EMIOS1_E1UC_12_H_OUT |
PORT102_EMIOS1_E1UC_15_H_OUT |
PORT103_EMIOS1_E1UC_16_X_OUT |
PORT107_EMIOS0_E0UC_25_Y_OUT |
PORT108_EMIOS0_E0UC_26_Y_OUT |
PORT109_EMIOS0_E0UC_27_Y_OUT |
PORT110_EMIOS1_E1UC_0_X_OUT |
PORT111_EMIOS1_E1UC_1_H_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 112 ... 127 : PORT112_EMIOS1_E1UC_2_H_OUT |
PORT113_EMIOS1_E1UC_3_H_OUT |
PORT114_EMIOS1_E1UC_4_H_OUT |
PORT121_DCI_TCK |
PORT122_DCI_TMS_OUT |
PORT124_DSPI_3_dSCLK_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(12)
          ),
/* Pads 128 ... 143 : PORT128_EMIOS0_E0UC_28_Y_OUT |
PORT129_EMIOS0_E0UC_29_Y_OUT |
PORT130_EMIOS0_E0UC_30_Y_OUT |
PORT131_EMIOS0_E0UC_31_Y_OUT |
PORT142_SAI2_SAI2_D0_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(14)
          ),
/* Pads 144 ... 159 : PORT144_SPI_0_CS1_0 |
PORT145_SPI_0_SOUT_0 |
PORT146_SPI_1_CS0_1 |
PORT157_SPI_3_CS1_3 |
PORT158_FlexCAN_1_TX */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14)
          )
}
,
/*  Mode PORT_ALT2_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_CGM_CLKOUT0 |
PORT3_LIN_5_LIN5TX |
PORT4_DSPI_1_dCS0 |
PORT5_LIN_4_LIN4TX |
PORT6_DSPI_1_dCS1 |
PORT7_LIN_3_LIN3TX |
PORT8_EMIOS0_E0UC_14_H_OUT |
PORT9_DSPI_1_dCS2 |
PORT10_IIC_0_SDA0_OUT |
PORT11_IIC_0_SCL0_OUT |
PORT12_DSPI_1_dCS3 |
PORT13_EMIOS0_E0UC_29_Y_OUT |
PORT14_DSPI_0_dCS0 |
PORT15_DSPI_0_dSCLK_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_EMIOS0_E0UC_30_Y_OUT |
PORT17_EMIOS0_E0UC_5_G_OUT |
PORT26_FlexCAN_3_TX */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(10)
          ),
/* Pads  32 ...  47 : PORT37_FlexCAN_3_TX |
PORT42_FlexCAN_4_TX |
PORT43_EMIOS0_E0UC_1_G_OUT */
  (uint16)( SHL_PAD_U16(5) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11)
          ),
/* Pads  48 ...  63 : PORT61_EMIOS0_E0UC_25_Y_OUT */
  (uint16)( SHL_PAD_U16(13)
          ),
/* Pads  64 ...  79 : PORT66_FlexRay_FR_A_TX_EN |
PORT67_DSPI_1_dSOUT |
PORT72_EMIOS0_E0UC_22_X_OUT |
PORT73_IIC_2_SCL2_OUT |
PORT77_EMIOS1_E1UC_20_Y_OUT |
PORT79_EMIOS1_E1UC_22_X_OUT */
  (uint16)( SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(13) |
SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT80_DSPI_1_dCS3 |
PORT85_DSPI_2_dCS3 |
PORT88_DSPI_0_dCS4 |
PORT89_DSPI_0_dCS5 |
PORT90_LIN_4_LIN4TX |
PORT94_EMIOS1_E1UC_27_Y_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(5) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(14)
          ),
/* Pads  96 ... 111 : PORT96_EMIOS1_E1UC_23_X_OUT |
PORT97_ENET0_MII_RMII_0_TX_CLK_OUT |
PORT98_DSPI_3_dSOUT |
PORT99_DSPI_3_dCS0 |
PORT102_LIN_6_LIN6TX |
PORT103_EMIOS1_E1UC_30_Y_OUT |
PORT107_SPI_0_CS0_0 |
PORT108_SPI_0_SOUT_0 |
PORT109_SPI_0_SCLK_0_OUT |
PORT110_LIN_8_LIN8TX |
PORT111_SPI_2_SOUT_2 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 112 ... 127 : PORT113_DSPI_1_dSOUT |
PORT114_DSPI_1_dSCLK_OUT |
PORT124_SPI_0_CS1_0 */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(12)
          ),
/* Pads 128 ... 143 : PORT128_LIN_8_LIN8TX |
PORT129_IIC_1_SCL1_OUT |
PORT130_LIN_9_LIN9TX |
PORT131_IIC_2_SCL2_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3)
          ),
/* Pads 144 ... 159 : PORT144_DSPI_2_dCS3 |
PORT145_SAI2_SAI2_BCLK_OUT |
PORT146_SPI_2_CS0_2 |
PORT158_FlexCAN_4_TX */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(14)
          )
}
,
/*  Mode PORT_ALT3_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_EMIOS0_E0UC_13_H_OUT |
PORT2_ADC_0_ADC0_MA_2 |
PORT3_DSPI_1_dCS4 |
PORT4_EMIOS0_E0UC_24_X_OUT |
PORT10_LIN_2_LIN2TX |
PORT12_EMIOS0_E0UC_26_Y_OUT |
PORT13_EMIOS0_E0UC_25_Y_OUT |
PORT14_EMIOS0_E0UC_0_X_OUT |
PORT15_EMIOS0_E0UC_1_G_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(10) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_LIN_0_LIN0TX |
PORT26_CMP2_CMP2_O */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(10)
          ),
/* Pads  32 ...  47 : PORT42_ADC_0_ADC0_MA_1 */
  (uint16)( SHL_PAD_U16(10)
          ),
/* Pads  48 ...  63 : PORT61_ENET0_ENET0_TMR0_OUT */
  (uint16)( SHL_PAD_U16(13)
          ),
/* Pads  64 ...  79 : PORT72_FlexCAN_3_TX |
PORT79_SPI_2_SCLK_2_OUT */
  (uint16)( SHL_PAD_U16(8) |
SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT85_SPI_0_CS2_0 |
PORT88_FlexCAN_2_TX |
PORT89_EMIOS0_E0UC_14_H_OUT |
PORT90_EMIOS1_E1UC_2_H_OUT |
PORT94_FlexCAN_1_TX */
  (uint16)( SHL_PAD_U16(5) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(14)
          ),
/* Pads  96 ... 111 : PORT96_ENET0_MII_RMII_0_MDC |
PORT98_FlexCAN_7_TX |
PORT102_CGM_CLKOUT1 |
PORT103_CGM_CLKOUT0 |
PORT107_SPI_2_CS0_2 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(2) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(11)
          ),
/* Pads 112 ... 127 : PORT112_ENET0_MII_RMII_0_TXD_1 |
PORT124_EMIOS1_E1UC_25_Y_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(12)
          ),
/* Pads 128 ... 143 : PORT128_IIC_1_SDA1_OUT |
PORT130_IIC_2_SDA2_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(2)
          ),
/* Pads 144 ... 159 : PORT144_SAI2_SAI2_SYNC_OUT |
PORT146_SPI_3_CS0_3 |
PORT157_EMIOS1_E1UC_15_H_OUT |
PORT158_SPI_3_CS2_3 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(2) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14)
          )
}
,
/*  Mode PORT_ALT4_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT13_FlexCAN_0_TX |
PORT14_EMIOS0_E0UC_23_X_OUT |
PORT15_EMIOS0_E0UC_21_Y_OUT */
  (uint16)( SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_EMIOS0_E0UC_4_G_OUT |
PORT26_SAI0_SAI0_SYNC_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(10)
          ),
/* Pads  32 ...  47 : PORT37_FlexRay_FR_A_TX |
PORT42_CMP0_CMP0_O */
  (uint16)( SHL_PAD_U16(5) |
SHL_PAD_U16(10)
          ),
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads  64 ...  79 : PORT72_IIC_2_SDA2_OUT */
  (uint16)( SHL_PAD_U16(8)
          ),
/* Pads  80 ...  95 : PORT80_FlexCAN_6_TX |
PORT85_SAI0_SAI0_D0_OUT |
PORT88_EMIOS0_E0UC_15_H_OUT |
PORT90_EMIOS0_E0UC_19_Y_OUT |
PORT94_ENET0_MII_RMII_0_MDIO_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(5) |
SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(14)
          ),
/* Pads  96 ... 111 : PORT98_LIN_11_LIN11TX |
PORT102_EMIOS0_E0UC_3_G_OUT |
PORT108_ENET0_MII_0_TXD_2 |
PORT109_ENET0_MII_0_TXD_3 */
  (uint16)( SHL_PAD_U16(2) |
SHL_PAD_U16(6) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13)
          ),
/* Pads 112 ... 127 : PORT113_ENET0_MII_RMII_0_TXD_0 |
PORT114_ENET0_MII_RMII_0_TX_EN */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(2)
          ),
/* Pads 128 ... 143 */
  (uint16)0x0000,
/* Pads 144 ... 159 : PORT146_SAI1_SAI1_D0_OUT |
PORT158_FlexCAN_6_TX */
  (uint16)( SHL_PAD_U16(2) |
SHL_PAD_U16(14)
          )
}
,
/*  Mode PORT_ALT5_FUNC_MODE: */
{
/* Pads 0 ... 15 */
  (uint16)0x0000,
/* Pads  16 ...  31 : PORT26_EMIOS0_E0UC_29_Y_OUT */
  (uint16)( SHL_PAD_U16(10)
          ),
/* Pads 32 ... 47 */
  (uint16)0x0000,
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads  64 ...  79 : PORT72_LIN_6_LIN6TX */
  (uint16)( SHL_PAD_U16(8)
          ),
/* Pads  80 ...  95 : PORT90_FCCU_EOUT0_OUT */
  (uint16)( SHL_PAD_U16(10)
          ),
/* Pads 96 ... 111 */
  (uint16)0x0000,
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 */
  (uint16)0x0000,
/* Pads 144 ... 159 */
  (uint16)0x0000
}
,
/*  Mode PORT_ALT6_FUNC_MODE: */
{
/* Pads 0 ... 15 */
  (uint16)0x0000,
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads  32 ...  47 : PORT42_LIN_6_LIN6TX */
  (uint16)( SHL_PAD_U16(10)
          ),
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads 64 ... 79 */
  (uint16)0x0000,
/* Pads 80 ... 95 */
  (uint16)0x0000,
/* Pads 96 ... 111 */
  (uint16)0x0000,
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 */
  (uint16)0x0000,
/* Pads 144 ... 159 : PORT158_EMIOS1_E1UC_14_H_OUT */
  (uint16)( SHL_PAD_U16(14)
          )
}
,
/*  Mode PORT_ALT7_FUNC_MODE: */
{
/* Pads 0 ... 15 */
  (uint16)0x0000,
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads  32 ...  47 : PORT37_SSCM_SSCM_DBG_3 */
  (uint16)( SHL_PAD_U16(5)
          ),
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads 64 ... 79 */
  (uint16)0x0000,
/* Pads  80 ...  95 : PORT80_SAI0_SAI0_MCLK_OUT */
  (uint16)( SHL_PAD_U16(0)
          ),
/* Pads 96 ... 111 */
  (uint16)0x0000,
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 */
  (uint16)0x0000,
/* Pads 144 ... 159 */
  (uint16)0x0000
}
,
/*  Mode PORT_ONLY_OUTPUT_MODE: */
{
/* Pads 0 ... 15 */
  (uint16)0x0000,
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads 32 ... 47 */
  (uint16)0x0000,
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads 64 ... 79 */
  (uint16)0x0000,
/* Pads 80 ... 95 */
  (uint16)0x0000,
/* Pads  96 ... 111 : PORT102_PMCDIG_EXTREGC */
  (uint16)( SHL_PAD_U16(6)
          ),
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 */
  (uint16)0x0000,
/* Pads 144 ... 159 */
  (uint16)0x0000
}
,
/*  Mode PORT_ONLY_INPUT_MODE: */
{
/* Pads   0 ...  15 : PORT0_WKPU_WKPU_19 |
PORT1_WKPU_WKPU_2 |
PORT1_WKPU_NMI_0 |
PORT2_WKPU_WKPU_3 |
PORT4_WKPU_WKPU_9 |
PORT15_WKPU_WKPU_10 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(4) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT17_WKPU_WKPU_4 |
PORT26_WKPU_WKPU_8 */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(10)
          ),
/* Pads  32 ...  47 : PORT43_WKPU_WKPU_5 */
  (uint16)( SHL_PAD_U16(11)
          ),
/* Pads  48 ...  63 : PORT49_GPI |
PORT49_WKPU_WKPU_28 */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(1)
          ),
/* Pads  64 ...  79 : PORT67_WKPU_WKPU_29 |
PORT73_WKPU_WKPU_7 */
  (uint16)( SHL_PAD_U16(3) |
SHL_PAD_U16(9)
          ),
/* Pads  80 ...  95 : PORT89_WKPU_WKPU_22 |
PORT90_FCCU_EOUT0_IN */
  (uint16)( SHL_PAD_U16(9) |
SHL_PAD_U16(10)
          ),
/* Pads  96 ... 111 : PORT99_WKPU_WKPU_17 |
PORT103_WKPU_WKPU_20 */
  (uint16)( SHL_PAD_U16(3) |
SHL_PAD_U16(7)
          ),
/* Pads 112 ... 127 : PORT122_DCI_TMS_IN */
  (uint16)( SHL_PAD_U16(10)
          ),
/* Pads 128 ... 143 : PORT129_WKPU_WKPU_24 |
PORT131_WKPU_WKPU_23 */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(3)
          ),
/* Pads 144 ... 159 : PORT157_WKPU_WKPU_31 */
  (uint16)( SHL_PAD_U16(13)
          )
}
,
/*  Mode PORT_ANALOG_INPUT_MODE: */
{
/* Pads   0 ...  15 : PORT3_ADC_1_ADC1_S_0 |
PORT4_CMP1_CMP1_13 |
PORT7_ADC_1_ADC1_S_8 |
PORT8_ADC_1_ADC1_S_9 |
PORT9_ADC_1_ADC1_S_10 |
PORT10_ADC_1_ADC1_S_11 |
PORT11_ADC_1_ADC1_S_12 |
PORT12_CMP1_CMP1_15 |
PORT13_CMP1_CMP1_14 |
PORT14_CMP1_CMP1_12 |
PORT15_CMP1_CMP1_10 */
  (uint16)( SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_CMP0_CMP0_2 |
PORT17_CMP0_CMP0_3 |
PORT26_ADC_0_ADC0_S_2 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(10)
          ),
/* Pads 32 ... 47 */
  (uint16)0x0000,
/* Pads  48 ...  63 : PORT49_ADC_1_ADC1_P_5 |
PORT61_ADC_0_ADC0_S_5 */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(13)
          ),
/* Pads  64 ...  79 : PORT77_ADC_1_ADC1_X_3 */
  (uint16)( SHL_PAD_U16(13)
          ),
/* Pads  80 ...  95 : PORT80_ADC_0_ADC0_S_8 |
PORT80_CMP2_CMP2_16 |
PORT85_ADC_0_ADC0_S_13 |
PORT85_CMP2_CMP2_21 |
PORT88_CMP0_CMP0_5 |
PORT89_CMP0_CMP0_4 |
PORT90_CMP1_CMP1_8 |
PORT94_ADC_1_ADC1_X_2 |
PORT95_ADC_1_ADC1_X_1 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(0) |
SHL_PAD_U16(5) |
SHL_PAD_U16(5) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT96_ADC_1_ADC1_X_0 |
PORT97_ADC_1_ADC1_S_7 |
PORT102_CMP0_CMP0_1 |
PORT103_CMP0_CMP0_0 |
PORT108_ADC_1_ADC1_S_2 |
PORT109_ADC_1_ADC1_S_1 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13)
          ),
/* Pads 112 ... 127 : PORT112_ADC_1_ADC1_S_3 |
PORT113_ADC_1_ADC1_S_4 |
PORT114_ADC_1_ADC1_S_5 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2)
          ),
/* Pads 128 ... 143 : PORT142_ADC_0_ADC0_S_22 */
  (uint16)( SHL_PAD_U16(14)
          ),
/* Pads 144 ... 159 : PORT144_ADC_0_ADC0_S_24 |
PORT145_ADC_0_ADC0_S_25 |
PORT146_ADC_0_ADC0_S_26 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2)
          )
}
,
/*  Mode PORT_INPUT1_MODE: */
{
/* Pads   0 ...  15 : PORT0_EMIOS0_E0UC_0_X_IN |
PORT1_EMIOS0_E0UC_1_G_IN |
PORT2_EMIOS0_E0UC_2_G_IN |
PORT3_EMIOS0_E0UC_3_G_IN |
PORT4_EMIOS0_E0UC_4_G_IN |
PORT5_EMIOS0_E0UC_5_G_IN |
PORT6_EMIOS0_E0UC_6_G_IN |
PORT7_EMIOS0_E0UC_7_G_IN |
PORT8_EMIOS0_E0UC_8_X_IN |
PORT9_EMIOS0_E0UC_9_H_IN |
PORT10_EMIOS0_E0UC_10_H_IN |
PORT11_EMIOS0_E0UC_11_H_IN |
PORT12_EMIOS0_E0UC_28_Y_IN |
PORT13_EMIOS0_E0UC_29_Y_IN |
PORT14_EMIOS0_E0UC_0_X_IN |
PORT15_EMIOS0_E0UC_1_G_IN */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_EMIOS0_E0UC_30_Y_IN |
PORT17_EMIOS0_E0UC_31_Y_IN |
PORT26_FlexCAN_6_RX */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(10)
          ),
/* Pads  32 ...  47 : PORT37_SIUL2_EIRQ7 |
PORT43_FlexCAN_1_RX */
  (uint16)( SHL_PAD_U16(5) |
SHL_PAD_U16(11)
          ),
/* Pads  48 ...  63 : PORT61_EMIOS0_E0UC_25_Y_IN */
  (uint16)( SHL_PAD_U16(13)
          ),
/* Pads  64 ...  79 : PORT66_EMIOS0_E0UC_18_Y_IN |
PORT67_EMIOS0_E0UC_19_Y_IN |
PORT72_EMIOS0_E0UC_22_X_IN |
PORT73_EMIOS0_E0UC_23_X_IN |
PORT77_EMIOS1_E1UC_20_Y_IN |
PORT79_EMIOS1_E1UC_22_X_IN */
  (uint16)( SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(13) |
SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT80_EMIOS0_E0UC_10_H_IN |
PORT85_EMIOS0_E0UC_22_X_IN |
PORT88_EMIOS0_E0UC_15_H_IN |
PORT89_EMIOS1_E1UC_1_H_IN |
PORT90_EMIOS1_E1UC_2_H_IN |
PORT94_EMIOS1_E1UC_27_Y_IN |
PORT95_EMIOS1_E1UC_4_H_IN */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(5) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT96_EMIOS1_E1UC_23_X_IN |
PORT97_EMIOS1_E1UC_24_X_IN |
PORT98_EMIOS1_E1UC_11_H_IN |
PORT99_EMIOS1_E1UC_12_H_IN |
PORT102_EMIOS1_E1UC_15_H_IN |
PORT103_EMIOS1_E1UC_16_X_IN |
PORT107_EMIOS0_E0UC_25_Y_IN |
PORT108_EMIOS0_E0UC_26_Y_IN |
PORT109_EMIOS0_E0UC_27_Y_IN |
PORT110_EMIOS1_E1UC_0_X_IN |
PORT111_EMIOS1_E1UC_1_H_IN */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 112 ... 127 : PORT112_EMIOS1_E1UC_2_H_IN |
PORT113_EMIOS1_E1UC_3_H_IN |
PORT114_EMIOS1_E1UC_4_H_IN |
PORT124_EMIOS1_E1UC_25_Y_IN */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(12)
          ),
/* Pads 128 ... 143 : PORT128_EMIOS0_E0UC_28_Y_IN |
PORT129_EMIOS0_E0UC_29_Y_IN |
PORT130_EMIOS0_E0UC_30_Y_IN |
PORT131_EMIOS0_E0UC_31_Y_IN |
PORT142_SPI_0_SIN_0 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(14)
          ),
/* Pads 144 ... 159 : PORT144_SAI2_SAI2_SYNC_IN |
PORT145_SPI_1_SIN_1 |
PORT146_SPI_1_SS_1 |
PORT157_EMIOS1_E1UC_15_H_IN |
PORT158_EMIOS1_E1UC_14_H_IN */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14)
          )
}
,
/*  Mode PORT_INPUT2_MODE: */
{
/* Pads   0 ...  15 : PORT0_EMIOS0_E0UC_13_H_IN |
PORT1_FlexCAN_3_RX |
PORT3_SIUL2_EIRQ0 |
PORT4_LIN_5_LIN5RX |
PORT6_SIUL2_EIRQ1 |
PORT7_SIUL2_EIRQ2 |
PORT8_EMIOS0_E0UC_14_H_IN |
PORT9_ENET0_MII_RMII_0_RXD_0 |
PORT10_IIC_0_SDA0_IN |
PORT11_SIUL2_EIRQ16 |
PORT12_SIUL2_EIRQ17 |
PORT13_EMIOS0_E0UC_25_Y_IN |
PORT14_SIUL2_EIRQ4 |
PORT15_FlexCAN_0_RX */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_EMIOS0_E0UC_4_G_IN |
PORT17_FlexCAN_0_RX |
PORT26_SAI0_SAI0_SYNC_IN */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(10)
          ),
/* Pads  32 ...  47 : PORT43_FlexCAN_4_RX */
  (uint16)( SHL_PAD_U16(11)
          ),
/* Pads  48 ...  63 : PORT61_DSPI_1_dSS */
  (uint16)( SHL_PAD_U16(13)
          ),
/* Pads  64 ...  79 : PORT66_SIUL2_EIRQ21 |
PORT67_FlexRay_FR_A_RX |
PORT72_IIC_2_SDA2_IN |
PORT73_FlexCAN_2_RX |
PORT77_ENET0_MII_0_RXD_3 |
PORT79_DSPI_2_dSS */
  (uint16)( SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(13) |
SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT80_SAI0_SAI0_MCLK_IN |
PORT85_SAI0_SAI0_D0_IN |
PORT89_FlexCAN_2_RX |
PORT90_EMIOS0_E0UC_19_Y_IN |
PORT94_ENET0_MII_RMII_0_MDIO_IN |
PORT95_SIUL2_EIRQ13 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(5) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT97_SIUL2_EIRQ14 |
PORT99_FlexCAN_7_RX |
PORT102_EMIOS0_E0UC_3_G_IN |
PORT103_EMIOS1_E1UC_30_Y_IN |
PORT107_SPI_0_SS_0 |
PORT109_SPI_0_SCLK_0_IN |
PORT110_SPI_2_SIN_2 |
PORT111_LIN_8_LIN8RX */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(3) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(11) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 112 ... 127 : PORT112_DSPI_1_dSIN |
PORT114_DSPI_1_dSCLK_IN |
PORT124_DSPI_3_dSCLK_IN */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(2) |
SHL_PAD_U16(12)
          ),
/* Pads 128 ... 143 : PORT128_IIC_1_SDA1_IN |
PORT129_LIN_8_LIN8RX |
PORT130_IIC_2_SDA2_IN |
PORT131_LIN_9_LIN9RX |
PORT142_SAI2_SAI2_D0_IN */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(14)
          ),
/* Pads 144 ... 159 : PORT145_SAI2_SAI2_BCLK_IN |
PORT146_SPI_2_SS_2 |
PORT157_FlexCAN_1_RX */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(13)
          )
}
,
/*  Mode PORT_INPUT3_MODE: */
{
/* Pads   0 ...  15 : PORT0_FlexCAN_1_RX |
PORT3_ENET0_MII_0_RX_CLK |
PORT4_DSPI_1_dSS |
PORT6_LIN_4_LIN4RX |
PORT7_ENET0_MII_0_RXD_2 |
PORT8_SIUL2_EIRQ3 |
PORT10_DSPI_1_dSIN |
PORT11_LIN_2_LIN2RX |
PORT12_DSPI_0_dSIN |
PORT13_GLITCH_FILTER0_INP |
PORT14_DSPI_0_dSCLK_IN |
PORT15_DSPI_0_dSCLK_IN */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_GLITCH_FILTER1_INP |
PORT17_LIN_0_LIN0RX |
PORT26_EMIOS0_E0UC_29_Y_IN */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(10)
          ),
/* Pads  32 ...  47 : PORT43_EMIOS0_E0UC_1_G_IN */
  (uint16)( SHL_PAD_U16(11)
          ),
/* Pads  48 ...  63 : PORT61_ENET0_ENET0_TMR0_IN */
  (uint16)( SHL_PAD_U16(13)
          ),
/* Pads  64 ...  79 : PORT66_DSPI_1_dSIN |
PORT73_FlexCAN_3_RX |
PORT79_SPI_2_SCLK_2_IN */
  (uint16)( SHL_PAD_U16(2) |
SHL_PAD_U16(9) |
SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT85_GLITCH_FILTER3_INP |
PORT89_FlexCAN_3_RX |
PORT95_FlexCAN_1_RX */
  (uint16)( SHL_PAD_U16(5) |
SHL_PAD_U16(9) |
SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT97_FlexCAN_5_RX |
PORT99_DSPI_3_dSS |
PORT103_LIN_6_LIN6RX |
PORT107_SPI_2_SS_2 */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(3) |
SHL_PAD_U16(7) |
SHL_PAD_U16(11)
          ),
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 : PORT128_GLITCH_FILTER0_INP |
PORT129_IIC_1_SCL1_IN |
PORT130_GLITCH_FILTER1_INP |
PORT131_IIC_2_SCL2_IN */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3)
          ),
/* Pads 144 ... 159 : PORT146_SPI_3_SS_3 |
PORT157_FlexCAN_4_RX */
  (uint16)( SHL_PAD_U16(2) |
SHL_PAD_U16(13)
          )
}
,
/*  Mode PORT_INPUT4_MODE: */
{
/* Pads   0 ...  15 : PORT4_EMIOS0_E0UC_24_X_IN |
PORT8_LIN_3_LIN3RX |
PORT10_ENET0_MII_0_COL |
PORT11_IIC_0_SCL0_IN |
PORT12_EMIOS0_E0UC_26_Y_IN |
PORT14_DSPI_0_dSS |
PORT15_DSPI_0_dSS */
  (uint16)( SHL_PAD_U16(4) |
SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT17_EMIOS0_E0UC_5_G_IN */
  (uint16)( SHL_PAD_U16(1)
          ),
/* Pads 32 ... 47 */
  (uint16)0x0000,
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads  64 ...  79 : PORT73_IIC_2_SCL2_IN */
  (uint16)( SHL_PAD_U16(9)
          ),
/* Pads  80 ...  95 : PORT89_EMIOS0_E0UC_14_H_IN |
PORT95_FlexCAN_4_RX */
  (uint16)( SHL_PAD_U16(9) |
SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT97_ENET0_MII_RMII_0_TX_CLK_IN |
PORT103_GLITCH_FILTER3_INP */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(7)
          ),
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 : PORT129_GLITCH_FILTER0_INP |
PORT131_GLITCH_FILTER1_INP */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(3)
          ),
/* Pads 144 ... 159 : PORT146_SAI1_SAI1_D0_IN |
PORT157_FlexCAN_6_RX */
  (uint16)( SHL_PAD_U16(2) |
SHL_PAD_U16(13)
          )
}
,
/*  Mode PORT_INPUT5_MODE: */
{
/* Pads   0 ...  15 : PORT8_ENET0_MII_RMII_0_RXD_1 |
PORT11_ENET0_MII_RMII_0_RX_ER |
PORT12_GLITCH_FILTER0_INP |
PORT14_EMIOS0_E0UC_23_X_IN |
PORT15_EMIOS0_E0UC_21_Y_IN */
  (uint16)( SHL_PAD_U16(8) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT17_GLITCH_FILTER1_INP */
  (uint16)( SHL_PAD_U16(1)
          ),
/* Pads 32 ... 47 */
  (uint16)0x0000,
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads 64 ... 79 */
  (uint16)0x0000,
/* Pads  80 ...  95 : PORT95_ENET0_MII_RMII_0_RX_DV */
  (uint16)( SHL_PAD_U16(15)
          ),
/* Pads 96 ... 111 */
  (uint16)0x0000,
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 */
  (uint16)0x0000,
/* Pads 144 ... 159 */
  (uint16)0x0000
}
,
/*  Mode PORT_INPUT6_MODE: */
{
/* Pads 0 ... 15 */
  (uint16)0x0000,
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads 32 ... 47 */
  (uint16)0x0000,
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads 64 ... 79 */
  (uint16)0x0000,
/* Pads 80 ... 95 */
  (uint16)0x0000,
/* Pads 96 ... 111 */
  (uint16)0x0000,
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 */
  (uint16)0x0000,
/* Pads 144 ... 159 */
  (uint16)0x0000
}
,
/*  Mode PORT_INOUT1_MODE: */
{
/* Pads   0 ...  15 : PORT0_EMIOS0_E0UC_0_X_IN_OUT |
PORT1_EMIOS0_E0UC_1_G_IN_OUT |
PORT2_EMIOS0_E0UC_2_G_IN_OUT |
PORT3_EMIOS0_E0UC_3_G_IN_OUT |
PORT4_EMIOS0_E0UC_4_G_IN_OUT |
PORT5_EMIOS0_E0UC_5_G_IN_OUT |
PORT6_EMIOS0_E0UC_6_G_IN_OUT |
PORT7_EMIOS0_E0UC_7_G_IN_OUT |
PORT8_EMIOS0_E0UC_8_X_IN_OUT |
PORT9_EMIOS0_E0UC_9_H_IN_OUT |
PORT10_EMIOS0_E0UC_10_H_IN_OUT |
PORT11_EMIOS0_E0UC_11_H_IN_OUT |
PORT12_EMIOS0_E0UC_28_Y_IN_OUT |
PORT14_DSPI_0_dSCLK_IN_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14)
          ),
/* Pads  16 ...  31 : PORT17_EMIOS0_E0UC_31_Y_IN_OUT */
  (uint16)( SHL_PAD_U16(1)
          ),
/* Pads 32 ... 47 */
  (uint16)0x0000,
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads  64 ...  79 : PORT66_EMIOS0_E0UC_18_Y_IN_OUT |
PORT67_EMIOS0_E0UC_19_Y_IN_OUT |
PORT73_EMIOS0_E0UC_23_X_IN_OUT */
  (uint16)( SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(9)
          ),
/* Pads  80 ...  95 : PORT80_EMIOS0_E0UC_10_H_IN_OUT |
PORT85_EMIOS0_E0UC_22_X_IN_OUT |
PORT89_EMIOS1_E1UC_1_H_IN_OUT |
PORT95_EMIOS1_E1UC_4_H_IN_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(5) |
SHL_PAD_U16(9) |
SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT97_EMIOS1_E1UC_24_X_IN_OUT |
PORT98_EMIOS1_E1UC_11_H_IN_OUT |
PORT99_EMIOS1_E1UC_12_H_IN_OUT |
PORT102_EMIOS1_E1UC_15_H_IN_OUT |
PORT103_EMIOS1_E1UC_16_X_IN_OUT |
PORT107_EMIOS0_E0UC_25_Y_IN_OUT |
PORT108_EMIOS0_E0UC_26_Y_IN_OUT |
PORT109_EMIOS0_E0UC_27_Y_IN_OUT |
PORT110_EMIOS1_E1UC_0_X_IN_OUT |
PORT111_EMIOS1_E1UC_1_H_IN_OUT */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 112 ... 127 : PORT112_EMIOS1_E1UC_2_H_IN_OUT |
PORT113_EMIOS1_E1UC_3_H_IN_OUT |
PORT114_EMIOS1_E1UC_4_H_IN_OUT |
PORT122_DCI_TMS_IN_OUT |
PORT124_DSPI_3_dSCLK_IN_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(10) |
SHL_PAD_U16(12)
          ),
/* Pads 128 ... 143 : PORT128_EMIOS0_E0UC_28_Y_IN_OUT |
PORT129_EMIOS0_E0UC_29_Y_IN_OUT |
PORT130_EMIOS0_E0UC_30_Y_IN_OUT |
PORT131_EMIOS0_E0UC_31_Y_IN_OUT |
PORT142_SAI2_SAI2_D0_IN_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(14)
          ),
/* Pads 144 ... 159 */
  (uint16)0x0000
}
,
/*  Mode PORT_INOUT2_MODE: */
{
/* Pads   0 ...  15 : PORT8_EMIOS0_E0UC_14_H_IN_OUT |
PORT10_IIC_0_SDA0_IN_OUT |
PORT11_IIC_0_SCL0_IN_OUT |
PORT13_EMIOS0_E0UC_29_Y_IN_OUT |
PORT15_DSPI_0_dSCLK_IN_OUT */
  (uint16)( SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(13) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_EMIOS0_E0UC_30_Y_IN_OUT |
PORT17_EMIOS0_E0UC_5_G_IN_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1)
          ),
/* Pads  32 ...  47 : PORT43_EMIOS0_E0UC_1_G_IN_OUT */
  (uint16)( SHL_PAD_U16(11)
          ),
/* Pads  48 ...  63 : PORT61_EMIOS0_E0UC_25_Y_IN_OUT */
  (uint16)( SHL_PAD_U16(13)
          ),
/* Pads  64 ...  79 : PORT72_EMIOS0_E0UC_22_X_IN_OUT |
PORT73_IIC_2_SCL2_IN_OUT |
PORT77_EMIOS1_E1UC_20_Y_IN_OUT |
PORT79_EMIOS1_E1UC_22_X_IN_OUT */
  (uint16)( SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(13) |
SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT94_EMIOS1_E1UC_27_Y_IN_OUT */
  (uint16)( SHL_PAD_U16(14)
          ),
/* Pads  96 ... 111 : PORT96_EMIOS1_E1UC_23_X_IN_OUT |
PORT97_ENET0_MII_RMII_0_TX_CLK_IN_OUT |
PORT103_EMIOS1_E1UC_30_Y_IN_OUT |
PORT109_SPI_0_SCLK_0_IN_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(7) |
SHL_PAD_U16(13)
          ),
/* Pads 112 ... 127 : PORT114_DSPI_1_dSCLK_IN_OUT */
  (uint16)( SHL_PAD_U16(2)
          ),
/* Pads 128 ... 143 : PORT129_IIC_1_SCL1_IN_OUT |
PORT131_IIC_2_SCL2_IN_OUT */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(3)
          ),
/* Pads 144 ... 159 : PORT145_SAI2_SAI2_BCLK_IN_OUT */
  (uint16)( SHL_PAD_U16(1)
          )
}
,
/*  Mode PORT_INOUT3_MODE: */
{
/* Pads   0 ...  15 : PORT0_EMIOS0_E0UC_13_H_IN_OUT |
PORT4_EMIOS0_E0UC_24_X_IN_OUT |
PORT12_EMIOS0_E0UC_26_Y_IN_OUT |
PORT13_EMIOS0_E0UC_25_Y_IN_OUT |
PORT14_EMIOS0_E0UC_0_X_IN_OUT |
PORT15_EMIOS0_E0UC_1_G_IN_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(4) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads 32 ... 47 */
  (uint16)0x0000,
/* Pads  48 ...  63 : PORT61_ENET0_ENET0_TMR0_IN_OUT */
  (uint16)( SHL_PAD_U16(13)
          ),
/* Pads  64 ...  79 : PORT79_SPI_2_SCLK_2_IN_OUT */
  (uint16)( SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT89_EMIOS0_E0UC_14_H_IN_OUT |
PORT90_EMIOS1_E1UC_2_H_IN_OUT */
  (uint16)( SHL_PAD_U16(9) |
SHL_PAD_U16(10)
          ),
/* Pads 96 ... 111 */
  (uint16)0x0000,
/* Pads 112 ... 127 : PORT124_EMIOS1_E1UC_25_Y_IN_OUT */
  (uint16)( SHL_PAD_U16(12)
          ),
/* Pads 128 ... 143 : PORT128_IIC_1_SDA1_IN_OUT |
PORT130_IIC_2_SDA2_IN_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(2)
          ),
/* Pads 144 ... 159 : PORT144_SAI2_SAI2_SYNC_IN_OUT |
PORT157_EMIOS1_E1UC_15_H_IN_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(13)
          )
}
,
/*  Mode PORT_INOUT4_MODE: */
{
/* Pads   0 ...  15 : PORT14_EMIOS0_E0UC_23_X_IN_OUT |
PORT15_EMIOS0_E0UC_21_Y_IN_OUT */
  (uint16)( SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_EMIOS0_E0UC_4_G_IN_OUT |
PORT26_SAI0_SAI0_SYNC_IN_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(10)
          ),
/* Pads 32 ... 47 */
  (uint16)0x0000,
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads  64 ...  79 : PORT72_IIC_2_SDA2_IN_OUT */
  (uint16)( SHL_PAD_U16(8)
          ),
/* Pads  80 ...  95 : PORT85_SAI0_SAI0_D0_IN_OUT |
PORT88_EMIOS0_E0UC_15_H_IN_OUT |
PORT90_EMIOS0_E0UC_19_Y_IN_OUT |
PORT94_ENET0_MII_RMII_0_MDIO_IN_OUT */
  (uint16)( SHL_PAD_U16(5) |
SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(14)
          ),
/* Pads  96 ... 111 : PORT102_EMIOS0_E0UC_3_G_IN_OUT */
  (uint16)( SHL_PAD_U16(6)
          ),
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 */
  (uint16)0x0000,
/* Pads 144 ... 159 : PORT146_SAI1_SAI1_D0_IN_OUT */
  (uint16)( SHL_PAD_U16(2)
          )
}
,
/*  Mode PORT_INOUT5_MODE: */
{
/* Pads 0 ... 15 */
  (uint16)0x0000,
/* Pads  16 ...  31 : PORT26_EMIOS0_E0UC_29_Y_IN_OUT */
  (uint16)( SHL_PAD_U16(10)
          ),
/* Pads 32 ... 47 */
  (uint16)0x0000,
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads 64 ... 79 */
  (uint16)0x0000,
/* Pads  80 ...  95 : PORT90_FCCU_EOUT0_IN_OUT */
  (uint16)( SHL_PAD_U16(10)
          ),
/* Pads 96 ... 111 */
  (uint16)0x0000,
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 */
  (uint16)0x0000,
/* Pads 144 ... 159 */
  (uint16)0x0000
}
,
/*  Mode PORT_INOUT6_MODE: */
{
/* Pads 0 ... 15 */
  (uint16)0x0000,
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads 32 ... 47 */
  (uint16)0x0000,
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads 64 ... 79 */
  (uint16)0x0000,
/* Pads 80 ... 95 */
  (uint16)0x0000,
/* Pads 96 ... 111 */
  (uint16)0x0000,
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 */
  (uint16)0x0000,
/* Pads 144 ... 159 : PORT158_EMIOS1_E1UC_14_H_IN_OUT */
  (uint16)( SHL_PAD_U16(14)
          )
}
,
/*  Mode PORT_INOUT7_MODE: */
{
/* Pads 0 ... 15 */
  (uint16)0x0000,
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads 32 ... 47 */
  (uint16)0x0000,
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads 64 ... 79 */
  (uint16)0x0000,
/* Pads  80 ...  95 : PORT80_SAI0_SAI0_MCLK_IN_OUT */
  (uint16)( SHL_PAD_U16(0)
          ),
/* Pads 96 ... 111 */
  (uint16)0x0000,
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 */
  (uint16)0x0000,
/* Pads 144 ... 159 */
  (uint16)0x0000
}

[!ENDVAR!]




[!VAR "CHECK_2"!]

/*  Mode PORT_GPIO_MODE: */
{
/* Pads   0 ...  15 : PORT0_GPIO |
PORT1_GPIO |
PORT2_GPIO |
PORT3_GPIO |
PORT4_GPIO |
PORT5_GPIO |
PORT6_GPIO |
PORT7_GPIO |
PORT8_GPIO |
PORT9_GPIO |
PORT10_GPIO |
PORT11_GPIO |
PORT12_GPIO |
PORT13_GPIO |
PORT14_GPIO |
PORT15_GPIO */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_GPIO |
PORT17_GPIO |
PORT18_GPIO |
PORT19_GPIO |
PORT26_GPIO |
PORT27_GPIO |
PORT28_GPIO |
PORT29_GPIO |
PORT30_GPIO |
PORT31_GPIO */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  32 ...  47 : PORT32_GPIO |
PORT33_GPIO |
PORT34_GPIO |
PORT35_GPIO |
PORT36_GPIO |
PORT37_GPIO |
PORT38_GPIO |
PORT39_GPIO |
PORT40_GPIO |
PORT41_GPIO |
PORT42_GPIO |
PORT43_GPIO |
PORT44_GPIO |
PORT45_GPIO |
PORT46_GPIO |
PORT47_GPIO */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  48 ...  63 : PORT60_GPIO |
PORT61_GPIO |
PORT62_GPIO |
PORT63_GPIO */
  (uint16)( SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  64 ...  79 : PORT64_GPIO |
PORT65_GPIO |
PORT66_GPIO |
PORT67_GPIO |
PORT68_GPIO |
PORT69_GPIO |
PORT70_GPIO |
PORT71_GPIO |
PORT72_GPIO |
PORT73_GPIO |
PORT74_GPIO |
PORT75_GPIO |
PORT76_GPIO |
PORT77_GPIO |
PORT78_GPIO |
PORT79_GPIO */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT80_GPIO |
PORT81_GPIO |
PORT82_GPIO |
PORT83_GPIO |
PORT84_GPIO |
PORT85_GPIO |
PORT86_GPIO |
PORT87_GPIO |
PORT88_GPIO |
PORT89_GPIO |
PORT90_GPIO |
PORT91_GPIO |
PORT92_GPIO |
PORT93_GPIO |
PORT94_GPIO |
PORT95_GPIO */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT96_GPIO |
PORT97_GPIO |
PORT98_GPIO |
PORT99_GPIO |
PORT100_GPIO |
PORT101_GPIO |
PORT102_GPIO |
PORT103_GPIO |
PORT104_GPIO |
PORT105_GPIO |
PORT106_GPIO |
PORT107_GPIO |
PORT108_GPIO |
PORT109_GPIO |
PORT110_GPIO |
PORT111_GPIO */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 112 ... 127 : PORT112_GPIO |
PORT113_GPIO |
PORT114_GPIO |
PORT115_GPIO |
PORT116_GPIO |
PORT117_GPIO |
PORT118_GPIO |
PORT119_GPIO |
PORT120_GPIO |
PORT121_GPIO |
PORT122_GPIO |
PORT123_GPIO |
PORT124_GPIO |
PORT125_GPIO |
PORT126_GPIO |
PORT127_GPIO */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 128 ... 143 : PORT128_GPIO |
PORT129_GPIO |
PORT130_GPIO |
PORT131_GPIO |
PORT132_GPIO |
PORT133_GPIO |
PORT134_GPIO |
PORT135_GPIO |
PORT136_GPIO |
PORT139_GPIO |
PORT140_GPIO |
PORT141_GPIO |
PORT142_GPIO |
PORT143_GPIO */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 144 ... 159 : PORT144_GPIO |
PORT145_GPIO |
PORT146_GPIO |
PORT147_GPIO |
PORT148_GPIO |
PORT157_GPIO |
PORT158_GPIO */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14)
          )
}
,
/*  Mode PORT_ALT1_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_EMIOS0_E0UC_0_X_OUT |
PORT1_EMIOS0_E0UC_1_G_OUT |
PORT2_EMIOS0_E0UC_2_G_OUT |
PORT3_EMIOS0_E0UC_3_G_OUT |
PORT4_EMIOS0_E0UC_4_G_OUT |
PORT5_EMIOS0_E0UC_5_G_OUT |
PORT6_EMIOS0_E0UC_6_G_OUT |
PORT7_EMIOS0_E0UC_7_G_OUT |
PORT8_EMIOS0_E0UC_8_X_OUT |
PORT9_EMIOS0_E0UC_9_H_OUT |
PORT10_EMIOS0_E0UC_10_H_OUT |
PORT11_EMIOS0_E0UC_11_H_OUT |
PORT12_EMIOS0_E0UC_28_Y_OUT |
PORT13_DSPI_0_dSOUT |
PORT14_DSPI_0_dSCLK_OUT |
PORT15_DSPI_0_dCS0 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_FlexCAN_0_TX |
PORT17_EMIOS0_E0UC_31_Y_OUT |
PORT18_LIN_0_LIN0TX |
PORT19_EMIOS0_E0UC_31_Y_OUT |
PORT26_DSPI_1_dSOUT |
PORT27_EMIOS0_E0UC_3_G_OUT |
PORT28_EMIOS0_E0UC_4_G_OUT |
PORT29_EMIOS0_E0UC_5_G_OUT |
PORT30_EMIOS0_E0UC_6_G_OUT |
PORT31_EMIOS0_E0UC_7_G_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  32 ...  47 : PORT32_DCI_TDI |
PORT33_DCI_TDO |
PORT34_DSPI_1_dSCLK_OUT |
PORT35_DSPI_1_dCS0 |
PORT36_EMIOS1_E1UC_31_Y_OUT |
PORT37_DSPI_1_dSOUT |
PORT38_LIN_1_LIN1TX |
PORT39_EMIOS1_E1UC_29_Y_OUT |
PORT40_LIN_2_LIN2TX |
PORT41_EMIOS0_E0UC_7_G_OUT |
PORT42_FlexCAN_1_TX |
PORT43_ADC_0_ADC0_MA_2 |
PORT44_EMIOS0_E0UC_12_H_OUT |
PORT45_EMIOS0_E0UC_13_H_OUT |
PORT46_EMIOS0_E0UC_14_H_OUT |
PORT47_EMIOS0_E0UC_15_H_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  48 ...  63 : PORT60_DSPI_0_dCS5 |
PORT61_DSPI_1_dCS0 |
PORT62_DSPI_1_dCS1 |
PORT63_DSPI_1_dCS2 */
  (uint16)( SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  64 ...  79 : PORT64_EMIOS0_E0UC_16_X_OUT |
PORT65_EMIOS0_E0UC_17_Y_OUT |
PORT66_EMIOS0_E0UC_18_Y_OUT |
PORT67_EMIOS0_E0UC_19_Y_OUT |
PORT68_EMIOS0_E0UC_20_Y_OUT |
PORT69_EMIOS0_E0UC_21_Y_OUT |
PORT70_EMIOS0_E0UC_22_X_OUT |
PORT71_EMIOS0_E0UC_23_X_OUT |
PORT72_FlexCAN_2_TX |
PORT73_EMIOS0_E0UC_23_X_OUT |
PORT74_LIN_3_LIN3TX |
PORT75_EMIOS0_E0UC_24_X_OUT |
PORT76_EMIOS1_E1UC_19_Y_OUT |
PORT77_DSPI_2_dSOUT |
PORT78_DSPI_2_dSCLK_OUT |
PORT79_DSPI_2_dCS0 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT80_EMIOS0_E0UC_10_H_OUT |
PORT81_EMIOS0_E0UC_11_H_OUT |
PORT82_EMIOS0_E0UC_12_H_OUT |
PORT83_EMIOS0_E0UC_13_H_OUT |
PORT84_EMIOS0_E0UC_14_H_OUT |
PORT85_EMIOS0_E0UC_22_X_OUT |
PORT86_EMIOS0_E0UC_23_X_OUT |
PORT87_SPI_0_SCLK_0_OUT |
PORT88_FlexCAN_3_TX |
PORT89_EMIOS1_E1UC_1_H_OUT |
PORT90_DSPI_0_dCS1 |
PORT91_DSPI_0_dCS2 |
PORT92_EMIOS1_E1UC_25_Y_OUT |
PORT93_EMIOS1_E1UC_26_Y_OUT |
PORT94_FlexCAN_4_TX |
PORT95_EMIOS1_E1UC_4_H_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT96_FlexCAN_5_TX |
PORT97_EMIOS1_E1UC_24_X_OUT |
PORT98_EMIOS1_E1UC_11_H_OUT |
PORT99_EMIOS1_E1UC_12_H_OUT |
PORT100_EMIOS1_E1UC_13_H_OUT |
PORT101_EMIOS1_E1UC_14_H_OUT |
PORT102_EMIOS1_E1UC_15_H_OUT |
PORT103_EMIOS1_E1UC_16_X_OUT |
PORT104_EMIOS1_E1UC_17_Y_OUT |
PORT105_EMIOS1_E1UC_18_Y_OUT |
PORT106_EMIOS0_E0UC_24_X_OUT |
PORT107_EMIOS0_E0UC_25_Y_OUT |
PORT108_EMIOS0_E0UC_26_Y_OUT |
PORT109_EMIOS0_E0UC_27_Y_OUT |
PORT110_EMIOS1_E1UC_0_X_OUT |
PORT111_EMIOS1_E1UC_1_H_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 112 ... 127 : PORT112_EMIOS1_E1UC_2_H_OUT |
PORT113_EMIOS1_E1UC_3_H_OUT |
PORT114_EMIOS1_E1UC_4_H_OUT |
PORT115_EMIOS1_E1UC_5_H_OUT |
PORT116_EMIOS1_E1UC_6_H_OUT |
PORT117_EMIOS1_E1UC_7_H_OUT |
PORT118_EMIOS1_E1UC_8_X_OUT |
PORT119_EMIOS1_E1UC_9_H_OUT |
PORT120_EMIOS1_E1UC_10_H_OUT |
PORT121_DCI_TCK |
PORT122_DCI_TMS_OUT |
PORT123_DSPI_3_dSOUT |
PORT124_DSPI_3_dSCLK_OUT |
PORT125_SPI_0_SOUT_0 |
PORT126_SPI_0_SCLK_0_OUT |
PORT127_SPI_1_SOUT_1 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 128 ... 143 : PORT128_EMIOS0_E0UC_28_Y_OUT |
PORT129_EMIOS0_E0UC_29_Y_OUT |
PORT130_EMIOS0_E0UC_30_Y_OUT |
PORT131_EMIOS0_E0UC_31_Y_OUT |
PORT132_EMIOS1_E1UC_28_Y_OUT |
PORT133_EMIOS1_E1UC_29_Y_OUT |
PORT134_EMIOS1_E1UC_30_Y_OUT |
PORT135_EMIOS1_E1UC_31_Y_OUT |
PORT140_DSPI_3_dCS0 |
PORT141_DSPI_3_dCS1 |
PORT142_SAI2_SAI2_D0_OUT |
PORT143_SPI_0_CS0_0 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 144 ... 159 : PORT144_SPI_0_CS1_0 |
PORT145_SPI_0_SOUT_0 |
PORT146_SPI_1_CS0_1 |
PORT147_SPI_1_CS1_1 |
PORT148_SPI_1_SCLK_1_OUT |
PORT157_SPI_3_CS1_3 |
PORT158_FlexCAN_1_TX */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14)
          )
}
,
/*  Mode PORT_ALT2_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_CGM_CLKOUT0 |
PORT3_LIN_5_LIN5TX |
PORT4_DSPI_1_dCS0 |
PORT5_LIN_4_LIN4TX |
PORT6_DSPI_1_dCS1 |
PORT7_LIN_3_LIN3TX |
PORT8_EMIOS0_E0UC_14_H_OUT |
PORT9_DSPI_1_dCS2 |
PORT10_IIC_0_SDA0_OUT |
PORT11_IIC_0_SCL0_OUT |
PORT12_DSPI_1_dCS3 |
PORT13_EMIOS0_E0UC_29_Y_OUT |
PORT14_DSPI_0_dCS0 |
PORT15_DSPI_0_dSCLK_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_EMIOS0_E0UC_30_Y_OUT |
PORT17_EMIOS0_E0UC_5_G_OUT |
PORT18_IIC_0_SDA0_OUT |
PORT19_IIC_0_SCL0_OUT |
PORT26_FlexCAN_3_TX |
PORT27_DSPI_0_dCS0 |
PORT28_DSPI_0_dCS1 |
PORT29_DSPI_0_dCS2 |
PORT30_DSPI_0_dCS3 |
PORT31_DSPI_0_dCS4 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  32 ...  47 : PORT34_FlexCAN_4_TX |
PORT35_ADC_0_ADC0_MA_0 |
PORT36_FlexRay_FR_B_TX_EN |
PORT37_FlexCAN_3_TX |
PORT38_EMIOS1_E1UC_28_Y_OUT |
PORT39_CMP1_CMP1_O |
PORT40_EMIOS0_E0UC_3_G_OUT |
PORT42_FlexCAN_4_TX |
PORT43_EMIOS0_E0UC_1_G_OUT |
PORT44_FlexRay_FR_DBG_0 |
PORT45_DSPI_2_dSOUT |
PORT46_DSPI_2_dSCLK_OUT |
PORT47_DSPI_2_dCS0 */
  (uint16)( SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  48 ...  63 : PORT60_EMIOS0_E0UC_24_X_OUT |
PORT61_EMIOS0_E0UC_25_Y_OUT |
PORT62_EMIOS0_E0UC_26_Y_OUT |
PORT63_EMIOS0_E0UC_27_Y_OUT */
  (uint16)( SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  64 ...  79 : PORT64_IIC_1_SCL1_OUT |
PORT65_FlexCAN_5_TX |
PORT66_FlexRay_FR_A_TX_EN |
PORT67_DSPI_1_dSOUT |
PORT68_DSPI_1_dSCLK_OUT |
PORT69_DSPI_1_dCS0 |
PORT70_DSPI_0_dCS3 |
PORT71_DSPI_0_dCS2 |
PORT72_EMIOS0_E0UC_22_X_OUT |
PORT73_IIC_2_SCL2_OUT |
PORT74_DSPI_1_dCS3 |
PORT75_DSPI_1_dCS4 |
PORT77_EMIOS1_E1UC_20_Y_OUT |
PORT78_EMIOS1_E1UC_21_Y_OUT |
PORT79_EMIOS1_E1UC_22_X_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT80_DSPI_1_dCS3 |
PORT81_DSPI_1_dCS4 |
PORT82_DSPI_2_dCS0 |
PORT83_DSPI_2_dCS1 |
PORT84_DSPI_2_dCS2 |
PORT85_DSPI_2_dCS3 |
PORT86_DSPI_1_dCS1 |
PORT87_DSPI_1_dCS2 |
PORT88_DSPI_0_dCS4 |
PORT89_DSPI_0_dCS5 |
PORT90_LIN_4_LIN4TX |
PORT91_EMIOS1_E1UC_3_H_OUT |
PORT92_LIN_5_LIN5TX |
PORT93_EMIOS0_E0UC_22_X_OUT |
PORT94_EMIOS1_E1UC_27_Y_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14)
          ),
/* Pads  96 ... 111 : PORT96_EMIOS1_E1UC_23_X_OUT |
PORT97_ENET0_MII_RMII_0_TX_CLK_OUT |
PORT98_DSPI_3_dSOUT |
PORT99_DSPI_3_dCS0 |
PORT100_DSPI_3_dSCLK_OUT |
PORT101_EMIOS0_E0UC_2_G_OUT |
PORT102_LIN_6_LIN6TX |
PORT103_EMIOS1_E1UC_30_Y_OUT |
PORT104_LIN_7_LIN7TX |
PORT105_DSPI_2_dSCLK_OUT |
PORT106_EMIOS1_E1UC_31_Y_OUT |
PORT107_SPI_0_CS0_0 |
PORT108_SPI_0_SOUT_0 |
PORT109_SPI_0_SCLK_0_OUT |
PORT110_LIN_8_LIN8TX |
PORT111_SPI_2_SOUT_2 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 112 ... 127 : PORT113_DSPI_1_dSOUT |
PORT114_DSPI_1_dSCLK_OUT |
PORT115_DSPI_1_dCS0 |
PORT116_SPI_3_SOUT_3 |
PORT117_IIC_3_SDA3_OUT |
PORT118_SPI_3_SCLK_3_OUT |
PORT119_DSPI_2_dCS3 |
PORT120_DSPI_2_dCS2 |
PORT123_SPI_0_CS0_0 |
PORT124_SPI_0_CS1_0 |
PORT125_DSPI_3_dCS0 |
PORT126_DSPI_3_dCS1 */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14)
          ),
/* Pads 128 ... 143 : PORT128_LIN_8_LIN8TX |
PORT129_IIC_1_SCL1_OUT |
PORT130_LIN_9_LIN9TX |
PORT131_IIC_2_SCL2_OUT |
PORT132_SPI_0_SOUT_0 |
PORT133_SPI_0_SCLK_0_OUT |
PORT134_SPI_0_CS0_0 |
PORT135_SPI_0_CS1_0 |
PORT139_ENET0_ENET0_TMR1_OUT |
PORT140_DSPI_2_dCS0 |
PORT141_DSPI_2_dCS1 |
PORT143_DSPI_2_dCS2 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(15)
          ),
/* Pads 144 ... 159 : PORT144_DSPI_2_dCS3 |
PORT145_SAI2_SAI2_BCLK_OUT |
PORT146_SPI_2_CS0_2 |
PORT147_SPI_2_CS1_2 |
PORT148_EMIOS1_E1UC_18_Y_OUT |
PORT158_FlexCAN_4_TX */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(14)
          )
}
,
/*  Mode PORT_ALT3_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_EMIOS0_E0UC_13_H_OUT |
PORT2_ADC_0_ADC0_MA_2 |
PORT3_DSPI_1_dCS4 |
PORT4_EMIOS0_E0UC_24_X_OUT |
PORT10_LIN_2_LIN2TX |
PORT12_EMIOS0_E0UC_26_Y_OUT |
PORT13_EMIOS0_E0UC_25_Y_OUT |
PORT14_EMIOS0_E0UC_0_X_OUT |
PORT15_EMIOS0_E0UC_1_G_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(10) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_LIN_0_LIN0TX |
PORT18_EMIOS0_E0UC_30_Y_OUT |
PORT19_EMIOS0_E0UC_8_X_OUT |
PORT26_CMP2_CMP2_O |
PORT28_HSM_DO1 |
PORT30_FlexRay_FR_DBG_1 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(10) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14)
          ),
/* Pads  32 ...  47 : PORT38_EMIOS0_E0UC_17_Y_OUT |
PORT39_EMIOS0_E0UC_18_Y_OUT |
PORT41_SSCM_SSCM_DBG_7 |
PORT42_ADC_0_ADC0_MA_1 |
PORT45_FlexRay_FR_DBG_1 */
  (uint16)( SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(13)
          ),
/* Pads  48 ...  63 : PORT60_HSM_DO0 |
PORT61_ENET0_ENET0_TMR0_OUT |
PORT62_FlexRay_FR_DBG_0 |
PORT63_FlexRay_FR_DBG_1 */
  (uint16)( SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  64 ...  79 : PORT65_IIC_1_SDA1_OUT |
PORT68_FlexRay_FR_B_TX |
PORT69_ADC_0_ADC0_MA_2 |
PORT70_ADC_0_ADC0_MA_1 |
PORT71_ADC_0_ADC0_MA_0 |
PORT72_FlexCAN_3_TX |
PORT74_EMIOS1_E1UC_30_Y_OUT |
PORT75_CGM_CLKOUT1 |
PORT79_SPI_2_SCLK_2_OUT */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT81_SPI_0_CS3_0 |
PORT85_SPI_0_CS2_0 |
PORT88_FlexCAN_2_TX |
PORT89_EMIOS0_E0UC_14_H_OUT |
PORT90_EMIOS1_E1UC_2_H_OUT |
PORT91_EMIOS0_E0UC_20_Y_OUT |
PORT92_EMIOS0_E0UC_16_X_OUT |
PORT94_FlexCAN_1_TX */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(5) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14)
          ),
/* Pads  96 ... 111 : PORT96_ENET0_MII_RMII_0_MDC |
PORT98_FlexCAN_7_TX |
PORT100_LIN_10_LIN10TX |
PORT102_CGM_CLKOUT1 |
PORT103_CGM_CLKOUT0 |
PORT104_DSPI_2_dCS0 |
PORT105_EMIOS0_E0UC_0_X_OUT |
PORT107_SPI_2_CS0_2 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(2) |
SHL_PAD_U16(4) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(11)
          ),
/* Pads 112 ... 127 : PORT112_ENET0_MII_RMII_0_TXD_1 |
PORT115_ENET0_MII_0_TX_ER |
PORT116_IIC_3_SCL3_OUT |
PORT118_ADC_0_ADC0_MA_2 |
PORT119_ADC_0_ADC0_MA_1 |
PORT120_ADC_0_ADC0_MA_0 |
PORT123_EMIOS1_E1UC_5_H_OUT |
PORT124_EMIOS1_E1UC_25_Y_OUT |
PORT125_EMIOS1_E1UC_26_Y_OUT |
PORT126_EMIOS1_E1UC_27_Y_OUT |
PORT127_EMIOS1_E1UC_17_Y_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 128 ... 143 : PORT128_IIC_1_SDA1_OUT |
PORT130_IIC_2_SDA2_OUT |
PORT133_SPI_1_CS2_1 |
PORT134_SPI_1_CS0_1 |
PORT135_SPI_1_CS1_1 |
PORT143_SAI2_SAI2_MCLK_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(2) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(15)
          ),
/* Pads 144 ... 159 : PORT144_SAI2_SAI2_SYNC_OUT |
PORT146_SPI_3_CS0_3 |
PORT147_SPI_3_CS1_3 |
PORT157_EMIOS1_E1UC_15_H_OUT |
PORT158_SPI_3_CS2_3 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14)
          )
}
,
/*  Mode PORT_ALT4_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT13_FlexCAN_0_TX |
PORT14_EMIOS0_E0UC_23_X_OUT |
PORT15_EMIOS0_E0UC_21_Y_OUT */
  (uint16)( SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_EMIOS0_E0UC_4_G_OUT |
PORT26_SAI0_SAI0_SYNC_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(10)
          ),
/* Pads  32 ...  47 : PORT34_SSCM_SSCM_DBG_0 |
PORT35_SSCM_SSCM_DBG_1 |
PORT37_FlexRay_FR_A_TX |
PORT38_SSCM_SSCM_DBG_4 |
PORT39_SSCM_SSCM_DBG_5 |
PORT40_SSCM_SSCM_DBG_6 |
PORT42_CMP0_CMP0_O |
PORT46_FlexRay_FR_DBG_2 |
PORT47_FlexRay_FR_DBG_3 */
  (uint16)( SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads  64 ...  79 : PORT70_ADC_1_ADC1_MA_1 |
PORT71_ADC_1_ADC1_MA_0 |
PORT72_IIC_2_SDA2_OUT |
PORT74_IIC_3_SDA3_OUT |
PORT75_IIC_3_SCL3_OUT */
  (uint16)( SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11)
          ),
/* Pads  80 ...  95 : PORT80_FlexCAN_6_TX |
PORT81_SAI0_SAI0_BCLK_OUT |
PORT82_SAI0_SAI0_D3_OUT |
PORT83_SAI0_SAI0_D2_OUT |
PORT84_SAI0_SAI0_D1_OUT |
PORT85_SAI0_SAI0_D0_OUT |
PORT86_SAI1_SAI1_SYNC_OUT |
PORT88_EMIOS0_E0UC_15_H_OUT |
PORT90_EMIOS0_E0UC_19_Y_OUT |
PORT92_FCCU_EOUT1_OUT |
PORT94_ENET0_MII_RMII_0_MDIO_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14)
          ),
/* Pads  96 ... 111 : PORT98_LIN_11_LIN11TX |
PORT102_EMIOS0_E0UC_3_G_OUT |
PORT104_FlexCAN_7_TX |
PORT108_ENET0_MII_0_TXD_2 |
PORT109_ENET0_MII_0_TXD_3 */
  (uint16)( SHL_PAD_U16(2) |
SHL_PAD_U16(6) |
SHL_PAD_U16(8) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13)
          ),
/* Pads 112 ... 127 : PORT113_ENET0_MII_RMII_0_TXD_0 |
PORT114_ENET0_MII_RMII_0_TX_EN |
PORT118_ADC_1_ADC1_MA_2 |
PORT119_SPI_3_CS0_3 |
PORT120_ADC_1_ADC1_MA_0 |
PORT125_FCCU_EOUT1_OUT |
PORT127_FCCU_EOUT0_OUT */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(13) |
SHL_PAD_U16(15)
          ),
/* Pads 128 ... 143 : PORT133_SPI_2_CS2_2 |
PORT134_SPI_2_CS0_2 |
PORT135_SPI_2_CS1_2 */
  (uint16)( SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7)
          ),
/* Pads 144 ... 159 : PORT146_SAI1_SAI1_D0_OUT |
PORT147_SAI1_SAI1_BCLK_OUT |
PORT158_FlexCAN_6_TX */
  (uint16)( SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(14)
          )
}
,
/*  Mode PORT_ALT5_FUNC_MODE: */
{
/* Pads 0 ... 15 */
  (uint16)0x0000,
/* Pads  16 ...  31 : PORT26_EMIOS0_E0UC_29_Y_OUT */
  (uint16)( SHL_PAD_U16(10)
          ),
/* Pads  32 ...  47 : PORT36_SSCM_SSCM_DBG_2 |
PORT46_FlexCAN_4_TX */
  (uint16)( SHL_PAD_U16(4) |
SHL_PAD_U16(14)
          ),
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads  64 ...  79 : PORT72_LIN_6_LIN6TX */
  (uint16)( SHL_PAD_U16(8)
          ),
/* Pads  80 ...  95 : PORT86_EMIOS0_E0UC_30_Y_OUT |
PORT90_FCCU_EOUT0_OUT */
  (uint16)( SHL_PAD_U16(6) |
SHL_PAD_U16(10)
          ),
/* Pads 96 ... 111 */
  (uint16)0x0000,
/* Pads 112 ... 127 : PORT119_ADC_1_ADC1_MA_1 */
  (uint16)( SHL_PAD_U16(7)
          ),
/* Pads 128 ... 143 : PORT134_HSM_DO0 |
PORT135_HSM_DO1 */
  (uint16)( SHL_PAD_U16(6) |
SHL_PAD_U16(7)
          ),
/* Pads 144 ... 159 */
  (uint16)0x0000
}
,
/*  Mode PORT_ALT6_FUNC_MODE: */
{
/* Pads 0 ... 15 */
  (uint16)0x0000,
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads  32 ...  47 : PORT42_LIN_6_LIN6TX */
  (uint16)( SHL_PAD_U16(10)
          ),
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads 64 ... 79 */
  (uint16)0x0000,
/* Pads  80 ...  95 : PORT87_SAI1_SAI1_MCLK_OUT */
  (uint16)( SHL_PAD_U16(7)
          ),
/* Pads 96 ... 111 */
  (uint16)0x0000,
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 */
  (uint16)0x0000,
/* Pads 144 ... 159 : PORT158_EMIOS1_E1UC_14_H_OUT */
  (uint16)( SHL_PAD_U16(14)
          )
}
,
/*  Mode PORT_ALT7_FUNC_MODE: */
{
/* Pads 0 ... 15 */
  (uint16)0x0000,
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads  32 ...  47 : PORT37_SSCM_SSCM_DBG_3 */
  (uint16)( SHL_PAD_U16(5)
          ),
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads 64 ... 79 */
  (uint16)0x0000,
/* Pads  80 ...  95 : PORT80_SAI0_SAI0_MCLK_OUT */
  (uint16)( SHL_PAD_U16(0)
          ),
/* Pads 96 ... 111 */
  (uint16)0x0000,
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 */
  (uint16)0x0000,
/* Pads 144 ... 159 */
  (uint16)0x0000
}
,
/*  Mode PORT_ONLY_OUTPUT_MODE: */
{
/* Pads 0 ... 15 */
  (uint16)0x0000,
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads 32 ... 47 */
  (uint16)0x0000,
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads 64 ... 79 */
  (uint16)0x0000,
/* Pads 80 ... 95 */
  (uint16)0x0000,
/* Pads  96 ... 111 : PORT102_PMCDIG_EXTREGC */
  (uint16)( SHL_PAD_U16(6)
          ),
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 */
  (uint16)0x0000,
/* Pads 144 ... 159 */
  (uint16)0x0000
}
,
/*  Mode PORT_ONLY_INPUT_MODE: */
{
/* Pads   0 ...  15 : PORT0_WKPU_WKPU_19 |
PORT1_WKPU_WKPU_2 |
PORT1_WKPU_NMI_0 |
PORT2_WKPU_WKPU_3 |
PORT4_WKPU_WKPU_9 |
PORT15_WKPU_WKPU_10 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(4) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT17_WKPU_WKPU_4 |
PORT19_WKPU_WKPU_11 |
PORT20_GPI |
PORT21_GPI |
PORT22_GPI |
PORT23_GPI |
PORT24_GPI |
PORT24_WKPU_WKPU_25 |
PORT24_XOSC_OSC32K_XTAL |
PORT25_GPI |
PORT25_WKPU_WKPU_26 |
PORT25_XOSC_OSC32K_EXTAL |
PORT26_WKPU_WKPU_8 */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(8) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(9) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10)
          ),
/* Pads  32 ...  47 : PORT39_WKPU_WKPU_12 |
PORT41_WKPU_WKPU_13 |
PORT43_WKPU_WKPU_5 */
  (uint16)( SHL_PAD_U16(7) |
SHL_PAD_U16(9) |
SHL_PAD_U16(11)
          ),
/* Pads  48 ...  63 : PORT48_GPI |
PORT48_WKPU_WKPU_27 |
PORT49_GPI |
PORT49_WKPU_WKPU_28 |
PORT50_GPI |
PORT51_GPI |
PORT52_GPI |
PORT53_GPI |
PORT54_GPI |
PORT55_GPI |
PORT56_GPI |
PORT57_GPI |
PORT58_GPI */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10)
          ),
/* Pads  64 ...  79 : PORT64_WKPU_WKPU_6 |
PORT67_WKPU_WKPU_29 |
PORT69_WKPU_WKPU_30 |
PORT73_WKPU_WKPU_7 |
PORT75_WKPU_WKPU_14 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(3) |
SHL_PAD_U16(5) |
SHL_PAD_U16(9) |
SHL_PAD_U16(11)
          ),
/* Pads  80 ...  95 : PORT89_WKPU_WKPU_22 |
PORT90_FCCU_EOUT0_IN |
PORT91_WKPU_WKPU_15 |
PORT92_FCCU_EOUT1_IN |
PORT93_WKPU_WKPU_16 */
  (uint16)( SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13)
          ),
/* Pads  96 ... 111 : PORT99_WKPU_WKPU_17 |
PORT101_WKPU_WKPU_18 |
PORT103_WKPU_WKPU_20 |
PORT105_WKPU_WKPU_21 */
  (uint16)( SHL_PAD_U16(3) |
SHL_PAD_U16(5) |
SHL_PAD_U16(7) |
SHL_PAD_U16(9)
          ),
/* Pads 112 ... 127 : PORT122_DCI_TMS_IN |
PORT125_FCCU_EOUT1_IN |
PORT127_FCCU_EOUT0_IN */
  (uint16)( SHL_PAD_U16(10) |
SHL_PAD_U16(13) |
SHL_PAD_U16(15)
          ),
/* Pads 128 ... 143 : PORT129_WKPU_WKPU_24 |
PORT131_WKPU_WKPU_23 */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(3)
          ),
/* Pads 144 ... 159 : PORT157_WKPU_WKPU_31 */
  (uint16)( SHL_PAD_U16(13)
          )
}
,
/*  Mode PORT_ANALOG_INPUT_MODE: */
{
/* Pads   0 ...  15 : PORT3_ADC_1_ADC1_S_0 |
PORT4_CMP1_CMP1_13 |
PORT7_ADC_1_ADC1_S_8 |
PORT8_ADC_1_ADC1_S_9 |
PORT9_ADC_1_ADC1_S_10 |
PORT10_ADC_1_ADC1_S_11 |
PORT11_ADC_1_ADC1_S_12 |
PORT12_CMP1_CMP1_15 |
PORT13_CMP1_CMP1_14 |
PORT14_CMP1_CMP1_12 |
PORT15_CMP1_CMP1_10 */
  (uint16)( SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_CMP0_CMP0_2 |
PORT17_CMP0_CMP0_3 |
PORT20_ADC_1_ADC1_P_0 |
PORT21_ADC_1_ADC1_P_1 |
PORT22_ADC_1_ADC1_P_2 |
PORT23_ADC_1_ADC1_P_3 |
PORT24_ADC_0_ADC0_S_0 |
PORT25_ADC_0_ADC0_S_1 |
PORT26_ADC_0_ADC0_S_2 |
PORT27_ADC_0_ADC0_S_3 |
PORT28_ADC_0_ADC0_X_0 |
PORT29_ADC_0_ADC0_X_1 |
PORT30_ADC_0_ADC0_X_2 |
PORT31_ADC_0_ADC0_X_3 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  32 ...  47 : PORT38_CMP0_CMP0_7 */
  (uint16)( SHL_PAD_U16(6)
          ),
/* Pads  48 ...  63 : PORT48_ADC_1_ADC1_P_4 |
PORT49_ADC_1_ADC1_P_5 |
PORT50_ADC_1_ADC1_P_6 |
PORT51_ADC_1_ADC1_P_7 |
PORT52_ADC_1_ADC1_P_8 |
PORT53_ADC_1_ADC1_P_9 |
PORT54_ADC_1_ADC1_P_10 |
PORT55_ADC_1_ADC1_P_11 |
PORT56_ADC_1_ADC1_P_12 |
PORT57_ADC_1_ADC1_P_13 |
PORT58_ADC_1_ADC1_P_14 |
PORT60_ADC_0_ADC0_S_4 |
PORT61_ADC_0_ADC0_S_5 |
PORT62_ADC_0_ADC0_S_6 |
PORT63_ADC_0_ADC0_S_7 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  64 ...  79 : PORT76_ADC_1_ADC1_S_13 |
PORT77_ADC_1_ADC1_X_3 */
  (uint16)( SHL_PAD_U16(12) |
SHL_PAD_U16(13)
          ),
/* Pads  80 ...  95 : PORT80_ADC_0_ADC0_S_8 |
PORT80_CMP2_CMP2_16 |
PORT81_ADC_0_ADC0_S_9 |
PORT81_CMP2_CMP2_17 |
PORT82_ADC_0_ADC0_S_10 |
PORT82_CMP2_CMP2_18 |
PORT83_ADC_0_ADC0_S_11 |
PORT83_CMP2_CMP2_19 |
PORT84_ADC_0_ADC0_S_12 |
PORT84_CMP2_CMP2_20 |
PORT85_ADC_0_ADC0_S_13 |
PORT85_CMP2_CMP2_21 |
PORT86_ADC_0_ADC0_S_14 |
PORT86_CMP2_CMP2_22 |
PORT87_ADC_0_ADC0_S_15 |
PORT87_CMP2_CMP2_23 |
PORT88_CMP0_CMP0_5 |
PORT89_CMP0_CMP0_4 |
PORT90_CMP1_CMP1_8 |
PORT91_CMP1_CMP1_9 |
PORT92_CMP0_CMP0_6 |
PORT93_CMP1_CMP1_11 |
PORT94_ADC_1_ADC1_X_2 |
PORT95_ADC_1_ADC1_X_1 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT96_ADC_1_ADC1_X_0 |
PORT97_ADC_1_ADC1_S_7 |
PORT102_CMP0_CMP0_1 |
PORT103_CMP0_CMP0_0 |
PORT108_ADC_1_ADC1_S_2 |
PORT109_ADC_1_ADC1_S_1 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13)
          ),
/* Pads 112 ... 127 : PORT112_ADC_1_ADC1_S_3 |
PORT113_ADC_1_ADC1_S_4 |
PORT114_ADC_1_ADC1_S_5 |
PORT115_ADC_1_ADC1_S_6 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3)
          ),
/* Pads 128 ... 143 : PORT136_ADC_0_ADC0_S_16 |
PORT139_ADC_0_ADC0_S_19 |
PORT140_ADC_0_ADC0_S_20 |
PORT141_ADC_0_ADC0_S_21 |
PORT142_ADC_0_ADC0_S_22 |
PORT143_ADC_0_ADC0_S_23 */
  (uint16)( SHL_PAD_U16(8) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 144 ... 159 : PORT144_ADC_0_ADC0_S_24 |
PORT145_ADC_0_ADC0_S_25 |
PORT146_ADC_0_ADC0_S_26 |
PORT147_ADC_0_ADC0_S_27 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3)
          )
}
,
/*  Mode PORT_INPUT1_MODE: */
{
/* Pads   0 ...  15 : PORT0_EMIOS0_E0UC_0_X_IN |
PORT1_EMIOS0_E0UC_1_G_IN |
PORT2_EMIOS0_E0UC_2_G_IN |
PORT3_EMIOS0_E0UC_3_G_IN |
PORT4_EMIOS0_E0UC_4_G_IN |
PORT5_EMIOS0_E0UC_5_G_IN |
PORT6_EMIOS0_E0UC_6_G_IN |
PORT7_EMIOS0_E0UC_7_G_IN |
PORT8_EMIOS0_E0UC_8_X_IN |
PORT9_EMIOS0_E0UC_9_H_IN |
PORT10_EMIOS0_E0UC_10_H_IN |
PORT11_EMIOS0_E0UC_11_H_IN |
PORT12_EMIOS0_E0UC_28_Y_IN |
PORT13_EMIOS0_E0UC_29_Y_IN |
PORT14_EMIOS0_E0UC_0_X_IN |
PORT15_EMIOS0_E0UC_1_G_IN */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_EMIOS0_E0UC_30_Y_IN |
PORT17_EMIOS0_E0UC_31_Y_IN |
PORT18_EMIOS0_E0UC_30_Y_IN |
PORT19_EMIOS0_E0UC_31_Y_IN |
PORT26_FlexCAN_6_RX |
PORT27_EMIOS0_E0UC_3_G_IN |
PORT28_EMIOS0_E0UC_4_G_IN |
PORT29_EMIOS0_E0UC_5_G_IN |
PORT30_EMIOS0_E0UC_6_G_IN |
PORT31_EMIOS0_E0UC_7_G_IN */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  32 ...  47 : PORT34_SIUL2_EIRQ5 |
PORT35_SIUL2_EIRQ6 |
PORT36_EMIOS1_E1UC_31_Y_IN |
PORT37_SIUL2_EIRQ7 |
PORT38_EMIOS1_E1UC_28_Y_IN |
PORT39_EMIOS1_E1UC_29_Y_IN |
PORT40_EMIOS0_E0UC_3_G_IN |
PORT41_EMIOS0_E0UC_7_G_IN |
PORT43_FlexCAN_1_RX |
PORT44_EMIOS0_E0UC_12_H_IN |
PORT45_EMIOS0_E0UC_13_H_IN |
PORT46_EMIOS0_E0UC_14_H_IN |
PORT47_EMIOS0_E0UC_15_H_IN */
  (uint16)( SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  48 ...  63 : PORT60_EMIOS0_E0UC_24_X_IN |
PORT61_EMIOS0_E0UC_25_Y_IN |
PORT62_EMIOS0_E0UC_26_Y_IN |
PORT63_EMIOS0_E0UC_27_Y_IN */
  (uint16)( SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  64 ...  79 : PORT64_EMIOS0_E0UC_16_X_IN |
PORT65_EMIOS0_E0UC_17_Y_IN |
PORT66_EMIOS0_E0UC_18_Y_IN |
PORT67_EMIOS0_E0UC_19_Y_IN |
PORT68_EMIOS0_E0UC_20_Y_IN |
PORT69_EMIOS0_E0UC_21_Y_IN |
PORT70_EMIOS0_E0UC_22_X_IN |
PORT71_EMIOS0_E0UC_23_X_IN |
PORT72_EMIOS0_E0UC_22_X_IN |
PORT73_EMIOS0_E0UC_23_X_IN |
PORT74_EMIOS1_E1UC_30_Y_IN |
PORT75_EMIOS0_E0UC_24_X_IN |
PORT76_EMIOS1_E1UC_19_Y_IN |
PORT77_EMIOS1_E1UC_20_Y_IN |
PORT78_EMIOS1_E1UC_21_Y_IN |
PORT79_EMIOS1_E1UC_22_X_IN */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT80_EMIOS0_E0UC_10_H_IN |
PORT81_EMIOS0_E0UC_11_H_IN |
PORT82_EMIOS0_E0UC_12_H_IN |
PORT83_EMIOS0_E0UC_13_H_IN |
PORT84_EMIOS0_E0UC_14_H_IN |
PORT85_EMIOS0_E0UC_22_X_IN |
PORT86_EMIOS0_E0UC_23_X_IN |
PORT87_SPI_0_SCLK_0_IN |
PORT88_EMIOS0_E0UC_15_H_IN |
PORT89_EMIOS1_E1UC_1_H_IN |
PORT90_EMIOS1_E1UC_2_H_IN |
PORT91_EMIOS1_E1UC_3_H_IN |
PORT92_EMIOS1_E1UC_25_Y_IN |
PORT93_EMIOS1_E1UC_26_Y_IN |
PORT94_EMIOS1_E1UC_27_Y_IN |
PORT95_EMIOS1_E1UC_4_H_IN */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT96_EMIOS1_E1UC_23_X_IN |
PORT97_EMIOS1_E1UC_24_X_IN |
PORT98_EMIOS1_E1UC_11_H_IN |
PORT99_EMIOS1_E1UC_12_H_IN |
PORT100_EMIOS1_E1UC_13_H_IN |
PORT101_EMIOS1_E1UC_14_H_IN |
PORT102_EMIOS1_E1UC_15_H_IN |
PORT103_EMIOS1_E1UC_16_X_IN |
PORT104_EMIOS1_E1UC_17_Y_IN |
PORT105_EMIOS1_E1UC_18_Y_IN |
PORT106_EMIOS0_E0UC_24_X_IN |
PORT107_EMIOS0_E0UC_25_Y_IN |
PORT108_EMIOS0_E0UC_26_Y_IN |
PORT109_EMIOS0_E0UC_27_Y_IN |
PORT110_EMIOS1_E1UC_0_X_IN |
PORT111_EMIOS1_E1UC_1_H_IN */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 112 ... 127 : PORT112_EMIOS1_E1UC_2_H_IN |
PORT113_EMIOS1_E1UC_3_H_IN |
PORT114_EMIOS1_E1UC_4_H_IN |
PORT115_EMIOS1_E1UC_5_H_IN |
PORT116_EMIOS1_E1UC_6_H_IN |
PORT117_EMIOS1_E1UC_7_H_IN |
PORT118_EMIOS1_E1UC_8_X_IN |
PORT119_EMIOS1_E1UC_9_H_IN |
PORT120_EMIOS1_E1UC_10_H_IN |
PORT123_EMIOS1_E1UC_5_H_IN |
PORT124_EMIOS1_E1UC_25_Y_IN |
PORT125_EMIOS1_E1UC_26_Y_IN |
PORT126_EMIOS1_E1UC_27_Y_IN |
PORT127_EMIOS1_E1UC_17_Y_IN */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 128 ... 143 : PORT128_EMIOS0_E0UC_28_Y_IN |
PORT129_EMIOS0_E0UC_29_Y_IN |
PORT130_EMIOS0_E0UC_30_Y_IN |
PORT131_EMIOS0_E0UC_31_Y_IN |
PORT132_EMIOS1_E1UC_28_Y_IN |
PORT133_EMIOS1_E1UC_29_Y_IN |
PORT134_EMIOS1_E1UC_30_Y_IN |
PORT135_EMIOS1_E1UC_31_Y_IN |
PORT139_DSPI_3_dSIN |
PORT140_DSPI_2_dSS |
PORT142_SPI_0_SIN_0 |
PORT143_SPI_0_SS_0 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 144 ... 159 : PORT144_SAI2_SAI2_SYNC_IN |
PORT145_SPI_1_SIN_1 |
PORT146_SPI_1_SS_1 |
PORT147_SAI1_SAI1_BCLK_IN |
PORT148_EMIOS1_E1UC_18_Y_IN |
PORT157_EMIOS1_E1UC_15_H_IN |
PORT158_EMIOS1_E1UC_14_H_IN */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14)
          )
}
,
/*  Mode PORT_INPUT2_MODE: */
{
/* Pads   0 ...  15 : PORT0_EMIOS0_E0UC_13_H_IN |
PORT1_FlexCAN_3_RX |
PORT3_SIUL2_EIRQ0 |
PORT4_LIN_5_LIN5RX |
PORT6_SIUL2_EIRQ1 |
PORT7_SIUL2_EIRQ2 |
PORT8_EMIOS0_E0UC_14_H_IN |
PORT9_ENET0_MII_RMII_0_RXD_0 |
PORT10_IIC_0_SDA0_IN |
PORT11_SIUL2_EIRQ16 |
PORT12_SIUL2_EIRQ17 |
PORT13_EMIOS0_E0UC_25_Y_IN |
PORT14_SIUL2_EIRQ4 |
PORT15_FlexCAN_0_RX */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_EMIOS0_E0UC_4_G_IN |
PORT17_FlexCAN_0_RX |
PORT18_IIC_0_SDA0_IN |
PORT19_LIN_0_LIN0RX |
PORT26_SAI0_SAI0_SYNC_IN |
PORT27_DSPI_0_dSS */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11)
          ),
/* Pads  32 ...  47 : PORT34_DSPI_1_dSCLK_IN |
PORT35_FlexCAN_1_RX |
PORT36_SIUL2_EIRQ18 |
PORT38_EMIOS0_E0UC_17_Y_IN |
PORT39_LIN_1_LIN1RX |
PORT41_LIN_2_LIN2RX |
PORT43_FlexCAN_4_RX |
PORT44_SIUL2_EIRQ19 |
PORT46_SIUL2_EIRQ8 |
PORT47_SIUL2_EIRQ20 */
  (uint16)( SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(9) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  48 ...  63 : PORT61_DSPI_1_dSS */
  (uint16)( SHL_PAD_U16(13)
          ),
/* Pads  64 ...  79 : PORT64_FlexCAN_5_RX |
PORT65_IIC_1_SDA1_IN |
PORT66_SIUL2_EIRQ21 |
PORT67_FlexRay_FR_A_RX |
PORT68_SIUL2_EIRQ9 |
PORT69_FlexRay_FR_B_RX |
PORT70_SIUL2_EIRQ22 |
PORT71_SIUL2_EIRQ23 |
PORT72_IIC_2_SDA2_IN |
PORT73_FlexCAN_2_RX |
PORT74_SIUL2_EIRQ10 |
PORT75_LIN_3_LIN3RX |
PORT76_SIUL2_EIRQ11 |
PORT77_ENET0_MII_0_RXD_3 |
PORT78_SIUL2_EIRQ12 |
PORT79_DSPI_2_dSS */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT80_SAI0_SAI0_MCLK_IN |
PORT81_SAI0_SAI0_BCLK_IN |
PORT82_DSPI_2_dSS |
PORT83_SAI0_SAI0_D2_IN |
PORT84_SAI0_SAI0_D1_IN |
PORT85_SAI0_SAI0_D0_IN |
PORT86_SAI1_SAI1_SYNC_IN |
PORT87_SAI1_SAI1_MCLK_IN |
PORT89_FlexCAN_2_RX |
PORT90_EMIOS0_E0UC_19_Y_IN |
PORT91_LIN_4_LIN4RX |
PORT92_EMIOS0_E0UC_16_X_IN |
PORT93_LIN_5_LIN5RX |
PORT94_ENET0_MII_RMII_0_MDIO_IN |
PORT95_SIUL2_EIRQ13 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT97_SIUL2_EIRQ14 |
PORT99_FlexCAN_7_RX |
PORT100_DSPI_3_dSCLK_IN |
PORT101_LIN_10_LIN10RX |
PORT102_EMIOS0_E0UC_3_G_IN |
PORT103_EMIOS1_E1UC_30_Y_IN |
PORT104_SIUL2_EIRQ15 |
PORT105_FlexCAN_7_RX |
PORT106_EMIOS1_E1UC_31_Y_IN |
PORT107_SPI_0_SS_0 |
PORT109_SPI_0_SCLK_0_IN |
PORT110_SPI_2_SIN_2 |
PORT111_LIN_8_LIN8RX */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 112 ... 127 : PORT112_DSPI_1_dSIN |
PORT114_DSPI_1_dSCLK_IN |
PORT115_DSPI_1_dSS |
PORT116_IIC_3_SCL3_IN |
PORT117_IIC_3_SDA3_IN |
PORT118_SPI_3_SCLK_3_IN |
PORT119_SPI_3_SS_3 |
PORT123_SPI_0_SS_0 |
PORT124_DSPI_3_dSCLK_IN |
PORT125_DSPI_3_dSS |
PORT126_SPI_0_SCLK_0_IN */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14)
          ),
/* Pads 128 ... 143 : PORT128_IIC_1_SDA1_IN |
PORT129_LIN_8_LIN8RX |
PORT130_IIC_2_SDA2_IN |
PORT131_LIN_9_LIN9RX |
PORT132_GLITCH_FILTER2_INP |
PORT133_SPI_0_SCLK_0_IN |
PORT134_SPI_0_SS_0 |
PORT135_GLITCH_FILTER3_INP |
PORT139_ENET0_ENET0_TMR1_IN |
PORT140_DSPI_3_dSS |
PORT142_SAI2_SAI2_D0_IN |
PORT143_SAI2_SAI2_MCLK_IN */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 144 ... 159 : PORT145_SAI2_SAI2_BCLK_IN |
PORT146_SPI_2_SS_2 |
PORT148_SPI_1_SCLK_1_IN |
PORT157_FlexCAN_1_RX */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(4) |
SHL_PAD_U16(13)
          )
}
,
/*  Mode PORT_INPUT3_MODE: */
{
/* Pads   0 ...  15 : PORT0_FlexCAN_1_RX |
PORT3_ENET0_MII_0_RX_CLK |
PORT4_DSPI_1_dSS |
PORT6_LIN_4_LIN4RX |
PORT7_ENET0_MII_0_RXD_2 |
PORT8_SIUL2_EIRQ3 |
PORT10_DSPI_1_dSIN |
PORT11_LIN_2_LIN2RX |
PORT12_DSPI_0_dSIN |
PORT13_GLITCH_FILTER0_INP |
PORT14_DSPI_0_dSCLK_IN |
PORT15_DSPI_0_dSCLK_IN */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_GLITCH_FILTER1_INP |
PORT17_LIN_0_LIN0RX |
PORT18_GLITCH_FILTER1_INP |
PORT19_IIC_0_SCL0_IN |
PORT26_EMIOS0_E0UC_29_Y_IN */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(10)
          ),
/* Pads  32 ...  47 : PORT35_FlexCAN_4_RX |
PORT36_FlexCAN_3_RX |
PORT38_GLITCH_FILTER2_INP |
PORT39_EMIOS0_E0UC_18_Y_IN |
PORT43_EMIOS0_E0UC_1_G_IN |
PORT44_DSPI_2_dSIN |
PORT46_DSPI_2_dSCLK_IN |
PORT47_DSPI_2_dSS */
  (uint16)( SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  48 ...  63 : PORT61_ENET0_ENET0_TMR0_IN */
  (uint16)( SHL_PAD_U16(13)
          ),
/* Pads  64 ...  79 : PORT64_LIN_11_LIN11RX |
PORT66_DSPI_1_dSIN |
PORT68_DSPI_1_dSCLK_IN |
PORT69_DSPI_1_dSS |
PORT73_FlexCAN_3_RX |
PORT74_IIC_3_SDA3_IN |
PORT75_IIC_3_SCL3_IN |
PORT76_DSPI_2_dSIN |
PORT78_DSPI_2_dSCLK_IN |
PORT79_SPI_2_SCLK_2_IN */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(2) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT82_SAI0_SAI0_D3_IN |
PORT83_GLITCH_FILTER1_INP |
PORT84_GLITCH_FILTER2_INP |
PORT85_GLITCH_FILTER3_INP |
PORT86_EMIOS0_E0UC_30_Y_IN |
PORT89_FlexCAN_3_RX |
PORT91_EMIOS0_E0UC_20_Y_IN |
PORT93_EMIOS0_E0UC_22_X_IN |
PORT95_FlexCAN_1_RX */
  (uint16)( SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(9) |
SHL_PAD_U16(11) |
SHL_PAD_U16(13) |
SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT97_FlexCAN_5_RX |
PORT99_DSPI_3_dSS |
PORT101_DSPI_3_dSIN |
PORT103_LIN_6_LIN6RX |
PORT104_DSPI_2_dSS |
PORT105_LIN_7_LIN7RX |
PORT106_SPI_0_SIN_0 |
PORT107_SPI_2_SS_2 */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(3) |
SHL_PAD_U16(5) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11)
          ),
/* Pads 112 ... 127 : PORT117_SPI_3_SIN_3 |
PORT126_FCCU_EIN_ERR */
  (uint16)( SHL_PAD_U16(5) |
SHL_PAD_U16(14)
          ),
/* Pads 128 ... 143 : PORT128_GLITCH_FILTER0_INP |
PORT129_IIC_1_SCL1_IN |
PORT130_GLITCH_FILTER1_INP |
PORT131_IIC_2_SCL2_IN |
PORT133_GLITCH_FILTER2_INP |
PORT134_SPI_1_SS_1 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6)
          ),
/* Pads 144 ... 159 : PORT146_SPI_3_SS_3 |
PORT148_FCCU_EIN_ERR |
PORT157_FlexCAN_4_RX */
  (uint16)( SHL_PAD_U16(2) |
SHL_PAD_U16(4) |
SHL_PAD_U16(13)
          )
}
,
/*  Mode PORT_INPUT4_MODE: */
{
/* Pads   0 ...  15 : PORT4_EMIOS0_E0UC_24_X_IN |
PORT8_LIN_3_LIN3RX |
PORT10_ENET0_MII_0_COL |
PORT11_IIC_0_SCL0_IN |
PORT12_EMIOS0_E0UC_26_Y_IN |
PORT14_DSPI_0_dSS |
PORT15_DSPI_0_dSS */
  (uint16)( SHL_PAD_U16(4) |
SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT17_EMIOS0_E0UC_5_G_IN |
PORT19_EMIOS0_E0UC_8_X_IN */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(3)
          ),
/* Pads  32 ...  47 : PORT35_DSPI_1_dSS |
PORT36_DSPI_1_dSIN |
PORT39_GLITCH_FILTER2_INP |
PORT47_FlexCAN_4_RX */
  (uint16)( SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(7) |
SHL_PAD_U16(15)
          ),
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads  64 ...  79 : PORT64_IIC_1_SCL1_IN |
PORT73_IIC_2_SCL2_IN |
PORT74_GLITCH_FILTER3_INP |
PORT76_ENET0_MII_0_CRS */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(12)
          ),
/* Pads  80 ...  95 : PORT82_GLITCH_FILTER0_INP |
PORT89_EMIOS0_E0UC_14_H_IN |
PORT95_FlexCAN_4_RX */
  (uint16)( SHL_PAD_U16(2) |
SHL_PAD_U16(9) |
SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT97_ENET0_MII_RMII_0_TX_CLK_IN |
PORT101_EMIOS0_E0UC_2_G_IN |
PORT103_GLITCH_FILTER3_INP |
PORT105_DSPI_2_dSCLK_IN |
PORT106_GLITCH_FILTER3_INP */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(5) |
SHL_PAD_U16(7) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10)
          ),
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 : PORT129_GLITCH_FILTER0_INP |
PORT131_GLITCH_FILTER1_INP |
PORT134_SPI_2_SS_2 */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(3) |
SHL_PAD_U16(6)
          ),
/* Pads 144 ... 159 : PORT146_SAI1_SAI1_D0_IN |
PORT157_FlexCAN_6_RX */
  (uint16)( SHL_PAD_U16(2) |
SHL_PAD_U16(13)
          )
}
,
/*  Mode PORT_INPUT5_MODE: */
{
/* Pads   0 ...  15 : PORT8_ENET0_MII_RMII_0_RXD_1 |
PORT11_ENET0_MII_RMII_0_RX_ER |
PORT12_GLITCH_FILTER0_INP |
PORT14_EMIOS0_E0UC_23_X_IN |
PORT15_EMIOS0_E0UC_21_Y_IN */
  (uint16)( SHL_PAD_U16(8) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT17_GLITCH_FILTER1_INP |
PORT19_GLITCH_FILTER1_INP */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(3)
          ),
/* Pads  32 ...  47 : PORT36_GLITCH_FILTER3_INP */
  (uint16)( SHL_PAD_U16(4)
          ),
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads 64 ... 79 */
  (uint16)0x0000,
/* Pads  80 ...  95 : PORT95_ENET0_MII_RMII_0_RX_DV */
  (uint16)( SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT105_EMIOS0_E0UC_0_X_IN */
  (uint16)( SHL_PAD_U16(9)
          ),
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 : PORT134_GLITCH_FILTER3_INP */
  (uint16)( SHL_PAD_U16(6)
          ),
/* Pads 144 ... 159 */
  (uint16)0x0000
}
,
/*  Mode PORT_INPUT6_MODE: */
{
/* Pads 0 ... 15 */
  (uint16)0x0000,
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads 32 ... 47 */
  (uint16)0x0000,
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads 64 ... 79 */
  (uint16)0x0000,
/* Pads 80 ... 95 */
  (uint16)0x0000,
/* Pads 96 ... 111 */
  (uint16)0x0000,
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 */
  (uint16)0x0000,
/* Pads 144 ... 159 */
  (uint16)0x0000
}
,
/*  Mode PORT_INOUT1_MODE: */
{
/* Pads   0 ...  15 : PORT0_EMIOS0_E0UC_0_X_IN_OUT |
PORT1_EMIOS0_E0UC_1_G_IN_OUT |
PORT2_EMIOS0_E0UC_2_G_IN_OUT |
PORT3_EMIOS0_E0UC_3_G_IN_OUT |
PORT4_EMIOS0_E0UC_4_G_IN_OUT |
PORT5_EMIOS0_E0UC_5_G_IN_OUT |
PORT6_EMIOS0_E0UC_6_G_IN_OUT |
PORT7_EMIOS0_E0UC_7_G_IN_OUT |
PORT8_EMIOS0_E0UC_8_X_IN_OUT |
PORT9_EMIOS0_E0UC_9_H_IN_OUT |
PORT10_EMIOS0_E0UC_10_H_IN_OUT |
PORT11_EMIOS0_E0UC_11_H_IN_OUT |
PORT12_EMIOS0_E0UC_28_Y_IN_OUT |
PORT14_DSPI_0_dSCLK_IN_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14)
          ),
/* Pads  16 ...  31 : PORT17_EMIOS0_E0UC_31_Y_IN_OUT |
PORT19_EMIOS0_E0UC_31_Y_IN_OUT |
PORT27_EMIOS0_E0UC_3_G_IN_OUT |
PORT28_EMIOS0_E0UC_4_G_IN_OUT |
PORT29_EMIOS0_E0UC_5_G_IN_OUT |
PORT30_EMIOS0_E0UC_6_G_IN_OUT |
PORT31_EMIOS0_E0UC_7_G_IN_OUT */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(3) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  32 ...  47 : PORT34_DSPI_1_dSCLK_IN_OUT |
PORT36_EMIOS1_E1UC_31_Y_IN_OUT |
PORT39_EMIOS1_E1UC_29_Y_IN_OUT |
PORT41_EMIOS0_E0UC_7_G_IN_OUT |
PORT44_EMIOS0_E0UC_12_H_IN_OUT |
PORT45_EMIOS0_E0UC_13_H_IN_OUT |
PORT46_EMIOS0_E0UC_14_H_IN_OUT |
PORT47_EMIOS0_E0UC_15_H_IN_OUT */
  (uint16)( SHL_PAD_U16(2) |
SHL_PAD_U16(4) |
SHL_PAD_U16(7) |
SHL_PAD_U16(9) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads  64 ...  79 : PORT64_EMIOS0_E0UC_16_X_IN_OUT |
PORT65_EMIOS0_E0UC_17_Y_IN_OUT |
PORT66_EMIOS0_E0UC_18_Y_IN_OUT |
PORT67_EMIOS0_E0UC_19_Y_IN_OUT |
PORT68_EMIOS0_E0UC_20_Y_IN_OUT |
PORT69_EMIOS0_E0UC_21_Y_IN_OUT |
PORT70_EMIOS0_E0UC_22_X_IN_OUT |
PORT71_EMIOS0_E0UC_23_X_IN_OUT |
PORT73_EMIOS0_E0UC_23_X_IN_OUT |
PORT75_EMIOS0_E0UC_24_X_IN_OUT |
PORT76_EMIOS1_E1UC_19_Y_IN_OUT |
PORT78_DSPI_2_dSCLK_IN_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(9) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14)
          ),
/* Pads  80 ...  95 : PORT80_EMIOS0_E0UC_10_H_IN_OUT |
PORT81_EMIOS0_E0UC_11_H_IN_OUT |
PORT82_EMIOS0_E0UC_12_H_IN_OUT |
PORT83_EMIOS0_E0UC_13_H_IN_OUT |
PORT84_EMIOS0_E0UC_14_H_IN_OUT |
PORT85_EMIOS0_E0UC_22_X_IN_OUT |
PORT86_EMIOS0_E0UC_23_X_IN_OUT |
PORT87_SPI_0_SCLK_0_IN_OUT |
PORT89_EMIOS1_E1UC_1_H_IN_OUT |
PORT92_EMIOS1_E1UC_25_Y_IN_OUT |
PORT93_EMIOS1_E1UC_26_Y_IN_OUT |
PORT95_EMIOS1_E1UC_4_H_IN_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(9) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT97_EMIOS1_E1UC_24_X_IN_OUT |
PORT98_EMIOS1_E1UC_11_H_IN_OUT |
PORT99_EMIOS1_E1UC_12_H_IN_OUT |
PORT100_EMIOS1_E1UC_13_H_IN_OUT |
PORT101_EMIOS1_E1UC_14_H_IN_OUT |
PORT102_EMIOS1_E1UC_15_H_IN_OUT |
PORT103_EMIOS1_E1UC_16_X_IN_OUT |
PORT104_EMIOS1_E1UC_17_Y_IN_OUT |
PORT105_EMIOS1_E1UC_18_Y_IN_OUT |
PORT106_EMIOS0_E0UC_24_X_IN_OUT |
PORT107_EMIOS0_E0UC_25_Y_IN_OUT |
PORT108_EMIOS0_E0UC_26_Y_IN_OUT |
PORT109_EMIOS0_E0UC_27_Y_IN_OUT |
PORT110_EMIOS1_E1UC_0_X_IN_OUT |
PORT111_EMIOS1_E1UC_1_H_IN_OUT */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 112 ... 127 : PORT112_EMIOS1_E1UC_2_H_IN_OUT |
PORT113_EMIOS1_E1UC_3_H_IN_OUT |
PORT114_EMIOS1_E1UC_4_H_IN_OUT |
PORT115_EMIOS1_E1UC_5_H_IN_OUT |
PORT116_EMIOS1_E1UC_6_H_IN_OUT |
PORT117_EMIOS1_E1UC_7_H_IN_OUT |
PORT118_EMIOS1_E1UC_8_X_IN_OUT |
PORT119_EMIOS1_E1UC_9_H_IN_OUT |
PORT120_EMIOS1_E1UC_10_H_IN_OUT |
PORT122_DCI_TMS_IN_OUT |
PORT124_DSPI_3_dSCLK_IN_OUT |
PORT126_SPI_0_SCLK_0_IN_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14)
          ),
/* Pads 128 ... 143 : PORT128_EMIOS0_E0UC_28_Y_IN_OUT |
PORT129_EMIOS0_E0UC_29_Y_IN_OUT |
PORT130_EMIOS0_E0UC_30_Y_IN_OUT |
PORT131_EMIOS0_E0UC_31_Y_IN_OUT |
PORT132_EMIOS1_E1UC_28_Y_IN_OUT |
PORT133_EMIOS1_E1UC_29_Y_IN_OUT |
PORT134_EMIOS1_E1UC_30_Y_IN_OUT |
PORT135_EMIOS1_E1UC_31_Y_IN_OUT |
PORT142_SAI2_SAI2_D0_IN_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(14)
          ),
/* Pads 144 ... 159 : PORT148_SPI_1_SCLK_1_IN_OUT */
  (uint16)( SHL_PAD_U16(4)
          )
}
,
/*  Mode PORT_INOUT2_MODE: */
{
/* Pads   0 ...  15 : PORT8_EMIOS0_E0UC_14_H_IN_OUT |
PORT10_IIC_0_SDA0_IN_OUT |
PORT11_IIC_0_SCL0_IN_OUT |
PORT13_EMIOS0_E0UC_29_Y_IN_OUT |
PORT15_DSPI_0_dSCLK_IN_OUT */
  (uint16)( SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(13) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_EMIOS0_E0UC_30_Y_IN_OUT |
PORT17_EMIOS0_E0UC_5_G_IN_OUT |
PORT18_IIC_0_SDA0_IN_OUT |
PORT19_IIC_0_SCL0_IN_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3)
          ),
/* Pads  32 ...  47 : PORT38_EMIOS1_E1UC_28_Y_IN_OUT |
PORT40_EMIOS0_E0UC_3_G_IN_OUT |
PORT43_EMIOS0_E0UC_1_G_IN_OUT |
PORT46_DSPI_2_dSCLK_IN_OUT */
  (uint16)( SHL_PAD_U16(6) |
SHL_PAD_U16(8) |
SHL_PAD_U16(11) |
SHL_PAD_U16(14)
          ),
/* Pads  48 ...  63 : PORT60_EMIOS0_E0UC_24_X_IN_OUT |
PORT61_EMIOS0_E0UC_25_Y_IN_OUT |
PORT62_EMIOS0_E0UC_26_Y_IN_OUT |
PORT63_EMIOS0_E0UC_27_Y_IN_OUT */
  (uint16)( SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  64 ...  79 : PORT64_IIC_1_SCL1_IN_OUT |
PORT68_DSPI_1_dSCLK_IN_OUT |
PORT72_EMIOS0_E0UC_22_X_IN_OUT |
PORT73_IIC_2_SCL2_IN_OUT |
PORT77_EMIOS1_E1UC_20_Y_IN_OUT |
PORT78_EMIOS1_E1UC_21_Y_IN_OUT |
PORT79_EMIOS1_E1UC_22_X_IN_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(4) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT91_EMIOS1_E1UC_3_H_IN_OUT |
PORT93_EMIOS0_E0UC_22_X_IN_OUT |
PORT94_EMIOS1_E1UC_27_Y_IN_OUT */
  (uint16)( SHL_PAD_U16(11) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14)
          ),
/* Pads  96 ... 111 : PORT96_EMIOS1_E1UC_23_X_IN_OUT |
PORT97_ENET0_MII_RMII_0_TX_CLK_IN_OUT |
PORT100_DSPI_3_dSCLK_IN_OUT |
PORT101_EMIOS0_E0UC_2_G_IN_OUT |
PORT103_EMIOS1_E1UC_30_Y_IN_OUT |
PORT105_DSPI_2_dSCLK_IN_OUT |
PORT106_EMIOS1_E1UC_31_Y_IN_OUT |
PORT109_SPI_0_SCLK_0_IN_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(7) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(13)
          ),
/* Pads 112 ... 127 : PORT114_DSPI_1_dSCLK_IN_OUT |
PORT117_IIC_3_SDA3_IN_OUT |
PORT118_SPI_3_SCLK_3_IN_OUT */
  (uint16)( SHL_PAD_U16(2) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6)
          ),
/* Pads 128 ... 143 : PORT129_IIC_1_SCL1_IN_OUT |
PORT131_IIC_2_SCL2_IN_OUT |
PORT133_SPI_0_SCLK_0_IN_OUT |
PORT139_ENET0_ENET0_TMR1_IN_OUT */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(3) |
SHL_PAD_U16(5) |
SHL_PAD_U16(11)
          ),
/* Pads 144 ... 159 : PORT145_SAI2_SAI2_BCLK_IN_OUT |
PORT148_EMIOS1_E1UC_18_Y_IN_OUT */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(4)
          )
}
,
/*  Mode PORT_INOUT3_MODE: */
{
/* Pads   0 ...  15 : PORT0_EMIOS0_E0UC_13_H_IN_OUT |
PORT4_EMIOS0_E0UC_24_X_IN_OUT |
PORT12_EMIOS0_E0UC_26_Y_IN_OUT |
PORT13_EMIOS0_E0UC_25_Y_IN_OUT |
PORT14_EMIOS0_E0UC_0_X_IN_OUT |
PORT15_EMIOS0_E0UC_1_G_IN_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(4) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT18_EMIOS0_E0UC_30_Y_IN_OUT |
PORT19_EMIOS0_E0UC_8_X_IN_OUT */
  (uint16)( SHL_PAD_U16(2) |
SHL_PAD_U16(3)
          ),
/* Pads  32 ...  47 : PORT38_EMIOS0_E0UC_17_Y_IN_OUT |
PORT39_EMIOS0_E0UC_18_Y_IN_OUT */
  (uint16)( SHL_PAD_U16(6) |
SHL_PAD_U16(7)
          ),
/* Pads  48 ...  63 : PORT61_ENET0_ENET0_TMR0_IN_OUT */
  (uint16)( SHL_PAD_U16(13)
          ),
/* Pads  64 ...  79 : PORT65_IIC_1_SDA1_IN_OUT |
PORT74_EMIOS1_E1UC_30_Y_IN_OUT |
PORT79_SPI_2_SCLK_2_IN_OUT */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(10) |
SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT89_EMIOS0_E0UC_14_H_IN_OUT |
PORT90_EMIOS1_E1UC_2_H_IN_OUT |
PORT91_EMIOS0_E0UC_20_Y_IN_OUT |
PORT92_EMIOS0_E0UC_16_X_IN_OUT */
  (uint16)( SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12)
          ),
/* Pads  96 ... 111 : PORT105_EMIOS0_E0UC_0_X_IN_OUT */
  (uint16)( SHL_PAD_U16(9)
          ),
/* Pads 112 ... 127 : PORT116_IIC_3_SCL3_IN_OUT |
PORT123_EMIOS1_E1UC_5_H_IN_OUT |
PORT124_EMIOS1_E1UC_25_Y_IN_OUT |
PORT125_EMIOS1_E1UC_26_Y_IN_OUT |
PORT126_EMIOS1_E1UC_27_Y_IN_OUT |
PORT127_EMIOS1_E1UC_17_Y_IN_OUT */
  (uint16)( SHL_PAD_U16(4) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 128 ... 143 : PORT128_IIC_1_SDA1_IN_OUT |
PORT130_IIC_2_SDA2_IN_OUT |
PORT143_SAI2_SAI2_MCLK_IN_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(2) |
SHL_PAD_U16(15)
          ),
/* Pads 144 ... 159 : PORT144_SAI2_SAI2_SYNC_IN_OUT |
PORT157_EMIOS1_E1UC_15_H_IN_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(13)
          )
}
,
/*  Mode PORT_INOUT4_MODE: */
{
/* Pads   0 ...  15 : PORT14_EMIOS0_E0UC_23_X_IN_OUT |
PORT15_EMIOS0_E0UC_21_Y_IN_OUT */
  (uint16)( SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_EMIOS0_E0UC_4_G_IN_OUT |
PORT26_SAI0_SAI0_SYNC_IN_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(10)
          ),
/* Pads 32 ... 47 */
  (uint16)0x0000,
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads  64 ...  79 : PORT72_IIC_2_SDA2_IN_OUT |
PORT74_IIC_3_SDA3_IN_OUT |
PORT75_IIC_3_SCL3_IN_OUT */
  (uint16)( SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11)
          ),
/* Pads  80 ...  95 : PORT81_SAI0_SAI0_BCLK_IN_OUT |
PORT82_SAI0_SAI0_D3_IN_OUT |
PORT83_SAI0_SAI0_D2_IN_OUT |
PORT84_SAI0_SAI0_D1_IN_OUT |
PORT85_SAI0_SAI0_D0_IN_OUT |
PORT86_SAI1_SAI1_SYNC_IN_OUT |
PORT88_EMIOS0_E0UC_15_H_IN_OUT |
PORT90_EMIOS0_E0UC_19_Y_IN_OUT |
PORT92_FCCU_EOUT1_IN_OUT |
PORT94_ENET0_MII_RMII_0_MDIO_IN_OUT */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14)
          ),
/* Pads  96 ... 111 : PORT102_EMIOS0_E0UC_3_G_IN_OUT */
  (uint16)( SHL_PAD_U16(6)
          ),
/* Pads 112 ... 127 : PORT125_FCCU_EOUT1_IN_OUT |
PORT127_FCCU_EOUT0_IN_OUT */
  (uint16)( SHL_PAD_U16(13) |
SHL_PAD_U16(15)
          ),
/* Pads 128 ... 143 */
  (uint16)0x0000,
/* Pads 144 ... 159 : PORT146_SAI1_SAI1_D0_IN_OUT |
PORT147_SAI1_SAI1_BCLK_IN_OUT */
  (uint16)( SHL_PAD_U16(2) |
SHL_PAD_U16(3)
          )
}
,
/*  Mode PORT_INOUT5_MODE: */
{
/* Pads 0 ... 15 */
  (uint16)0x0000,
/* Pads  16 ...  31 : PORT26_EMIOS0_E0UC_29_Y_IN_OUT */
  (uint16)( SHL_PAD_U16(10)
          ),
/* Pads 32 ... 47 */
  (uint16)0x0000,
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads 64 ... 79 */
  (uint16)0x0000,
/* Pads  80 ...  95 : PORT86_EMIOS0_E0UC_30_Y_IN_OUT |
PORT90_FCCU_EOUT0_IN_OUT */
  (uint16)( SHL_PAD_U16(6) |
SHL_PAD_U16(10)
          ),
/* Pads 96 ... 111 */
  (uint16)0x0000,
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 */
  (uint16)0x0000,
/* Pads 144 ... 159 */
  (uint16)0x0000
}
,
/*  Mode PORT_INOUT6_MODE: */
{
/* Pads 0 ... 15 */
  (uint16)0x0000,
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads 32 ... 47 */
  (uint16)0x0000,
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads 64 ... 79 */
  (uint16)0x0000,
/* Pads  80 ...  95 : PORT87_SAI1_SAI1_MCLK_IN_OUT */
  (uint16)( SHL_PAD_U16(7)
          ),
/* Pads 96 ... 111 */
  (uint16)0x0000,
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 */
  (uint16)0x0000,
/* Pads 144 ... 159 : PORT158_EMIOS1_E1UC_14_H_IN_OUT */
  (uint16)( SHL_PAD_U16(14)
          )
}
,
/*  Mode PORT_INOUT7_MODE: */
{
/* Pads 0 ... 15 */
  (uint16)0x0000,
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads 32 ... 47 */
  (uint16)0x0000,
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads 64 ... 79 */
  (uint16)0x0000,
/* Pads  80 ...  95 : PORT80_SAI0_SAI0_MCLK_IN_OUT */
  (uint16)( SHL_PAD_U16(0)
          ),
/* Pads 96 ... 111 */
  (uint16)0x0000,
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 */
  (uint16)0x0000,
/* Pads 144 ... 159 */
  (uint16)0x0000
}

[!ENDVAR!]




[!VAR "CHECK_3"!]

/*  Mode PORT_GPIO_MODE: */
{
/* Pads   0 ...  15 : PORT0_GPIO |
PORT1_GPIO |
PORT2_GPIO |
PORT3_GPIO |
PORT4_GPIO |
PORT5_GPIO |
PORT6_GPIO |
PORT7_GPIO |
PORT8_GPIO |
PORT9_GPIO |
PORT10_GPIO |
PORT11_GPIO |
PORT12_GPIO |
PORT13_GPIO |
PORT14_GPIO |
PORT15_GPIO */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_GPIO |
PORT17_GPIO |
PORT18_GPIO |
PORT19_GPIO |
PORT26_GPIO |
PORT27_GPIO |
PORT28_GPIO |
PORT29_GPIO |
PORT30_GPIO |
PORT31_GPIO */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  32 ...  47 : PORT32_GPIO |
PORT33_GPIO |
PORT34_GPIO |
PORT35_GPIO |
PORT36_GPIO |
PORT37_GPIO |
PORT38_GPIO |
PORT39_GPIO |
PORT40_GPIO |
PORT41_GPIO |
PORT42_GPIO |
PORT43_GPIO |
PORT44_GPIO |
PORT45_GPIO |
PORT46_GPIO |
PORT47_GPIO */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  48 ...  63 : PORT60_GPIO |
PORT61_GPIO |
PORT62_GPIO |
PORT63_GPIO */
  (uint16)( SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  64 ...  79 : PORT64_GPIO |
PORT65_GPIO |
PORT66_GPIO |
PORT67_GPIO |
PORT68_GPIO |
PORT69_GPIO |
PORT70_GPIO |
PORT71_GPIO |
PORT72_GPIO |
PORT73_GPIO |
PORT74_GPIO |
PORT75_GPIO |
PORT76_GPIO |
PORT77_GPIO |
PORT78_GPIO |
PORT79_GPIO */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT80_GPIO |
PORT81_GPIO |
PORT82_GPIO |
PORT83_GPIO |
PORT84_GPIO |
PORT85_GPIO |
PORT86_GPIO |
PORT87_GPIO |
PORT88_GPIO |
PORT89_GPIO |
PORT90_GPIO |
PORT91_GPIO |
PORT92_GPIO |
PORT93_GPIO |
PORT94_GPIO |
PORT95_GPIO */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT96_GPIO |
PORT97_GPIO |
PORT98_GPIO |
PORT99_GPIO |
PORT100_GPIO |
PORT101_GPIO |
PORT102_GPIO |
PORT103_GPIO |
PORT104_GPIO |
PORT105_GPIO |
PORT106_GPIO |
PORT107_GPIO |
PORT108_GPIO |
PORT109_GPIO |
PORT110_GPIO |
PORT111_GPIO */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 112 ... 127 : PORT112_GPIO |
PORT113_GPIO |
PORT114_GPIO |
PORT115_GPIO |
PORT116_GPIO |
PORT117_GPIO |
PORT118_GPIO |
PORT119_GPIO |
PORT120_GPIO |
PORT121_GPIO |
PORT122_GPIO |
PORT123_GPIO |
PORT124_GPIO |
PORT125_GPIO |
PORT126_GPIO |
PORT127_GPIO */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 128 ... 143 : PORT128_GPIO |
PORT129_GPIO |
PORT130_GPIO |
PORT131_GPIO |
PORT132_GPIO |
PORT133_GPIO |
PORT134_GPIO |
PORT135_GPIO |
PORT136_GPIO |
PORT137_GPIO |
PORT138_GPIO |
PORT139_GPIO |
PORT140_GPIO |
PORT141_GPIO |
PORT142_GPIO |
PORT143_GPIO */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 144 ... 159 : PORT144_GPIO |
PORT145_GPIO |
PORT146_GPIO |
PORT147_GPIO |
PORT148_GPIO |
PORT149_GPIO |
PORT150_GPIO |
PORT151_GPIO |
PORT152_GPIO |
PORT153_GPIO |
PORT154_GPIO |
PORT155_GPIO |
PORT156_GPIO |
PORT157_GPIO |
PORT158_GPIO |
PORT159_GPIO */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 160 ... 175 : PORT160_GPIO |
PORT161_GPIO |
PORT162_GPIO |
PORT163_GPIO |
PORT164_GPIO |
PORT165_GPIO |
PORT166_GPIO |
PORT167_GPIO |
PORT168_GPIO |
PORT169_GPIO |
PORT170_GPIO |
PORT171_GPIO |
PORT172_GPIO |
PORT173_GPIO |
PORT174_GPIO |
PORT175_GPIO */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 176 ... 191 : PORT176_GPIO |
PORT177_GPIO */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1)
          ),
/* Pads 192 ... 207 : PORT195_GPIO |
PORT196_GPIO |
PORT197_GPIO |
PORT206_GPIO */
  (uint16)( SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(14)
          ),
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 : PORT224_GPIO |
PORT225_GPIO */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1)
          ),
/* Pads 240 ... 255 : PORT252_GPIO |
PORT253_GPIO |
PORT254_GPIO |
PORT255_GPIO */
  (uint16)( SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 256 ... 271 : PORT256_GPIO |
PORT257_GPIO |
PORT258_GPIO |
PORT259_GPIO |
PORT260_GPIO |
PORT261_GPIO |
PORT262_GPIO |
PORT263_GPIO */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7)
          )
}
,
/*  Mode PORT_ALT1_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_EMIOS0_E0UC_0_X_OUT |
PORT1_EMIOS0_E0UC_1_G_OUT |
PORT2_EMIOS0_E0UC_2_G_OUT |
PORT3_EMIOS0_E0UC_3_G_OUT |
PORT4_EMIOS0_E0UC_4_G_OUT |
PORT5_EMIOS0_E0UC_5_G_OUT |
PORT6_EMIOS0_E0UC_6_G_OUT |
PORT7_EMIOS0_E0UC_7_G_OUT |
PORT8_EMIOS0_E0UC_8_X_OUT |
PORT9_EMIOS0_E0UC_9_H_OUT |
PORT10_EMIOS0_E0UC_10_H_OUT |
PORT11_EMIOS0_E0UC_11_H_OUT |
PORT12_EMIOS0_E0UC_28_Y_OUT |
PORT13_DSPI_0_dSOUT |
PORT14_DSPI_0_dSCLK_OUT |
PORT15_DSPI_0_dCS0 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_FlexCAN_0_TX |
PORT17_EMIOS0_E0UC_31_Y_OUT |
PORT18_LIN_0_LIN0TX |
PORT19_EMIOS0_E0UC_31_Y_OUT |
PORT26_DSPI_1_dSOUT |
PORT27_EMIOS0_E0UC_3_G_OUT |
PORT28_EMIOS0_E0UC_4_G_OUT |
PORT29_EMIOS0_E0UC_5_G_OUT |
PORT30_EMIOS0_E0UC_6_G_OUT |
PORT31_EMIOS0_E0UC_7_G_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  32 ...  47 : PORT32_DCI_TDI |
PORT33_DCI_TDO |
PORT34_DSPI_1_dSCLK_OUT |
PORT35_DSPI_1_dCS0 |
PORT36_EMIOS1_E1UC_31_Y_OUT |
PORT37_DSPI_1_dSOUT |
PORT38_LIN_1_LIN1TX |
PORT39_EMIOS1_E1UC_29_Y_OUT |
PORT40_LIN_2_LIN2TX |
PORT41_EMIOS0_E0UC_7_G_OUT |
PORT42_FlexCAN_1_TX |
PORT43_ADC_0_ADC0_MA_2 |
PORT44_EMIOS0_E0UC_12_H_OUT |
PORT45_EMIOS0_E0UC_13_H_OUT |
PORT46_EMIOS0_E0UC_14_H_OUT |
PORT47_EMIOS0_E0UC_15_H_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  48 ...  63 : PORT60_DSPI_0_dCS5 |
PORT61_DSPI_1_dCS0 |
PORT62_DSPI_1_dCS1 |
PORT63_DSPI_1_dCS2 */
  (uint16)( SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  64 ...  79 : PORT64_EMIOS0_E0UC_16_X_OUT |
PORT65_EMIOS0_E0UC_17_Y_OUT |
PORT66_EMIOS0_E0UC_18_Y_OUT |
PORT67_EMIOS0_E0UC_19_Y_OUT |
PORT68_EMIOS0_E0UC_20_Y_OUT |
PORT69_EMIOS0_E0UC_21_Y_OUT |
PORT70_EMIOS0_E0UC_22_X_OUT |
PORT71_EMIOS0_E0UC_23_X_OUT |
PORT72_FlexCAN_2_TX |
PORT73_EMIOS0_E0UC_23_X_OUT |
PORT74_LIN_3_LIN3TX |
PORT75_EMIOS0_E0UC_24_X_OUT |
PORT76_EMIOS1_E1UC_19_Y_OUT |
PORT77_DSPI_2_dSOUT |
PORT78_DSPI_2_dSCLK_OUT |
PORT79_DSPI_2_dCS0 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT80_EMIOS0_E0UC_10_H_OUT |
PORT81_EMIOS0_E0UC_11_H_OUT |
PORT82_EMIOS0_E0UC_12_H_OUT |
PORT83_EMIOS0_E0UC_13_H_OUT |
PORT84_EMIOS0_E0UC_14_H_OUT |
PORT85_EMIOS0_E0UC_22_X_OUT |
PORT86_EMIOS0_E0UC_23_X_OUT |
PORT87_SPI_0_SCLK_0_OUT |
PORT88_FlexCAN_3_TX |
PORT89_EMIOS1_E1UC_1_H_OUT |
PORT90_DSPI_0_dCS1 |
PORT91_DSPI_0_dCS2 |
PORT92_EMIOS1_E1UC_25_Y_OUT |
PORT93_EMIOS1_E1UC_26_Y_OUT |
PORT94_FlexCAN_4_TX |
PORT95_EMIOS1_E1UC_4_H_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT96_FlexCAN_5_TX |
PORT97_EMIOS1_E1UC_24_X_OUT |
PORT98_EMIOS1_E1UC_11_H_OUT |
PORT99_EMIOS1_E1UC_12_H_OUT |
PORT100_EMIOS1_E1UC_13_H_OUT |
PORT101_EMIOS1_E1UC_14_H_OUT |
PORT102_EMIOS1_E1UC_15_H_OUT |
PORT103_EMIOS1_E1UC_16_X_OUT |
PORT104_EMIOS1_E1UC_17_Y_OUT |
PORT105_EMIOS1_E1UC_18_Y_OUT |
PORT106_EMIOS0_E0UC_24_X_OUT |
PORT107_EMIOS0_E0UC_25_Y_OUT |
PORT108_EMIOS0_E0UC_26_Y_OUT |
PORT109_EMIOS0_E0UC_27_Y_OUT |
PORT110_EMIOS1_E1UC_0_X_OUT |
PORT111_EMIOS1_E1UC_1_H_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 112 ... 127 : PORT112_EMIOS1_E1UC_2_H_OUT |
PORT113_EMIOS1_E1UC_3_H_OUT |
PORT114_EMIOS1_E1UC_4_H_OUT |
PORT115_EMIOS1_E1UC_5_H_OUT |
PORT116_EMIOS1_E1UC_6_H_OUT |
PORT117_EMIOS1_E1UC_7_H_OUT |
PORT118_EMIOS1_E1UC_8_X_OUT |
PORT119_EMIOS1_E1UC_9_H_OUT |
PORT120_EMIOS1_E1UC_10_H_OUT |
PORT121_DCI_TCK |
PORT122_DCI_TMS_OUT |
PORT123_DSPI_3_dSOUT |
PORT124_DSPI_3_dSCLK_OUT |
PORT125_SPI_0_SOUT_0 |
PORT126_SPI_0_SCLK_0_OUT |
PORT127_SPI_1_SOUT_1 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 128 ... 143 : PORT128_EMIOS0_E0UC_28_Y_OUT |
PORT129_EMIOS0_E0UC_29_Y_OUT |
PORT130_EMIOS0_E0UC_30_Y_OUT |
PORT131_EMIOS0_E0UC_31_Y_OUT |
PORT132_EMIOS1_E1UC_28_Y_OUT |
PORT133_EMIOS1_E1UC_29_Y_OUT |
PORT134_EMIOS1_E1UC_30_Y_OUT |
PORT135_EMIOS1_E1UC_31_Y_OUT |
PORT140_DSPI_3_dCS0 |
PORT141_DSPI_3_dCS1 |
PORT142_SAI2_SAI2_D0_OUT |
PORT143_SPI_0_CS0_0 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 144 ... 159 : PORT144_SPI_0_CS1_0 |
PORT145_SPI_0_SOUT_0 |
PORT146_SPI_1_CS0_1 |
PORT147_SPI_1_CS1_1 |
PORT148_SPI_1_SCLK_1_OUT |
PORT155_FlexCAN_2_TX |
PORT156_EMIOS1_E1UC_10_H_OUT |
PORT157_SPI_3_CS1_3 |
PORT158_FlexCAN_1_TX |
PORT159_SPI_2_CS1_2 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 160 ... 175 : PORT160_FlexCAN_1_TX |
PORT161_SPI_2_CS3_2 |
PORT162_FlexCAN_4_TX |
PORT163_EMIOS1_E1UC_0_X_OUT |
PORT164_FlexCAN_5_TX |
PORT165_EMIOS0_E0UC_10_H_OUT |
PORT166_FlexCAN_2_TX |
PORT167_EMIOS0_E0UC_12_H_OUT |
PORT168_FlexCAN_3_TX |
PORT169_EMIOS1_E1UC_29_Y_OUT |
PORT170_SPI_0_SOUT_0 |
PORT171_SPI_0_SCLK_0_OUT |
PORT172_SPI_0_CS0_0 |
PORT173_SPI_2_CS3_2 |
PORT174_FlexCAN_3_TX |
PORT175_SPI_0_CS2_0 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 176 ... 191 : PORT176_SPI_1_SOUT_1 |
PORT177_SAI0_SAI0_D0_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1)
          ),
/* Pads 192 ... 207 : PORT195_SAI0_SAI0_D1_OUT |
PORT196_SAI0_SAI0_D2_OUT |
PORT197_SAI0_SAI0_D3_OUT |
PORT206_SAI0_SAI0_MCLK_OUT */
  (uint16)( SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(14)
          ),
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 */
  (uint16)0x0000,
/* Pads 240 ... 255 : PORT252_SPI_2_CS0_2 |
PORT253_SPI_2_SOUT_2 |
PORT254_SPI_2_SCLK_2_OUT |
PORT255_EMIOS1_E1UC_21_Y_OUT */
  (uint16)( SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 256 ... 271 : PORT256_DSPI_0_dCS1 |
PORT257_DSPI_0_dCS0 |
PORT258_DSPI_0_dSCLK_OUT |
PORT260_DSPI_0_dSOUT |
PORT261_SPI_2_CS3_2 |
PORT262_SPI_2_CS2_2 |
PORT263_SPI_2_CS1_2 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7)
          )
}
,
/*  Mode PORT_ALT2_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_CGM_CLKOUT0 |
PORT3_LIN_5_LIN5TX |
PORT4_DSPI_1_dCS0 |
PORT5_LIN_4_LIN4TX |
PORT6_DSPI_1_dCS1 |
PORT7_LIN_3_LIN3TX |
PORT8_EMIOS0_E0UC_14_H_OUT |
PORT9_DSPI_1_dCS2 |
PORT10_IIC_0_SDA0_OUT |
PORT11_IIC_0_SCL0_OUT |
PORT12_DSPI_1_dCS3 |
PORT13_EMIOS0_E0UC_29_Y_OUT |
PORT14_DSPI_0_dCS0 |
PORT15_DSPI_0_dSCLK_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_EMIOS0_E0UC_30_Y_OUT |
PORT17_EMIOS0_E0UC_5_G_OUT |
PORT18_IIC_0_SDA0_OUT |
PORT19_IIC_0_SCL0_OUT |
PORT26_FlexCAN_3_TX |
PORT27_DSPI_0_dCS0 |
PORT28_DSPI_0_dCS1 |
PORT29_DSPI_0_dCS2 |
PORT30_DSPI_0_dCS3 |
PORT31_DSPI_0_dCS4 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  32 ...  47 : PORT34_FlexCAN_4_TX |
PORT35_ADC_0_ADC0_MA_0 |
PORT36_FlexRay_FR_B_TX_EN |
PORT37_FlexCAN_3_TX |
PORT38_EMIOS1_E1UC_28_Y_OUT |
PORT39_CMP1_CMP1_O |
PORT40_EMIOS0_E0UC_3_G_OUT |
PORT42_FlexCAN_4_TX |
PORT43_EMIOS0_E0UC_1_G_OUT |
PORT44_FlexRay_FR_DBG_0 |
PORT45_DSPI_2_dSOUT |
PORT46_DSPI_2_dSCLK_OUT |
PORT47_DSPI_2_dCS0 */
  (uint16)( SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  48 ...  63 : PORT60_EMIOS0_E0UC_24_X_OUT |
PORT61_EMIOS0_E0UC_25_Y_OUT |
PORT62_EMIOS0_E0UC_26_Y_OUT |
PORT63_EMIOS0_E0UC_27_Y_OUT */
  (uint16)( SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  64 ...  79 : PORT64_IIC_1_SCL1_OUT |
PORT65_FlexCAN_5_TX |
PORT66_FlexRay_FR_A_TX_EN |
PORT67_DSPI_1_dSOUT |
PORT68_DSPI_1_dSCLK_OUT |
PORT69_DSPI_1_dCS0 |
PORT70_DSPI_0_dCS3 |
PORT71_DSPI_0_dCS2 |
PORT72_EMIOS0_E0UC_22_X_OUT |
PORT73_IIC_2_SCL2_OUT |
PORT74_DSPI_1_dCS3 |
PORT75_DSPI_1_dCS4 |
PORT77_EMIOS1_E1UC_20_Y_OUT |
PORT78_EMIOS1_E1UC_21_Y_OUT |
PORT79_EMIOS1_E1UC_22_X_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT80_DSPI_1_dCS3 |
PORT81_DSPI_1_dCS4 |
PORT82_DSPI_2_dCS0 |
PORT83_DSPI_2_dCS1 |
PORT84_DSPI_2_dCS2 |
PORT85_DSPI_2_dCS3 |
PORT86_DSPI_1_dCS1 |
PORT87_DSPI_1_dCS2 |
PORT88_DSPI_0_dCS4 |
PORT89_DSPI_0_dCS5 |
PORT90_LIN_4_LIN4TX |
PORT91_EMIOS1_E1UC_3_H_OUT |
PORT92_LIN_5_LIN5TX |
PORT93_EMIOS0_E0UC_22_X_OUT |
PORT94_EMIOS1_E1UC_27_Y_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14)
          ),
/* Pads  96 ... 111 : PORT96_EMIOS1_E1UC_23_X_OUT |
PORT97_ENET0_MII_RMII_0_TX_CLK_OUT |
PORT98_DSPI_3_dSOUT |
PORT99_DSPI_3_dCS0 |
PORT100_DSPI_3_dSCLK_OUT |
PORT101_EMIOS0_E0UC_2_G_OUT |
PORT102_LIN_6_LIN6TX |
PORT103_EMIOS1_E1UC_30_Y_OUT |
PORT104_LIN_7_LIN7TX |
PORT105_DSPI_2_dSCLK_OUT |
PORT106_EMIOS1_E1UC_31_Y_OUT |
PORT107_SPI_0_CS0_0 |
PORT108_SPI_0_SOUT_0 |
PORT109_SPI_0_SCLK_0_OUT |
PORT110_LIN_8_LIN8TX |
PORT111_SPI_2_SOUT_2 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 112 ... 127 : PORT113_DSPI_1_dSOUT |
PORT114_DSPI_1_dSCLK_OUT |
PORT115_DSPI_1_dCS0 |
PORT116_SPI_3_SOUT_3 |
PORT117_IIC_3_SDA3_OUT |
PORT118_SPI_3_SCLK_3_OUT |
PORT119_DSPI_2_dCS3 |
PORT120_DSPI_2_dCS2 |
PORT123_SPI_0_CS0_0 |
PORT124_SPI_0_CS1_0 |
PORT125_DSPI_3_dCS0 |
PORT126_DSPI_3_dCS1 */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14)
          ),
/* Pads 128 ... 143 : PORT128_LIN_8_LIN8TX |
PORT129_IIC_1_SCL1_OUT |
PORT130_LIN_9_LIN9TX |
PORT131_IIC_2_SCL2_OUT |
PORT132_SPI_0_SOUT_0 |
PORT133_SPI_0_SCLK_0_OUT |
PORT134_SPI_0_CS0_0 |
PORT135_SPI_0_CS1_0 |
PORT139_ENET0_ENET0_TMR1_OUT |
PORT140_DSPI_2_dCS0 |
PORT141_DSPI_2_dCS1 |
PORT143_DSPI_2_dCS2 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(15)
          ),
/* Pads 144 ... 159 : PORT144_DSPI_2_dCS3 |
PORT145_SAI2_SAI2_BCLK_OUT |
PORT146_SPI_2_CS0_2 |
PORT147_SPI_2_CS1_2 |
PORT148_EMIOS1_E1UC_18_Y_OUT |
PORT149_SAI2_SAI2_D0_OUT |
PORT150_SAI2_SAI2_BCLK_OUT |
PORT152_SAI2_SAI2_SYNC_OUT |
PORT153_FlexCAN_4_TX |
PORT154_EMIOS1_E1UC_16_X_OUT |
PORT155_EMIOS1_E1UC_11_H_OUT |
PORT158_FlexCAN_4_TX |
PORT159_EMIOS1_E1UC_13_H_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 160 ... 175 : PORT160_SPI_2_CS2_2 |
PORT161_EMIOS0_E0UC_6_G_OUT |
PORT164_LIN_8_LIN8TX |
PORT165_EMIOS1_E1UC_4_H_OUT |
PORT166_LIN_2_LIN2TX |
PORT167_EMIOS1_E1UC_6_H_OUT |
PORT168_LIN_3_LIN3TX |
PORT170_EMIOS1_E1UC_30_Y_OUT |
PORT171_EMIOS1_E1UC_31_Y_OUT |
PORT172_EMIOS0_E0UC_0_X_OUT |
PORT173_SPI_3_CS2_3 |
PORT174_SPI_3_CS3_3 |
PORT175_EMIOS0_E0UC_3_G_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 176 ... 191 : PORT176_SPI_3_SOUT_3 */
  (uint16)( SHL_PAD_U16(0)
          ),
/* Pads 192 ... 207 : PORT195_ENET0_ENET0_TMR2_OUT |
PORT197_DCI_TCK_ALT |
PORT206_DCI_TMS_ALT_OUT */
  (uint16)( SHL_PAD_U16(3) |
SHL_PAD_U16(5) |
SHL_PAD_U16(14)
          ),
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 : PORT224_IIC_0_SDA0_OUT |
PORT225_IIC_0_SCL0_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1)
          ),
/* Pads 240 ... 255 : PORT252_DSPI_0_dCS4 |
PORT253_EMIOS1_E1UC_23_X_OUT |
PORT254_EMIOS1_E1UC_22_X_OUT */
  (uint16)( SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14)
          ),
/* Pads 256 ... 271 : PORT260_EMIOS1_E1UC_28_Y_OUT |
PORT261_DSPI_0_dCS3 |
PORT262_DSPI_0_dCS2 |
PORT263_DSPI_0_dCS5 */
  (uint16)( SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7)
          )
}
,
/*  Mode PORT_ALT3_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_EMIOS0_E0UC_13_H_OUT |
PORT2_ADC_0_ADC0_MA_2 |
PORT3_DSPI_1_dCS4 |
PORT4_EMIOS0_E0UC_24_X_OUT |
PORT10_LIN_2_LIN2TX |
PORT12_EMIOS0_E0UC_26_Y_OUT |
PORT13_EMIOS0_E0UC_25_Y_OUT |
PORT14_EMIOS0_E0UC_0_X_OUT |
PORT15_EMIOS0_E0UC_1_G_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(10) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_LIN_0_LIN0TX |
PORT18_EMIOS0_E0UC_30_Y_OUT |
PORT19_EMIOS0_E0UC_8_X_OUT |
PORT26_CMP2_CMP2_O |
PORT28_HSM_DO1 |
PORT30_FlexRay_FR_DBG_1 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(10) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14)
          ),
/* Pads  32 ...  47 : PORT38_EMIOS0_E0UC_17_Y_OUT |
PORT39_EMIOS0_E0UC_18_Y_OUT |
PORT41_SSCM_SSCM_DBG_7 |
PORT42_ADC_0_ADC0_MA_1 |
PORT45_FlexRay_FR_DBG_1 */
  (uint16)( SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(13)
          ),
/* Pads  48 ...  63 : PORT60_HSM_DO0 |
PORT61_ENET0_ENET0_TMR0_OUT |
PORT62_FlexRay_FR_DBG_0 |
PORT63_FlexRay_FR_DBG_1 */
  (uint16)( SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  64 ...  79 : PORT65_IIC_1_SDA1_OUT |
PORT68_FlexRay_FR_B_TX |
PORT69_ADC_0_ADC0_MA_2 |
PORT70_ADC_0_ADC0_MA_1 |
PORT71_ADC_0_ADC0_MA_0 |
PORT72_FlexCAN_3_TX |
PORT74_EMIOS1_E1UC_30_Y_OUT |
PORT75_CGM_CLKOUT1 |
PORT79_SPI_2_SCLK_2_OUT */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT81_SPI_0_CS3_0 |
PORT85_SPI_0_CS2_0 |
PORT88_FlexCAN_2_TX |
PORT89_EMIOS0_E0UC_14_H_OUT |
PORT90_EMIOS1_E1UC_2_H_OUT |
PORT91_EMIOS0_E0UC_20_Y_OUT |
PORT92_EMIOS0_E0UC_16_X_OUT |
PORT94_FlexCAN_1_TX */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(5) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14)
          ),
/* Pads  96 ... 111 : PORT96_ENET0_MII_RMII_0_MDC |
PORT98_FlexCAN_7_TX |
PORT100_LIN_10_LIN10TX |
PORT102_CGM_CLKOUT1 |
PORT103_CGM_CLKOUT0 |
PORT104_DSPI_2_dCS0 |
PORT105_EMIOS0_E0UC_0_X_OUT |
PORT107_SPI_2_CS0_2 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(2) |
SHL_PAD_U16(4) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(11)
          ),
/* Pads 112 ... 127 : PORT112_ENET0_MII_RMII_0_TXD_1 |
PORT115_ENET0_MII_0_TX_ER |
PORT116_IIC_3_SCL3_OUT |
PORT118_ADC_0_ADC0_MA_2 |
PORT119_ADC_0_ADC0_MA_1 |
PORT120_ADC_0_ADC0_MA_0 |
PORT123_EMIOS1_E1UC_5_H_OUT |
PORT124_EMIOS1_E1UC_25_Y_OUT |
PORT125_EMIOS1_E1UC_26_Y_OUT |
PORT126_EMIOS1_E1UC_27_Y_OUT |
PORT127_EMIOS1_E1UC_17_Y_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 128 ... 143 : PORT128_IIC_1_SDA1_OUT |
PORT130_IIC_2_SDA2_OUT |
PORT133_SPI_1_CS2_1 |
PORT134_SPI_1_CS0_1 |
PORT135_SPI_1_CS1_1 |
PORT143_SAI2_SAI2_MCLK_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(2) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(15)
          ),
/* Pads 144 ... 159 : PORT144_SAI2_SAI2_SYNC_OUT |
PORT146_SPI_3_CS0_3 |
PORT147_SPI_3_CS1_3 |
PORT151_SAI2_SAI2_MCLK_OUT |
PORT153_EMIOS1_E1UC_17_Y_OUT |
PORT157_EMIOS1_E1UC_15_H_OUT |
PORT158_SPI_3_CS2_3 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(7) |
SHL_PAD_U16(9) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14)
          ),
/* Pads 160 ... 175 : PORT160_FlexCAN_3_TX |
PORT161_EMIOS1_E1UC_1_H_OUT |
PORT162_EMIOS1_E1UC_2_H_OUT |
PORT163_EMIOS1_E1UC_3_H_OUT |
PORT164_EMIOS1_E1UC_1_H_OUT |
PORT166_EMIOS0_E0UC_11_H_OUT |
PORT168_EMIOS0_E0UC_13_H_OUT |
PORT170_LIN_15_LIN15TX |
PORT171_LIN_14_LIN14TX |
PORT173_SPI_1_SCLK_1_OUT |
PORT174_SPI_1_CS0_1 |
PORT175_LIN_13_LIN13TX */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(6) |
SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 176 ... 191 : PORT176_SPI_0_CS3_0 */
  (uint16)( SHL_PAD_U16(0)
          ),
/* Pads 192 ... 207 */
  (uint16)0x0000,
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 : PORT224_LIN_12_LIN12TX */
  (uint16)( SHL_PAD_U16(0)
          ),
/* Pads 240 ... 255 : PORT252_EMIOS1_E1UC_24_X_OUT */
  (uint16)( SHL_PAD_U16(12)
          ),
/* Pads 256 ... 271 : PORT261_EMIOS1_E1UC_27_Y_OUT |
PORT262_EMIOS1_E1UC_26_Y_OUT |
PORT263_EMIOS1_E1UC_25_Y_OUT */
  (uint16)( SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7)
          )
}
,
/*  Mode PORT_ALT4_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT13_FlexCAN_0_TX |
PORT14_EMIOS0_E0UC_23_X_OUT |
PORT15_EMIOS0_E0UC_21_Y_OUT */
  (uint16)( SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_EMIOS0_E0UC_4_G_OUT |
PORT26_SAI0_SAI0_SYNC_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(10)
          ),
/* Pads  32 ...  47 : PORT34_SSCM_SSCM_DBG_0 |
PORT35_SSCM_SSCM_DBG_1 |
PORT37_FlexRay_FR_A_TX |
PORT38_SSCM_SSCM_DBG_4 |
PORT39_SSCM_SSCM_DBG_5 |
PORT40_SSCM_SSCM_DBG_6 |
PORT42_CMP0_CMP0_O |
PORT46_FlexRay_FR_DBG_2 |
PORT47_FlexRay_FR_DBG_3 */
  (uint16)( SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads  64 ...  79 : PORT70_ADC_1_ADC1_MA_1 |
PORT71_ADC_1_ADC1_MA_0 |
PORT72_IIC_2_SDA2_OUT |
PORT74_IIC_3_SDA3_OUT |
PORT75_IIC_3_SCL3_OUT */
  (uint16)( SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11)
          ),
/* Pads  80 ...  95 : PORT80_FlexCAN_6_TX |
PORT81_SAI0_SAI0_BCLK_OUT |
PORT82_SAI0_SAI0_D3_OUT |
PORT83_SAI0_SAI0_D2_OUT |
PORT84_SAI0_SAI0_D1_OUT |
PORT85_SAI0_SAI0_D0_OUT |
PORT86_SAI1_SAI1_SYNC_OUT |
PORT88_EMIOS0_E0UC_15_H_OUT |
PORT90_EMIOS0_E0UC_19_Y_OUT |
PORT92_FCCU_EOUT1_OUT |
PORT94_ENET0_MII_RMII_0_MDIO_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14)
          ),
/* Pads  96 ... 111 : PORT98_LIN_11_LIN11TX |
PORT102_EMIOS0_E0UC_3_G_OUT |
PORT104_FlexCAN_7_TX |
PORT108_ENET0_MII_0_TXD_2 |
PORT109_ENET0_MII_0_TXD_3 */
  (uint16)( SHL_PAD_U16(2) |
SHL_PAD_U16(6) |
SHL_PAD_U16(8) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13)
          ),
/* Pads 112 ... 127 : PORT113_ENET0_MII_RMII_0_TXD_0 |
PORT114_ENET0_MII_RMII_0_TX_EN |
PORT118_ADC_1_ADC1_MA_2 |
PORT119_SPI_3_CS0_3 |
PORT120_ADC_1_ADC1_MA_0 |
PORT125_FCCU_EOUT1_OUT |
PORT127_FCCU_EOUT0_OUT */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(13) |
SHL_PAD_U16(15)
          ),
/* Pads 128 ... 143 : PORT133_SPI_2_CS2_2 |
PORT134_SPI_2_CS0_2 |
PORT135_SPI_2_CS1_2 */
  (uint16)( SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7)
          ),
/* Pads 144 ... 159 : PORT146_SAI1_SAI1_D0_OUT |
PORT147_SAI1_SAI1_BCLK_OUT |
PORT158_FlexCAN_6_TX */
  (uint16)( SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(14)
          ),
/* Pads 160 ... 175 : PORT160_EMIOS1_E1UC_12_H_OUT |
PORT164_EMIOS0_E0UC_9_H_OUT |
PORT166_EMIOS1_E1UC_5_H_OUT |
PORT168_EMIOS1_E1UC_7_H_OUT |
PORT173_EMIOS0_E0UC_1_G_OUT |
PORT174_EMIOS0_E0UC_2_G_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(4) |
SHL_PAD_U16(6) |
SHL_PAD_U16(8) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14)
          ),
/* Pads 176 ... 191 : PORT176_EMIOS0_E0UC_4_G_OUT */
  (uint16)( SHL_PAD_U16(0)
          ),
/* Pads 192 ... 207 */
  (uint16)0x0000,
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 */
  (uint16)0x0000,
/* Pads 240 ... 255 */
  (uint16)0x0000,
/* Pads 256 ... 271 */
  (uint16)0x0000
}
,
/*  Mode PORT_ALT5_FUNC_MODE: */
{
/* Pads 0 ... 15 */
  (uint16)0x0000,
/* Pads  16 ...  31 : PORT26_EMIOS0_E0UC_29_Y_OUT */
  (uint16)( SHL_PAD_U16(10)
          ),
/* Pads  32 ...  47 : PORT36_SSCM_SSCM_DBG_2 |
PORT46_FlexCAN_4_TX */
  (uint16)( SHL_PAD_U16(4) |
SHL_PAD_U16(14)
          ),
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads  64 ...  79 : PORT72_LIN_6_LIN6TX */
  (uint16)( SHL_PAD_U16(8)
          ),
/* Pads  80 ...  95 : PORT86_EMIOS0_E0UC_30_Y_OUT |
PORT90_FCCU_EOUT0_OUT */
  (uint16)( SHL_PAD_U16(6) |
SHL_PAD_U16(10)
          ),
/* Pads 96 ... 111 */
  (uint16)0x0000,
/* Pads 112 ... 127 : PORT119_ADC_1_ADC1_MA_1 */
  (uint16)( SHL_PAD_U16(7)
          ),
/* Pads 128 ... 143 : PORT134_HSM_DO0 |
PORT135_HSM_DO1 */
  (uint16)( SHL_PAD_U16(6) |
SHL_PAD_U16(7)
          ),
/* Pads 144 ... 159 */
  (uint16)0x0000,
/* Pads 160 ... 175 */
  (uint16)0x0000,
/* Pads 176 ... 191 */
  (uint16)0x0000,
/* Pads 192 ... 207 */
  (uint16)0x0000,
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 */
  (uint16)0x0000,
/* Pads 240 ... 255 */
  (uint16)0x0000,
/* Pads 256 ... 271 */
  (uint16)0x0000
}
,
/*  Mode PORT_ALT6_FUNC_MODE: */
{
/* Pads 0 ... 15 */
  (uint16)0x0000,
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads  32 ...  47 : PORT42_LIN_6_LIN6TX */
  (uint16)( SHL_PAD_U16(10)
          ),
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads 64 ... 79 */
  (uint16)0x0000,
/* Pads  80 ...  95 : PORT87_SAI1_SAI1_MCLK_OUT */
  (uint16)( SHL_PAD_U16(7)
          ),
/* Pads 96 ... 111 */
  (uint16)0x0000,
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 */
  (uint16)0x0000,
/* Pads 144 ... 159 : PORT158_EMIOS1_E1UC_14_H_OUT */
  (uint16)( SHL_PAD_U16(14)
          ),
/* Pads 160 ... 175 */
  (uint16)0x0000,
/* Pads 176 ... 191 */
  (uint16)0x0000,
/* Pads 192 ... 207 */
  (uint16)0x0000,
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 */
  (uint16)0x0000,
/* Pads 240 ... 255 */
  (uint16)0x0000,
/* Pads 256 ... 271 */
  (uint16)0x0000
}
,
/*  Mode PORT_ALT7_FUNC_MODE: */
{
/* Pads 0 ... 15 */
  (uint16)0x0000,
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads  32 ...  47 : PORT37_SSCM_SSCM_DBG_3 */
  (uint16)( SHL_PAD_U16(5)
          ),
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads 64 ... 79 */
  (uint16)0x0000,
/* Pads  80 ...  95 : PORT80_SAI0_SAI0_MCLK_OUT */
  (uint16)( SHL_PAD_U16(0)
          ),
/* Pads 96 ... 111 */
  (uint16)0x0000,
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 */
  (uint16)0x0000,
/* Pads 144 ... 159 */
  (uint16)0x0000,
/* Pads 160 ... 175 */
  (uint16)0x0000,
/* Pads 176 ... 191 */
  (uint16)0x0000,
/* Pads 192 ... 207 */
  (uint16)0x0000,
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 */
  (uint16)0x0000,
/* Pads 240 ... 255 */
  (uint16)0x0000,
/* Pads 256 ... 271 */
  (uint16)0x0000
}
,
/*  Mode PORT_ONLY_OUTPUT_MODE: */
{
/* Pads 0 ... 15 */
  (uint16)0x0000,
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads 32 ... 47 */
  (uint16)0x0000,
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads 64 ... 79 */
  (uint16)0x0000,
/* Pads 80 ... 95 */
  (uint16)0x0000,
/* Pads  96 ... 111 : PORT102_PMCDIG_EXTREGC */
  (uint16)( SHL_PAD_U16(6)
          ),
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 */
  (uint16)0x0000,
/* Pads 144 ... 159 */
  (uint16)0x0000,
/* Pads 160 ... 175 */
  (uint16)0x0000,
/* Pads 176 ... 191 */
  (uint16)0x0000,
/* Pads 192 ... 207 */
  (uint16)0x0000,
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 */
  (uint16)0x0000,
/* Pads 240 ... 255 */
  (uint16)0x0000,
/* Pads 256 ... 271 */
  (uint16)0x0000
}
,
/*  Mode PORT_ONLY_INPUT_MODE: */
{
/* Pads   0 ...  15 : PORT0_WKPU_WKPU_19 |
PORT1_WKPU_WKPU_2 |
PORT1_WKPU_NMI_0 |
PORT2_WKPU_WKPU_3 |
PORT4_WKPU_WKPU_9 |
PORT15_WKPU_WKPU_10 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(4) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT17_WKPU_WKPU_4 |
PORT19_WKPU_WKPU_11 |
PORT20_GPI |
PORT21_GPI |
PORT22_GPI |
PORT23_GPI |
PORT24_GPI |
PORT24_WKPU_WKPU_25 |
PORT24_XOSC_OSC32K_XTAL |
PORT25_GPI |
PORT25_WKPU_WKPU_26 |
PORT25_XOSC_OSC32K_EXTAL |
PORT26_WKPU_WKPU_8 */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(8) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(9) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10)
          ),
/* Pads  32 ...  47 : PORT39_WKPU_WKPU_12 |
PORT41_WKPU_WKPU_13 |
PORT43_WKPU_WKPU_5 */
  (uint16)( SHL_PAD_U16(7) |
SHL_PAD_U16(9) |
SHL_PAD_U16(11)
          ),
/* Pads  48 ...  63 : PORT48_GPI |
PORT48_WKPU_WKPU_27 |
PORT49_GPI |
PORT49_WKPU_WKPU_28 |
PORT50_GPI |
PORT51_GPI |
PORT52_GPI |
PORT53_GPI |
PORT54_GPI |
PORT55_GPI |
PORT56_GPI |
PORT57_GPI |
PORT58_GPI |
PORT59_GPI */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11)
          ),
/* Pads  64 ...  79 : PORT64_WKPU_WKPU_6 |
PORT67_WKPU_WKPU_29 |
PORT69_WKPU_WKPU_30 |
PORT73_WKPU_WKPU_7 |
PORT75_WKPU_WKPU_14 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(3) |
SHL_PAD_U16(5) |
SHL_PAD_U16(9) |
SHL_PAD_U16(11)
          ),
/* Pads  80 ...  95 : PORT89_WKPU_WKPU_22 |
PORT90_FCCU_EOUT0_IN |
PORT91_WKPU_WKPU_15 |
PORT92_FCCU_EOUT1_IN |
PORT93_WKPU_WKPU_16 */
  (uint16)( SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13)
          ),
/* Pads  96 ... 111 : PORT99_WKPU_WKPU_17 |
PORT101_WKPU_WKPU_18 |
PORT103_WKPU_WKPU_20 |
PORT105_WKPU_WKPU_21 */
  (uint16)( SHL_PAD_U16(3) |
SHL_PAD_U16(5) |
SHL_PAD_U16(7) |
SHL_PAD_U16(9)
          ),
/* Pads 112 ... 127 : PORT122_DCI_TMS_IN |
PORT125_FCCU_EOUT1_IN |
PORT127_FCCU_EOUT0_IN */
  (uint16)( SHL_PAD_U16(10) |
SHL_PAD_U16(13) |
SHL_PAD_U16(15)
          ),
/* Pads 128 ... 143 : PORT129_WKPU_WKPU_24 |
PORT131_WKPU_WKPU_23 */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(3)
          ),
/* Pads 144 ... 159 : PORT157_WKPU_WKPU_31 */
  (uint16)( SHL_PAD_U16(13)
          ),
/* Pads 160 ... 175 */
  (uint16)0x0000,
/* Pads 176 ... 191 */
  (uint16)0x0000,
/* Pads 192 ... 207 : PORT206_DCI_TMS_ALT_IN */
  (uint16)( SHL_PAD_U16(14)
          ),
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 */
  (uint16)0x0000,
/* Pads 240 ... 255 */
  (uint16)0x0000,
/* Pads 256 ... 271 */
  (uint16)0x0000
}
,
/*  Mode PORT_ANALOG_INPUT_MODE: */
{
/* Pads   0 ...  15 : PORT3_ADC_1_ADC1_S_0 |
PORT4_CMP1_CMP1_13 |
PORT7_ADC_1_ADC1_S_8 |
PORT8_ADC_1_ADC1_S_9 |
PORT9_ADC_1_ADC1_S_10 |
PORT10_ADC_1_ADC1_S_11 |
PORT11_ADC_1_ADC1_S_12 |
PORT12_CMP1_CMP1_15 |
PORT13_CMP1_CMP1_14 |
PORT14_CMP1_CMP1_12 |
PORT15_CMP1_CMP1_10 */
  (uint16)( SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_CMP0_CMP0_2 |
PORT17_CMP0_CMP0_3 |
PORT20_ADC_1_ADC1_P_0 |
PORT21_ADC_1_ADC1_P_1 |
PORT22_ADC_1_ADC1_P_2 |
PORT23_ADC_1_ADC1_P_3 |
PORT24_ADC_0_ADC0_S_0 |
PORT25_ADC_0_ADC0_S_1 |
PORT26_ADC_0_ADC0_S_2 |
PORT27_ADC_0_ADC0_S_3 |
PORT28_ADC_0_ADC0_X_0 |
PORT29_ADC_0_ADC0_X_1 |
PORT30_ADC_0_ADC0_X_2 |
PORT31_ADC_0_ADC0_X_3 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  32 ...  47 : PORT38_CMP0_CMP0_7 */
  (uint16)( SHL_PAD_U16(6)
          ),
/* Pads  48 ...  63 : PORT48_ADC_1_ADC1_P_4 |
PORT49_ADC_1_ADC1_P_5 |
PORT50_ADC_1_ADC1_P_6 |
PORT51_ADC_1_ADC1_P_7 |
PORT52_ADC_1_ADC1_P_8 |
PORT53_ADC_1_ADC1_P_9 |
PORT54_ADC_1_ADC1_P_10 |
PORT55_ADC_1_ADC1_P_11 |
PORT56_ADC_1_ADC1_P_12 |
PORT57_ADC_1_ADC1_P_13 |
PORT58_ADC_1_ADC1_P_14 |
PORT59_ADC_1_ADC1_P_15 |
PORT60_ADC_0_ADC0_S_4 |
PORT61_ADC_0_ADC0_S_5 |
PORT62_ADC_0_ADC0_S_6 |
PORT63_ADC_0_ADC0_S_7 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  64 ...  79 : PORT76_ADC_1_ADC1_S_13 |
PORT77_ADC_1_ADC1_X_3 */
  (uint16)( SHL_PAD_U16(12) |
SHL_PAD_U16(13)
          ),
/* Pads  80 ...  95 : PORT80_ADC_0_ADC0_S_8 |
PORT80_CMP2_CMP2_16 |
PORT81_ADC_0_ADC0_S_9 |
PORT81_CMP2_CMP2_17 |
PORT82_ADC_0_ADC0_S_10 |
PORT82_CMP2_CMP2_18 |
PORT83_ADC_0_ADC0_S_11 |
PORT83_CMP2_CMP2_19 |
PORT84_ADC_0_ADC0_S_12 |
PORT84_CMP2_CMP2_20 |
PORT85_ADC_0_ADC0_S_13 |
PORT85_CMP2_CMP2_21 |
PORT86_ADC_0_ADC0_S_14 |
PORT86_CMP2_CMP2_22 |
PORT87_ADC_0_ADC0_S_15 |
PORT87_CMP2_CMP2_23 |
PORT88_CMP0_CMP0_5 |
PORT89_CMP0_CMP0_4 |
PORT90_CMP1_CMP1_8 |
PORT91_CMP1_CMP1_9 |
PORT92_CMP0_CMP0_6 |
PORT93_CMP1_CMP1_11 |
PORT94_ADC_1_ADC1_X_2 |
PORT95_ADC_1_ADC1_X_1 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT96_ADC_1_ADC1_X_0 |
PORT97_ADC_1_ADC1_S_7 |
PORT102_CMP0_CMP0_1 |
PORT103_CMP0_CMP0_0 |
PORT108_ADC_1_ADC1_S_2 |
PORT109_ADC_1_ADC1_S_1 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13)
          ),
/* Pads 112 ... 127 : PORT112_ADC_1_ADC1_S_3 |
PORT113_ADC_1_ADC1_S_4 |
PORT114_ADC_1_ADC1_S_5 |
PORT115_ADC_1_ADC1_S_6 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3)
          ),
/* Pads 128 ... 143 : PORT136_ADC_0_ADC0_S_16 |
PORT137_ADC_0_ADC0_S_17 |
PORT138_ADC_0_ADC0_S_18 |
PORT139_ADC_0_ADC0_S_19 |
PORT140_ADC_0_ADC0_S_20 |
PORT141_ADC_0_ADC0_S_21 |
PORT142_ADC_0_ADC0_S_22 |
PORT143_ADC_0_ADC0_S_23 */
  (uint16)( SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 144 ... 159 : PORT144_ADC_0_ADC0_S_24 |
PORT145_ADC_0_ADC0_S_25 |
PORT146_ADC_0_ADC0_S_26 |
PORT147_ADC_0_ADC0_S_27 |
PORT149_ADC_0_ADC0_S_28 |
PORT150_ADC_0_ADC0_S_29 |
PORT151_ADC_0_ADC0_S_30 |
PORT152_ADC_0_ADC0_S_31 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8)
          ),
/* Pads 160 ... 175 */
  (uint16)0x0000,
/* Pads 176 ... 191 : PORT177_ADC_0_ADC0_S_47 */
  (uint16)( SHL_PAD_U16(1)
          ),
/* Pads 192 ... 207 : PORT195_ADC_0_ADC0_S_46 |
PORT196_ADC_0_ADC0_S_45 |
PORT197_ADC_0_ADC0_S_44 |
PORT206_ADC_1_ADC1_S_15 */
  (uint16)( SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(14)
          ),
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 */
  (uint16)0x0000,
/* Pads 240 ... 255 */
  (uint16)0x0000,
/* Pads 256 ... 271 */
  (uint16)0x0000
}
,
/*  Mode PORT_INPUT1_MODE: */
{
/* Pads   0 ...  15 : PORT0_EMIOS0_E0UC_0_X_IN |
PORT1_EMIOS0_E0UC_1_G_IN |
PORT2_EMIOS0_E0UC_2_G_IN |
PORT3_EMIOS0_E0UC_3_G_IN |
PORT4_EMIOS0_E0UC_4_G_IN |
PORT5_EMIOS0_E0UC_5_G_IN |
PORT6_EMIOS0_E0UC_6_G_IN |
PORT7_EMIOS0_E0UC_7_G_IN |
PORT8_EMIOS0_E0UC_8_X_IN |
PORT9_EMIOS0_E0UC_9_H_IN |
PORT10_EMIOS0_E0UC_10_H_IN |
PORT11_EMIOS0_E0UC_11_H_IN |
PORT12_EMIOS0_E0UC_28_Y_IN |
PORT13_EMIOS0_E0UC_29_Y_IN |
PORT14_EMIOS0_E0UC_0_X_IN |
PORT15_EMIOS0_E0UC_1_G_IN */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_EMIOS0_E0UC_30_Y_IN |
PORT17_EMIOS0_E0UC_31_Y_IN |
PORT18_EMIOS0_E0UC_30_Y_IN |
PORT19_EMIOS0_E0UC_31_Y_IN |
PORT26_FlexCAN_6_RX |
PORT27_EMIOS0_E0UC_3_G_IN |
PORT28_EMIOS0_E0UC_4_G_IN |
PORT29_EMIOS0_E0UC_5_G_IN |
PORT30_EMIOS0_E0UC_6_G_IN |
PORT31_EMIOS0_E0UC_7_G_IN */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  32 ...  47 : PORT34_SIUL2_EIRQ5 |
PORT35_SIUL2_EIRQ6 |
PORT36_EMIOS1_E1UC_31_Y_IN |
PORT37_SIUL2_EIRQ7 |
PORT38_EMIOS1_E1UC_28_Y_IN |
PORT39_EMIOS1_E1UC_29_Y_IN |
PORT40_EMIOS0_E0UC_3_G_IN |
PORT41_EMIOS0_E0UC_7_G_IN |
PORT43_FlexCAN_1_RX |
PORT44_EMIOS0_E0UC_12_H_IN |
PORT45_EMIOS0_E0UC_13_H_IN |
PORT46_EMIOS0_E0UC_14_H_IN |
PORT47_EMIOS0_E0UC_15_H_IN */
  (uint16)( SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  48 ...  63 : PORT60_EMIOS0_E0UC_24_X_IN |
PORT61_EMIOS0_E0UC_25_Y_IN |
PORT62_EMIOS0_E0UC_26_Y_IN |
PORT63_EMIOS0_E0UC_27_Y_IN */
  (uint16)( SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  64 ...  79 : PORT64_EMIOS0_E0UC_16_X_IN |
PORT65_EMIOS0_E0UC_17_Y_IN |
PORT66_EMIOS0_E0UC_18_Y_IN |
PORT67_EMIOS0_E0UC_19_Y_IN |
PORT68_EMIOS0_E0UC_20_Y_IN |
PORT69_EMIOS0_E0UC_21_Y_IN |
PORT70_EMIOS0_E0UC_22_X_IN |
PORT71_EMIOS0_E0UC_23_X_IN |
PORT72_EMIOS0_E0UC_22_X_IN |
PORT73_EMIOS0_E0UC_23_X_IN |
PORT74_EMIOS1_E1UC_30_Y_IN |
PORT75_EMIOS0_E0UC_24_X_IN |
PORT76_EMIOS1_E1UC_19_Y_IN |
PORT77_EMIOS1_E1UC_20_Y_IN |
PORT78_EMIOS1_E1UC_21_Y_IN |
PORT79_EMIOS1_E1UC_22_X_IN */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT80_EMIOS0_E0UC_10_H_IN |
PORT81_EMIOS0_E0UC_11_H_IN |
PORT82_EMIOS0_E0UC_12_H_IN |
PORT83_EMIOS0_E0UC_13_H_IN |
PORT84_EMIOS0_E0UC_14_H_IN |
PORT85_EMIOS0_E0UC_22_X_IN |
PORT86_EMIOS0_E0UC_23_X_IN |
PORT87_SPI_0_SCLK_0_IN |
PORT88_EMIOS0_E0UC_15_H_IN |
PORT89_EMIOS1_E1UC_1_H_IN |
PORT90_EMIOS1_E1UC_2_H_IN |
PORT91_EMIOS1_E1UC_3_H_IN |
PORT92_EMIOS1_E1UC_25_Y_IN |
PORT93_EMIOS1_E1UC_26_Y_IN |
PORT94_EMIOS1_E1UC_27_Y_IN |
PORT95_EMIOS1_E1UC_4_H_IN */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT96_EMIOS1_E1UC_23_X_IN |
PORT97_EMIOS1_E1UC_24_X_IN |
PORT98_EMIOS1_E1UC_11_H_IN |
PORT99_EMIOS1_E1UC_12_H_IN |
PORT100_EMIOS1_E1UC_13_H_IN |
PORT101_EMIOS1_E1UC_14_H_IN |
PORT102_EMIOS1_E1UC_15_H_IN |
PORT103_EMIOS1_E1UC_16_X_IN |
PORT104_EMIOS1_E1UC_17_Y_IN |
PORT105_EMIOS1_E1UC_18_Y_IN |
PORT106_EMIOS0_E0UC_24_X_IN |
PORT107_EMIOS0_E0UC_25_Y_IN |
PORT108_EMIOS0_E0UC_26_Y_IN |
PORT109_EMIOS0_E0UC_27_Y_IN |
PORT110_EMIOS1_E1UC_0_X_IN |
PORT111_EMIOS1_E1UC_1_H_IN */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 112 ... 127 : PORT112_EMIOS1_E1UC_2_H_IN |
PORT113_EMIOS1_E1UC_3_H_IN |
PORT114_EMIOS1_E1UC_4_H_IN |
PORT115_EMIOS1_E1UC_5_H_IN |
PORT116_EMIOS1_E1UC_6_H_IN |
PORT117_EMIOS1_E1UC_7_H_IN |
PORT118_EMIOS1_E1UC_8_X_IN |
PORT119_EMIOS1_E1UC_9_H_IN |
PORT120_EMIOS1_E1UC_10_H_IN |
PORT123_EMIOS1_E1UC_5_H_IN |
PORT124_EMIOS1_E1UC_25_Y_IN |
PORT125_EMIOS1_E1UC_26_Y_IN |
PORT126_EMIOS1_E1UC_27_Y_IN |
PORT127_EMIOS1_E1UC_17_Y_IN */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 128 ... 143 : PORT128_EMIOS0_E0UC_28_Y_IN |
PORT129_EMIOS0_E0UC_29_Y_IN |
PORT130_EMIOS0_E0UC_30_Y_IN |
PORT131_EMIOS0_E0UC_31_Y_IN |
PORT132_EMIOS1_E1UC_28_Y_IN |
PORT133_EMIOS1_E1UC_29_Y_IN |
PORT134_EMIOS1_E1UC_30_Y_IN |
PORT135_EMIOS1_E1UC_31_Y_IN |
PORT139_DSPI_3_dSIN |
PORT140_DSPI_2_dSS |
PORT142_SPI_0_SIN_0 |
PORT143_SPI_0_SS_0 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 144 ... 159 : PORT144_SAI2_SAI2_SYNC_IN |
PORT145_SPI_1_SIN_1 |
PORT146_SPI_1_SS_1 |
PORT147_SAI1_SAI1_BCLK_IN |
PORT148_EMIOS1_E1UC_18_Y_IN |
PORT149_SAI2_SAI2_D0_IN |
PORT150_SAI2_SAI2_BCLK_IN |
PORT151_SAI2_SAI2_MCLK_IN |
PORT152_SAI2_SAI2_SYNC_IN |
PORT153_EMIOS1_E1UC_17_Y_IN |
PORT154_EMIOS1_E1UC_16_X_IN |
PORT155_EMIOS1_E1UC_11_H_IN |
PORT156_EMIOS1_E1UC_10_H_IN |
PORT157_EMIOS1_E1UC_15_H_IN |
PORT158_EMIOS1_E1UC_14_H_IN |
PORT159_EMIOS1_E1UC_13_H_IN */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 160 ... 175 : PORT160_EMIOS1_E1UC_12_H_IN |
PORT161_EMIOS1_E1UC_1_H_IN |
PORT162_EMIOS1_E1UC_2_H_IN |
PORT163_EMIOS1_E1UC_0_X_IN |
PORT164_EMIOS1_E1UC_1_H_IN |
PORT165_EMIOS1_E1UC_4_H_IN |
PORT166_EMIOS1_E1UC_5_H_IN |
PORT167_EMIOS1_E1UC_6_H_IN |
PORT168_EMIOS1_E1UC_7_H_IN |
PORT169_EMIOS1_E1UC_29_Y_IN |
PORT170_EMIOS1_E1UC_30_Y_IN |
PORT171_EMIOS1_E1UC_31_Y_IN |
PORT172_EMIOS0_E0UC_0_X_IN |
PORT173_EMIOS0_E0UC_1_G_IN |
PORT174_EMIOS0_E0UC_2_G_IN |
PORT175_EMIOS0_E0UC_3_G_IN */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 176 ... 191 : PORT176_EMIOS0_E0UC_4_G_IN |
PORT177_SAI0_SAI0_D0_IN */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1)
          ),
/* Pads 192 ... 207 : PORT195_SAI0_SAI0_D1_IN |
PORT196_SAI0_SAI0_D2_IN |
PORT197_SAI0_SAI0_D3_IN |
PORT206_SAI0_SAI0_MCLK_IN */
  (uint16)( SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(14)
          ),
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 : PORT224_IIC_0_SDA0_IN |
PORT225_LIN_12_LIN12RX */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1)
          ),
/* Pads 240 ... 255 : PORT252_EMIOS1_E1UC_24_X_IN |
PORT253_EMIOS1_E1UC_23_X_IN |
PORT254_EMIOS1_E1UC_22_X_IN |
PORT255_EMIOS1_E1UC_21_Y_IN */
  (uint16)( SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 256 ... 271 : PORT257_DSPI_0_dSS |
PORT258_DSPI_0_dSCLK_IN |
PORT259_DSPI_0_dSIN |
PORT260_EMIOS1_E1UC_28_Y_IN |
PORT261_EMIOS1_E1UC_27_Y_IN |
PORT262_EMIOS1_E1UC_26_Y_IN |
PORT263_EMIOS1_E1UC_25_Y_IN */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7)
          )
}
,
/*  Mode PORT_INPUT2_MODE: */
{
/* Pads   0 ...  15 : PORT0_EMIOS0_E0UC_13_H_IN |
PORT1_FlexCAN_3_RX |
PORT3_SIUL2_EIRQ0 |
PORT4_LIN_5_LIN5RX |
PORT6_SIUL2_EIRQ1 |
PORT7_SIUL2_EIRQ2 |
PORT8_EMIOS0_E0UC_14_H_IN |
PORT9_ENET0_MII_RMII_0_RXD_0 |
PORT10_IIC_0_SDA0_IN |
PORT11_SIUL2_EIRQ16 |
PORT12_SIUL2_EIRQ17 |
PORT13_EMIOS0_E0UC_25_Y_IN |
PORT14_SIUL2_EIRQ4 |
PORT15_FlexCAN_0_RX */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_EMIOS0_E0UC_4_G_IN |
PORT17_FlexCAN_0_RX |
PORT18_IIC_0_SDA0_IN |
PORT19_LIN_0_LIN0RX |
PORT26_SAI0_SAI0_SYNC_IN |
PORT27_DSPI_0_dSS */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11)
          ),
/* Pads  32 ...  47 : PORT34_DSPI_1_dSCLK_IN |
PORT35_FlexCAN_1_RX |
PORT36_SIUL2_EIRQ18 |
PORT38_EMIOS0_E0UC_17_Y_IN |
PORT39_LIN_1_LIN1RX |
PORT41_LIN_2_LIN2RX |
PORT43_FlexCAN_4_RX |
PORT44_SIUL2_EIRQ19 |
PORT46_SIUL2_EIRQ8 |
PORT47_SIUL2_EIRQ20 */
  (uint16)( SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(9) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  48 ...  63 : PORT61_DSPI_1_dSS */
  (uint16)( SHL_PAD_U16(13)
          ),
/* Pads  64 ...  79 : PORT64_FlexCAN_5_RX |
PORT65_IIC_1_SDA1_IN |
PORT66_SIUL2_EIRQ21 |
PORT67_FlexRay_FR_A_RX |
PORT68_SIUL2_EIRQ9 |
PORT69_FlexRay_FR_B_RX |
PORT70_SIUL2_EIRQ22 |
PORT71_SIUL2_EIRQ23 |
PORT72_IIC_2_SDA2_IN |
PORT73_FlexCAN_2_RX |
PORT74_SIUL2_EIRQ10 |
PORT75_LIN_3_LIN3RX |
PORT76_SIUL2_EIRQ11 |
PORT77_ENET0_MII_0_RXD_3 |
PORT78_SIUL2_EIRQ12 |
PORT79_DSPI_2_dSS */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT80_SAI0_SAI0_MCLK_IN |
PORT81_SAI0_SAI0_BCLK_IN |
PORT82_DSPI_2_dSS |
PORT83_SAI0_SAI0_D2_IN |
PORT84_SAI0_SAI0_D1_IN |
PORT85_SAI0_SAI0_D0_IN |
PORT86_SAI1_SAI1_SYNC_IN |
PORT87_SAI1_SAI1_MCLK_IN |
PORT89_FlexCAN_2_RX |
PORT90_EMIOS0_E0UC_19_Y_IN |
PORT91_LIN_4_LIN4RX |
PORT92_EMIOS0_E0UC_16_X_IN |
PORT93_LIN_5_LIN5RX |
PORT94_ENET0_MII_RMII_0_MDIO_IN |
PORT95_SIUL2_EIRQ13 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT97_SIUL2_EIRQ14 |
PORT99_FlexCAN_7_RX |
PORT100_DSPI_3_dSCLK_IN |
PORT101_LIN_10_LIN10RX |
PORT102_EMIOS0_E0UC_3_G_IN |
PORT103_EMIOS1_E1UC_30_Y_IN |
PORT104_SIUL2_EIRQ15 |
PORT105_FlexCAN_7_RX |
PORT106_EMIOS1_E1UC_31_Y_IN |
PORT107_SPI_0_SS_0 |
PORT109_SPI_0_SCLK_0_IN |
PORT110_SPI_2_SIN_2 |
PORT111_LIN_8_LIN8RX */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 112 ... 127 : PORT112_DSPI_1_dSIN |
PORT114_DSPI_1_dSCLK_IN |
PORT115_DSPI_1_dSS |
PORT116_IIC_3_SCL3_IN |
PORT117_IIC_3_SDA3_IN |
PORT118_SPI_3_SCLK_3_IN |
PORT119_SPI_3_SS_3 |
PORT123_SPI_0_SS_0 |
PORT124_DSPI_3_dSCLK_IN |
PORT125_DSPI_3_dSS |
PORT126_SPI_0_SCLK_0_IN */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14)
          ),
/* Pads 128 ... 143 : PORT128_IIC_1_SDA1_IN |
PORT129_LIN_8_LIN8RX |
PORT130_IIC_2_SDA2_IN |
PORT131_LIN_9_LIN9RX |
PORT132_GLITCH_FILTER2_INP |
PORT133_SPI_0_SCLK_0_IN |
PORT134_SPI_0_SS_0 |
PORT135_GLITCH_FILTER3_INP |
PORT139_ENET0_ENET0_TMR1_IN |
PORT140_DSPI_3_dSS |
PORT142_SAI2_SAI2_D0_IN |
PORT143_SAI2_SAI2_MCLK_IN */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 144 ... 159 : PORT145_SAI2_SAI2_BCLK_IN |
PORT146_SPI_2_SS_2 |
PORT148_SPI_1_SCLK_1_IN |
PORT154_FlexCAN_4_RX |
PORT156_FlexCAN_2_RX |
PORT157_FlexCAN_1_RX |
PORT159_FlexCAN_1_RX */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(4) |
SHL_PAD_U16(10) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(15)
          ),
/* Pads 160 ... 175 : PORT161_FlexCAN_4_RX |
PORT163_EMIOS1_E1UC_3_H_IN |
PORT164_EMIOS0_E0UC_9_H_IN |
PORT165_FlexCAN_2_RX |
PORT166_EMIOS0_E0UC_11_H_IN |
PORT167_FlexCAN_3_RX |
PORT168_EMIOS0_E0UC_13_H_IN |
PORT169_LIN_15_LIN15RX |
PORT170_GLITCH_FILTER3_INP |
PORT171_SPI_0_SCLK_0_IN |
PORT172_LIN_14_LIN14RX |
PORT173_FlexCAN_3_RX |
PORT174_SPI_1_SS_1 |
PORT175_SPI_1_SIN_1 */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 176 ... 191 : PORT176_LIN_13_LIN13RX */
  (uint16)( SHL_PAD_U16(0)
          ),
/* Pads 192 ... 207 : PORT195_ENET0_ENET0_TMR2_IN */
  (uint16)( SHL_PAD_U16(3)
          ),
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 : PORT225_IIC_0_SCL0_IN */
  (uint16)( SHL_PAD_U16(1)
          ),
/* Pads 240 ... 255 : PORT252_SPI_2_SS_2 |
PORT254_SPI_2_SCLK_2_IN |
PORT255_SPI_2_SIN_2 */
  (uint16)( SHL_PAD_U16(12) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 256 ... 271 : PORT260_GLITCH_FILTER2_INP */
  (uint16)( SHL_PAD_U16(4)
          )
}
,
/*  Mode PORT_INPUT3_MODE: */
{
/* Pads   0 ...  15 : PORT0_FlexCAN_1_RX |
PORT3_ENET0_MII_0_RX_CLK |
PORT4_DSPI_1_dSS |
PORT6_LIN_4_LIN4RX |
PORT7_ENET0_MII_0_RXD_2 |
PORT8_SIUL2_EIRQ3 |
PORT10_DSPI_1_dSIN |
PORT11_LIN_2_LIN2RX |
PORT12_DSPI_0_dSIN |
PORT13_GLITCH_FILTER0_INP |
PORT14_DSPI_0_dSCLK_IN |
PORT15_DSPI_0_dSCLK_IN */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_GLITCH_FILTER1_INP |
PORT17_LIN_0_LIN0RX |
PORT18_GLITCH_FILTER1_INP |
PORT19_IIC_0_SCL0_IN |
PORT26_EMIOS0_E0UC_29_Y_IN */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(10)
          ),
/* Pads  32 ...  47 : PORT35_FlexCAN_4_RX |
PORT36_FlexCAN_3_RX |
PORT38_GLITCH_FILTER2_INP |
PORT39_EMIOS0_E0UC_18_Y_IN |
PORT43_EMIOS0_E0UC_1_G_IN |
PORT44_DSPI_2_dSIN |
PORT46_DSPI_2_dSCLK_IN |
PORT47_DSPI_2_dSS */
  (uint16)( SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  48 ...  63 : PORT61_ENET0_ENET0_TMR0_IN */
  (uint16)( SHL_PAD_U16(13)
          ),
/* Pads  64 ...  79 : PORT64_LIN_11_LIN11RX |
PORT66_DSPI_1_dSIN |
PORT68_DSPI_1_dSCLK_IN |
PORT69_DSPI_1_dSS |
PORT73_FlexCAN_3_RX |
PORT74_IIC_3_SDA3_IN |
PORT75_IIC_3_SCL3_IN |
PORT76_DSPI_2_dSIN |
PORT78_DSPI_2_dSCLK_IN |
PORT79_SPI_2_SCLK_2_IN */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(2) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT82_SAI0_SAI0_D3_IN |
PORT83_GLITCH_FILTER1_INP |
PORT84_GLITCH_FILTER2_INP |
PORT85_GLITCH_FILTER3_INP |
PORT86_EMIOS0_E0UC_30_Y_IN |
PORT89_FlexCAN_3_RX |
PORT91_EMIOS0_E0UC_20_Y_IN |
PORT93_EMIOS0_E0UC_22_X_IN |
PORT95_FlexCAN_1_RX */
  (uint16)( SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(9) |
SHL_PAD_U16(11) |
SHL_PAD_U16(13) |
SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT97_FlexCAN_5_RX |
PORT99_DSPI_3_dSS |
PORT101_DSPI_3_dSIN |
PORT103_LIN_6_LIN6RX |
PORT104_DSPI_2_dSS |
PORT105_LIN_7_LIN7RX |
PORT106_SPI_0_SIN_0 |
PORT107_SPI_2_SS_2 */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(3) |
SHL_PAD_U16(5) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11)
          ),
/* Pads 112 ... 127 : PORT117_SPI_3_SIN_3 |
PORT126_FCCU_EIN_ERR */
  (uint16)( SHL_PAD_U16(5) |
SHL_PAD_U16(14)
          ),
/* Pads 128 ... 143 : PORT128_GLITCH_FILTER0_INP |
PORT129_IIC_1_SCL1_IN |
PORT130_GLITCH_FILTER1_INP |
PORT131_IIC_2_SCL2_IN |
PORT133_GLITCH_FILTER2_INP |
PORT134_SPI_1_SS_1 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6)
          ),
/* Pads 144 ... 159 : PORT146_SPI_3_SS_3 |
PORT148_FCCU_EIN_ERR |
PORT157_FlexCAN_4_RX |
PORT159_FlexCAN_3_RX */
  (uint16)( SHL_PAD_U16(2) |
SHL_PAD_U16(4) |
SHL_PAD_U16(13) |
SHL_PAD_U16(15)
          ),
/* Pads 160 ... 175 : PORT161_EMIOS0_E0UC_6_G_IN |
PORT163_SIUL2_EIRQ31 |
PORT165_LIN_2_LIN2RX |
PORT167_LIN_3_LIN3RX |
PORT169_SPI_0_SIN_0 |
PORT171_GLITCH_FILTER3_INP |
PORT172_SPI_0_SS_0 |
PORT173_SPI_1_SCLK_1_IN |
PORT175_SPI_3_SIN_3 */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(3) |
SHL_PAD_U16(5) |
SHL_PAD_U16(7) |
SHL_PAD_U16(9) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(15)
          ),
/* Pads 176 ... 191 */
  (uint16)0x0000,
/* Pads 192 ... 207 */
  (uint16)0x0000,
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 */
  (uint16)0x0000,
/* Pads 240 ... 255 */
  (uint16)0x0000,
/* Pads 256 ... 271 */
  (uint16)0x0000
}
,
/*  Mode PORT_INPUT4_MODE: */
{
/* Pads   0 ...  15 : PORT4_EMIOS0_E0UC_24_X_IN |
PORT8_LIN_3_LIN3RX |
PORT10_ENET0_MII_0_COL |
PORT11_IIC_0_SCL0_IN |
PORT12_EMIOS0_E0UC_26_Y_IN |
PORT14_DSPI_0_dSS |
PORT15_DSPI_0_dSS */
  (uint16)( SHL_PAD_U16(4) |
SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT17_EMIOS0_E0UC_5_G_IN |
PORT19_EMIOS0_E0UC_8_X_IN */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(3)
          ),
/* Pads  32 ...  47 : PORT35_DSPI_1_dSS |
PORT36_DSPI_1_dSIN |
PORT39_GLITCH_FILTER2_INP |
PORT47_FlexCAN_4_RX */
  (uint16)( SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(7) |
SHL_PAD_U16(15)
          ),
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads  64 ...  79 : PORT64_IIC_1_SCL1_IN |
PORT73_IIC_2_SCL2_IN |
PORT74_GLITCH_FILTER3_INP |
PORT76_ENET0_MII_0_CRS */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(12)
          ),
/* Pads  80 ...  95 : PORT82_GLITCH_FILTER0_INP |
PORT89_EMIOS0_E0UC_14_H_IN |
PORT95_FlexCAN_4_RX */
  (uint16)( SHL_PAD_U16(2) |
SHL_PAD_U16(9) |
SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT97_ENET0_MII_RMII_0_TX_CLK_IN |
PORT101_EMIOS0_E0UC_2_G_IN |
PORT103_GLITCH_FILTER3_INP |
PORT105_DSPI_2_dSCLK_IN |
PORT106_GLITCH_FILTER3_INP */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(5) |
SHL_PAD_U16(7) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10)
          ),
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 : PORT129_GLITCH_FILTER0_INP |
PORT131_GLITCH_FILTER1_INP |
PORT134_SPI_2_SS_2 */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(3) |
SHL_PAD_U16(6)
          ),
/* Pads 144 ... 159 : PORT146_SAI1_SAI1_D0_IN |
PORT157_FlexCAN_6_RX */
  (uint16)( SHL_PAD_U16(2) |
SHL_PAD_U16(13)
          ),
/* Pads 160 ... 175 : PORT163_FlexCAN_5_RX |
PORT165_EMIOS0_E0UC_10_H_IN |
PORT167_EMIOS0_E0UC_12_H_IN |
PORT169_GLITCH_FILTER2_INP */
  (uint16)( SHL_PAD_U16(3) |
SHL_PAD_U16(5) |
SHL_PAD_U16(7) |
SHL_PAD_U16(9)
          ),
/* Pads 176 ... 191 */
  (uint16)0x0000,
/* Pads 192 ... 207 */
  (uint16)0x0000,
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 */
  (uint16)0x0000,
/* Pads 240 ... 255 */
  (uint16)0x0000,
/* Pads 256 ... 271 */
  (uint16)0x0000
}
,
/*  Mode PORT_INPUT5_MODE: */
{
/* Pads   0 ...  15 : PORT8_ENET0_MII_RMII_0_RXD_1 |
PORT11_ENET0_MII_RMII_0_RX_ER |
PORT12_GLITCH_FILTER0_INP |
PORT14_EMIOS0_E0UC_23_X_IN |
PORT15_EMIOS0_E0UC_21_Y_IN */
  (uint16)( SHL_PAD_U16(8) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT17_GLITCH_FILTER1_INP |
PORT19_GLITCH_FILTER1_INP */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(3)
          ),
/* Pads  32 ...  47 : PORT36_GLITCH_FILTER3_INP */
  (uint16)( SHL_PAD_U16(4)
          ),
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads 64 ... 79 */
  (uint16)0x0000,
/* Pads  80 ...  95 : PORT95_ENET0_MII_RMII_0_RX_DV */
  (uint16)( SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT105_EMIOS0_E0UC_0_X_IN */
  (uint16)( SHL_PAD_U16(9)
          ),
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 : PORT134_GLITCH_FILTER3_INP */
  (uint16)( SHL_PAD_U16(6)
          ),
/* Pads 144 ... 159 */
  (uint16)0x0000,
/* Pads 160 ... 175 : PORT163_LIN_8_LIN8RX */
  (uint16)( SHL_PAD_U16(3)
          ),
/* Pads 176 ... 191 */
  (uint16)0x0000,
/* Pads 192 ... 207 */
  (uint16)0x0000,
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 */
  (uint16)0x0000,
/* Pads 240 ... 255 */
  (uint16)0x0000,
/* Pads 256 ... 271 */
  (uint16)0x0000
}
,
/*  Mode PORT_INPUT6_MODE: */
{
/* Pads 0 ... 15 */
  (uint16)0x0000,
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads 32 ... 47 */
  (uint16)0x0000,
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads 64 ... 79 */
  (uint16)0x0000,
/* Pads 80 ... 95 */
  (uint16)0x0000,
/* Pads 96 ... 111 */
  (uint16)0x0000,
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 */
  (uint16)0x0000,
/* Pads 144 ... 159 */
  (uint16)0x0000,
/* Pads 160 ... 175 */
  (uint16)0x0000,
/* Pads 176 ... 191 */
  (uint16)0x0000,
/* Pads 192 ... 207 */
  (uint16)0x0000,
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 */
  (uint16)0x0000,
/* Pads 240 ... 255 */
  (uint16)0x0000,
/* Pads 256 ... 271 */
  (uint16)0x0000
}
,
/*  Mode PORT_INOUT1_MODE: */
{
/* Pads   0 ...  15 : PORT0_EMIOS0_E0UC_0_X_IN_OUT |
PORT1_EMIOS0_E0UC_1_G_IN_OUT |
PORT2_EMIOS0_E0UC_2_G_IN_OUT |
PORT3_EMIOS0_E0UC_3_G_IN_OUT |
PORT4_EMIOS0_E0UC_4_G_IN_OUT |
PORT5_EMIOS0_E0UC_5_G_IN_OUT |
PORT6_EMIOS0_E0UC_6_G_IN_OUT |
PORT7_EMIOS0_E0UC_7_G_IN_OUT |
PORT8_EMIOS0_E0UC_8_X_IN_OUT |
PORT9_EMIOS0_E0UC_9_H_IN_OUT |
PORT10_EMIOS0_E0UC_10_H_IN_OUT |
PORT11_EMIOS0_E0UC_11_H_IN_OUT |
PORT12_EMIOS0_E0UC_28_Y_IN_OUT |
PORT14_DSPI_0_dSCLK_IN_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14)
          ),
/* Pads  16 ...  31 : PORT17_EMIOS0_E0UC_31_Y_IN_OUT |
PORT19_EMIOS0_E0UC_31_Y_IN_OUT |
PORT27_EMIOS0_E0UC_3_G_IN_OUT |
PORT28_EMIOS0_E0UC_4_G_IN_OUT |
PORT29_EMIOS0_E0UC_5_G_IN_OUT |
PORT30_EMIOS0_E0UC_6_G_IN_OUT |
PORT31_EMIOS0_E0UC_7_G_IN_OUT */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(3) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  32 ...  47 : PORT34_DSPI_1_dSCLK_IN_OUT |
PORT36_EMIOS1_E1UC_31_Y_IN_OUT |
PORT39_EMIOS1_E1UC_29_Y_IN_OUT |
PORT41_EMIOS0_E0UC_7_G_IN_OUT |
PORT44_EMIOS0_E0UC_12_H_IN_OUT |
PORT45_EMIOS0_E0UC_13_H_IN_OUT |
PORT46_EMIOS0_E0UC_14_H_IN_OUT |
PORT47_EMIOS0_E0UC_15_H_IN_OUT */
  (uint16)( SHL_PAD_U16(2) |
SHL_PAD_U16(4) |
SHL_PAD_U16(7) |
SHL_PAD_U16(9) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads  64 ...  79 : PORT64_EMIOS0_E0UC_16_X_IN_OUT |
PORT65_EMIOS0_E0UC_17_Y_IN_OUT |
PORT66_EMIOS0_E0UC_18_Y_IN_OUT |
PORT67_EMIOS0_E0UC_19_Y_IN_OUT |
PORT68_EMIOS0_E0UC_20_Y_IN_OUT |
PORT69_EMIOS0_E0UC_21_Y_IN_OUT |
PORT70_EMIOS0_E0UC_22_X_IN_OUT |
PORT71_EMIOS0_E0UC_23_X_IN_OUT |
PORT73_EMIOS0_E0UC_23_X_IN_OUT |
PORT75_EMIOS0_E0UC_24_X_IN_OUT |
PORT76_EMIOS1_E1UC_19_Y_IN_OUT |
PORT78_DSPI_2_dSCLK_IN_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(9) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14)
          ),
/* Pads  80 ...  95 : PORT80_EMIOS0_E0UC_10_H_IN_OUT |
PORT81_EMIOS0_E0UC_11_H_IN_OUT |
PORT82_EMIOS0_E0UC_12_H_IN_OUT |
PORT83_EMIOS0_E0UC_13_H_IN_OUT |
PORT84_EMIOS0_E0UC_14_H_IN_OUT |
PORT85_EMIOS0_E0UC_22_X_IN_OUT |
PORT86_EMIOS0_E0UC_23_X_IN_OUT |
PORT87_SPI_0_SCLK_0_IN_OUT |
PORT89_EMIOS1_E1UC_1_H_IN_OUT |
PORT92_EMIOS1_E1UC_25_Y_IN_OUT |
PORT93_EMIOS1_E1UC_26_Y_IN_OUT |
PORT95_EMIOS1_E1UC_4_H_IN_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(9) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT97_EMIOS1_E1UC_24_X_IN_OUT |
PORT98_EMIOS1_E1UC_11_H_IN_OUT |
PORT99_EMIOS1_E1UC_12_H_IN_OUT |
PORT100_EMIOS1_E1UC_13_H_IN_OUT |
PORT101_EMIOS1_E1UC_14_H_IN_OUT |
PORT102_EMIOS1_E1UC_15_H_IN_OUT |
PORT103_EMIOS1_E1UC_16_X_IN_OUT |
PORT104_EMIOS1_E1UC_17_Y_IN_OUT |
PORT105_EMIOS1_E1UC_18_Y_IN_OUT |
PORT106_EMIOS0_E0UC_24_X_IN_OUT |
PORT107_EMIOS0_E0UC_25_Y_IN_OUT |
PORT108_EMIOS0_E0UC_26_Y_IN_OUT |
PORT109_EMIOS0_E0UC_27_Y_IN_OUT |
PORT110_EMIOS1_E1UC_0_X_IN_OUT |
PORT111_EMIOS1_E1UC_1_H_IN_OUT */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 112 ... 127 : PORT112_EMIOS1_E1UC_2_H_IN_OUT |
PORT113_EMIOS1_E1UC_3_H_IN_OUT |
PORT114_EMIOS1_E1UC_4_H_IN_OUT |
PORT115_EMIOS1_E1UC_5_H_IN_OUT |
PORT116_EMIOS1_E1UC_6_H_IN_OUT |
PORT117_EMIOS1_E1UC_7_H_IN_OUT |
PORT118_EMIOS1_E1UC_8_X_IN_OUT |
PORT119_EMIOS1_E1UC_9_H_IN_OUT |
PORT120_EMIOS1_E1UC_10_H_IN_OUT |
PORT122_DCI_TMS_IN_OUT |
PORT124_DSPI_3_dSCLK_IN_OUT |
PORT126_SPI_0_SCLK_0_IN_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14)
          ),
/* Pads 128 ... 143 : PORT128_EMIOS0_E0UC_28_Y_IN_OUT |
PORT129_EMIOS0_E0UC_29_Y_IN_OUT |
PORT130_EMIOS0_E0UC_30_Y_IN_OUT |
PORT131_EMIOS0_E0UC_31_Y_IN_OUT |
PORT132_EMIOS1_E1UC_28_Y_IN_OUT |
PORT133_EMIOS1_E1UC_29_Y_IN_OUT |
PORT134_EMIOS1_E1UC_30_Y_IN_OUT |
PORT135_EMIOS1_E1UC_31_Y_IN_OUT |
PORT142_SAI2_SAI2_D0_IN_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(14)
          ),
/* Pads 144 ... 159 : PORT148_SPI_1_SCLK_1_IN_OUT |
PORT156_EMIOS1_E1UC_10_H_IN_OUT */
  (uint16)( SHL_PAD_U16(4) |
SHL_PAD_U16(12)
          ),
/* Pads 160 ... 175 : PORT163_EMIOS1_E1UC_0_X_IN_OUT |
PORT165_EMIOS0_E0UC_10_H_IN_OUT |
PORT167_EMIOS0_E0UC_12_H_IN_OUT |
PORT169_EMIOS1_E1UC_29_Y_IN_OUT |
PORT171_SPI_0_SCLK_0_IN_OUT */
  (uint16)( SHL_PAD_U16(3) |
SHL_PAD_U16(5) |
SHL_PAD_U16(7) |
SHL_PAD_U16(9) |
SHL_PAD_U16(11)
          ),
/* Pads 176 ... 191 : PORT177_SAI0_SAI0_D0_IN_OUT */
  (uint16)( SHL_PAD_U16(1)
          ),
/* Pads 192 ... 207 : PORT195_SAI0_SAI0_D1_IN_OUT |
PORT196_SAI0_SAI0_D2_IN_OUT |
PORT197_SAI0_SAI0_D3_IN_OUT |
PORT206_SAI0_SAI0_MCLK_IN_OUT */
  (uint16)( SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(14)
          ),
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 */
  (uint16)0x0000,
/* Pads 240 ... 255 : PORT254_SPI_2_SCLK_2_IN_OUT |
PORT255_EMIOS1_E1UC_21_Y_IN_OUT */
  (uint16)( SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 256 ... 271 : PORT258_DSPI_0_dSCLK_IN_OUT */
  (uint16)( SHL_PAD_U16(2)
          )
}
,
/*  Mode PORT_INOUT2_MODE: */
{
/* Pads   0 ...  15 : PORT8_EMIOS0_E0UC_14_H_IN_OUT |
PORT10_IIC_0_SDA0_IN_OUT |
PORT11_IIC_0_SCL0_IN_OUT |
PORT13_EMIOS0_E0UC_29_Y_IN_OUT |
PORT15_DSPI_0_dSCLK_IN_OUT */
  (uint16)( SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(13) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_EMIOS0_E0UC_30_Y_IN_OUT |
PORT17_EMIOS0_E0UC_5_G_IN_OUT |
PORT18_IIC_0_SDA0_IN_OUT |
PORT19_IIC_0_SCL0_IN_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3)
          ),
/* Pads  32 ...  47 : PORT38_EMIOS1_E1UC_28_Y_IN_OUT |
PORT40_EMIOS0_E0UC_3_G_IN_OUT |
PORT43_EMIOS0_E0UC_1_G_IN_OUT |
PORT46_DSPI_2_dSCLK_IN_OUT */
  (uint16)( SHL_PAD_U16(6) |
SHL_PAD_U16(8) |
SHL_PAD_U16(11) |
SHL_PAD_U16(14)
          ),
/* Pads  48 ...  63 : PORT60_EMIOS0_E0UC_24_X_IN_OUT |
PORT61_EMIOS0_E0UC_25_Y_IN_OUT |
PORT62_EMIOS0_E0UC_26_Y_IN_OUT |
PORT63_EMIOS0_E0UC_27_Y_IN_OUT */
  (uint16)( SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  64 ...  79 : PORT64_IIC_1_SCL1_IN_OUT |
PORT68_DSPI_1_dSCLK_IN_OUT |
PORT72_EMIOS0_E0UC_22_X_IN_OUT |
PORT73_IIC_2_SCL2_IN_OUT |
PORT77_EMIOS1_E1UC_20_Y_IN_OUT |
PORT78_EMIOS1_E1UC_21_Y_IN_OUT |
PORT79_EMIOS1_E1UC_22_X_IN_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(4) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT91_EMIOS1_E1UC_3_H_IN_OUT |
PORT93_EMIOS0_E0UC_22_X_IN_OUT |
PORT94_EMIOS1_E1UC_27_Y_IN_OUT */
  (uint16)( SHL_PAD_U16(11) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14)
          ),
/* Pads  96 ... 111 : PORT96_EMIOS1_E1UC_23_X_IN_OUT |
PORT97_ENET0_MII_RMII_0_TX_CLK_IN_OUT |
PORT100_DSPI_3_dSCLK_IN_OUT |
PORT101_EMIOS0_E0UC_2_G_IN_OUT |
PORT103_EMIOS1_E1UC_30_Y_IN_OUT |
PORT105_DSPI_2_dSCLK_IN_OUT |
PORT106_EMIOS1_E1UC_31_Y_IN_OUT |
PORT109_SPI_0_SCLK_0_IN_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(7) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(13)
          ),
/* Pads 112 ... 127 : PORT114_DSPI_1_dSCLK_IN_OUT |
PORT117_IIC_3_SDA3_IN_OUT |
PORT118_SPI_3_SCLK_3_IN_OUT */
  (uint16)( SHL_PAD_U16(2) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6)
          ),
/* Pads 128 ... 143 : PORT129_IIC_1_SCL1_IN_OUT |
PORT131_IIC_2_SCL2_IN_OUT |
PORT133_SPI_0_SCLK_0_IN_OUT |
PORT139_ENET0_ENET0_TMR1_IN_OUT */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(3) |
SHL_PAD_U16(5) |
SHL_PAD_U16(11)
          ),
/* Pads 144 ... 159 : PORT145_SAI2_SAI2_BCLK_IN_OUT |
PORT148_EMIOS1_E1UC_18_Y_IN_OUT |
PORT149_SAI2_SAI2_D0_IN_OUT |
PORT150_SAI2_SAI2_BCLK_IN_OUT |
PORT152_SAI2_SAI2_SYNC_IN_OUT |
PORT154_EMIOS1_E1UC_16_X_IN_OUT |
PORT155_EMIOS1_E1UC_11_H_IN_OUT |
PORT159_EMIOS1_E1UC_13_H_IN_OUT */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(15)
          ),
/* Pads 160 ... 175 : PORT161_EMIOS0_E0UC_6_G_IN_OUT |
PORT165_EMIOS1_E1UC_4_H_IN_OUT |
PORT167_EMIOS1_E1UC_6_H_IN_OUT |
PORT170_EMIOS1_E1UC_30_Y_IN_OUT |
PORT171_EMIOS1_E1UC_31_Y_IN_OUT |
PORT172_EMIOS0_E0UC_0_X_IN_OUT |
PORT175_EMIOS0_E0UC_3_G_IN_OUT */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(5) |
SHL_PAD_U16(7) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(15)
          ),
/* Pads 176 ... 191 */
  (uint16)0x0000,
/* Pads 192 ... 207 : PORT195_ENET0_ENET0_TMR2_IN_OUT |
PORT206_DCI_TMS_ALT_IN_OUT */
  (uint16)( SHL_PAD_U16(3) |
SHL_PAD_U16(14)
          ),
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 : PORT224_IIC_0_SDA0_IN_OUT |
PORT225_IIC_0_SCL0_IN_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1)
          ),
/* Pads 240 ... 255 : PORT253_EMIOS1_E1UC_23_X_IN_OUT |
PORT254_EMIOS1_E1UC_22_X_IN_OUT */
  (uint16)( SHL_PAD_U16(13) |
SHL_PAD_U16(14)
          ),
/* Pads 256 ... 271 : PORT260_EMIOS1_E1UC_28_Y_IN_OUT */
  (uint16)( SHL_PAD_U16(4)
          )
}
,
/*  Mode PORT_INOUT3_MODE: */
{
/* Pads   0 ...  15 : PORT0_EMIOS0_E0UC_13_H_IN_OUT |
PORT4_EMIOS0_E0UC_24_X_IN_OUT |
PORT12_EMIOS0_E0UC_26_Y_IN_OUT |
PORT13_EMIOS0_E0UC_25_Y_IN_OUT |
PORT14_EMIOS0_E0UC_0_X_IN_OUT |
PORT15_EMIOS0_E0UC_1_G_IN_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(4) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT18_EMIOS0_E0UC_30_Y_IN_OUT |
PORT19_EMIOS0_E0UC_8_X_IN_OUT */
  (uint16)( SHL_PAD_U16(2) |
SHL_PAD_U16(3)
          ),
/* Pads  32 ...  47 : PORT38_EMIOS0_E0UC_17_Y_IN_OUT |
PORT39_EMIOS0_E0UC_18_Y_IN_OUT */
  (uint16)( SHL_PAD_U16(6) |
SHL_PAD_U16(7)
          ),
/* Pads  48 ...  63 : PORT61_ENET0_ENET0_TMR0_IN_OUT */
  (uint16)( SHL_PAD_U16(13)
          ),
/* Pads  64 ...  79 : PORT65_IIC_1_SDA1_IN_OUT |
PORT74_EMIOS1_E1UC_30_Y_IN_OUT |
PORT79_SPI_2_SCLK_2_IN_OUT */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(10) |
SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT89_EMIOS0_E0UC_14_H_IN_OUT |
PORT90_EMIOS1_E1UC_2_H_IN_OUT |
PORT91_EMIOS0_E0UC_20_Y_IN_OUT |
PORT92_EMIOS0_E0UC_16_X_IN_OUT */
  (uint16)( SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12)
          ),
/* Pads  96 ... 111 : PORT105_EMIOS0_E0UC_0_X_IN_OUT */
  (uint16)( SHL_PAD_U16(9)
          ),
/* Pads 112 ... 127 : PORT116_IIC_3_SCL3_IN_OUT |
PORT123_EMIOS1_E1UC_5_H_IN_OUT |
PORT124_EMIOS1_E1UC_25_Y_IN_OUT |
PORT125_EMIOS1_E1UC_26_Y_IN_OUT |
PORT126_EMIOS1_E1UC_27_Y_IN_OUT |
PORT127_EMIOS1_E1UC_17_Y_IN_OUT */
  (uint16)( SHL_PAD_U16(4) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 128 ... 143 : PORT128_IIC_1_SDA1_IN_OUT |
PORT130_IIC_2_SDA2_IN_OUT |
PORT143_SAI2_SAI2_MCLK_IN_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(2) |
SHL_PAD_U16(15)
          ),
/* Pads 144 ... 159 : PORT144_SAI2_SAI2_SYNC_IN_OUT |
PORT151_SAI2_SAI2_MCLK_IN_OUT |
PORT153_EMIOS1_E1UC_17_Y_IN_OUT |
PORT157_EMIOS1_E1UC_15_H_IN_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(7) |
SHL_PAD_U16(9) |
SHL_PAD_U16(13)
          ),
/* Pads 160 ... 175 : PORT161_EMIOS1_E1UC_1_H_IN_OUT |
PORT162_EMIOS1_E1UC_2_H_IN_OUT |
PORT163_EMIOS1_E1UC_3_H_IN_OUT |
PORT164_EMIOS1_E1UC_1_H_IN_OUT |
PORT166_EMIOS0_E0UC_11_H_IN_OUT |
PORT168_EMIOS0_E0UC_13_H_IN_OUT |
PORT173_SPI_1_SCLK_1_IN_OUT */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(6) |
SHL_PAD_U16(8) |
SHL_PAD_U16(13)
          ),
/* Pads 176 ... 191 */
  (uint16)0x0000,
/* Pads 192 ... 207 */
  (uint16)0x0000,
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 */
  (uint16)0x0000,
/* Pads 240 ... 255 : PORT252_EMIOS1_E1UC_24_X_IN_OUT */
  (uint16)( SHL_PAD_U16(12)
          ),
/* Pads 256 ... 271 : PORT261_EMIOS1_E1UC_27_Y_IN_OUT |
PORT262_EMIOS1_E1UC_26_Y_IN_OUT |
PORT263_EMIOS1_E1UC_25_Y_IN_OUT */
  (uint16)( SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7)
          )
}
,
/*  Mode PORT_INOUT4_MODE: */
{
/* Pads   0 ...  15 : PORT14_EMIOS0_E0UC_23_X_IN_OUT |
PORT15_EMIOS0_E0UC_21_Y_IN_OUT */
  (uint16)( SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_EMIOS0_E0UC_4_G_IN_OUT |
PORT26_SAI0_SAI0_SYNC_IN_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(10)
          ),
/* Pads 32 ... 47 */
  (uint16)0x0000,
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads  64 ...  79 : PORT72_IIC_2_SDA2_IN_OUT |
PORT74_IIC_3_SDA3_IN_OUT |
PORT75_IIC_3_SCL3_IN_OUT */
  (uint16)( SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11)
          ),
/* Pads  80 ...  95 : PORT81_SAI0_SAI0_BCLK_IN_OUT |
PORT82_SAI0_SAI0_D3_IN_OUT |
PORT83_SAI0_SAI0_D2_IN_OUT |
PORT84_SAI0_SAI0_D1_IN_OUT |
PORT85_SAI0_SAI0_D0_IN_OUT |
PORT86_SAI1_SAI1_SYNC_IN_OUT |
PORT88_EMIOS0_E0UC_15_H_IN_OUT |
PORT90_EMIOS0_E0UC_19_Y_IN_OUT |
PORT92_FCCU_EOUT1_IN_OUT |
PORT94_ENET0_MII_RMII_0_MDIO_IN_OUT */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14)
          ),
/* Pads  96 ... 111 : PORT102_EMIOS0_E0UC_3_G_IN_OUT */
  (uint16)( SHL_PAD_U16(6)
          ),
/* Pads 112 ... 127 : PORT125_FCCU_EOUT1_IN_OUT |
PORT127_FCCU_EOUT0_IN_OUT */
  (uint16)( SHL_PAD_U16(13) |
SHL_PAD_U16(15)
          ),
/* Pads 128 ... 143 */
  (uint16)0x0000,
/* Pads 144 ... 159 : PORT146_SAI1_SAI1_D0_IN_OUT |
PORT147_SAI1_SAI1_BCLK_IN_OUT */
  (uint16)( SHL_PAD_U16(2) |
SHL_PAD_U16(3)
          ),
/* Pads 160 ... 175 : PORT160_EMIOS1_E1UC_12_H_IN_OUT |
PORT164_EMIOS0_E0UC_9_H_IN_OUT |
PORT166_EMIOS1_E1UC_5_H_IN_OUT |
PORT168_EMIOS1_E1UC_7_H_IN_OUT |
PORT173_EMIOS0_E0UC_1_G_IN_OUT |
PORT174_EMIOS0_E0UC_2_G_IN_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(4) |
SHL_PAD_U16(6) |
SHL_PAD_U16(8) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14)
          ),
/* Pads 176 ... 191 : PORT176_EMIOS0_E0UC_4_G_IN_OUT */
  (uint16)( SHL_PAD_U16(0)
          ),
/* Pads 192 ... 207 */
  (uint16)0x0000,
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 */
  (uint16)0x0000,
/* Pads 240 ... 255 */
  (uint16)0x0000,
/* Pads 256 ... 271 */
  (uint16)0x0000
}
,
/*  Mode PORT_INOUT5_MODE: */
{
/* Pads 0 ... 15 */
  (uint16)0x0000,
/* Pads  16 ...  31 : PORT26_EMIOS0_E0UC_29_Y_IN_OUT */
  (uint16)( SHL_PAD_U16(10)
          ),
/* Pads 32 ... 47 */
  (uint16)0x0000,
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads 64 ... 79 */
  (uint16)0x0000,
/* Pads  80 ...  95 : PORT86_EMIOS0_E0UC_30_Y_IN_OUT |
PORT90_FCCU_EOUT0_IN_OUT */
  (uint16)( SHL_PAD_U16(6) |
SHL_PAD_U16(10)
          ),
/* Pads 96 ... 111 */
  (uint16)0x0000,
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 */
  (uint16)0x0000,
/* Pads 144 ... 159 */
  (uint16)0x0000,
/* Pads 160 ... 175 */
  (uint16)0x0000,
/* Pads 176 ... 191 */
  (uint16)0x0000,
/* Pads 192 ... 207 */
  (uint16)0x0000,
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 */
  (uint16)0x0000,
/* Pads 240 ... 255 */
  (uint16)0x0000,
/* Pads 256 ... 271 */
  (uint16)0x0000
}
,
/*  Mode PORT_INOUT6_MODE: */
{
/* Pads 0 ... 15 */
  (uint16)0x0000,
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads 32 ... 47 */
  (uint16)0x0000,
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads 64 ... 79 */
  (uint16)0x0000,
/* Pads  80 ...  95 : PORT87_SAI1_SAI1_MCLK_IN_OUT */
  (uint16)( SHL_PAD_U16(7)
          ),
/* Pads 96 ... 111 */
  (uint16)0x0000,
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 */
  (uint16)0x0000,
/* Pads 144 ... 159 : PORT158_EMIOS1_E1UC_14_H_IN_OUT */
  (uint16)( SHL_PAD_U16(14)
          ),
/* Pads 160 ... 175 */
  (uint16)0x0000,
/* Pads 176 ... 191 */
  (uint16)0x0000,
/* Pads 192 ... 207 */
  (uint16)0x0000,
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 */
  (uint16)0x0000,
/* Pads 240 ... 255 */
  (uint16)0x0000,
/* Pads 256 ... 271 */
  (uint16)0x0000
}
,
/*  Mode PORT_INOUT7_MODE: */
{
/* Pads 0 ... 15 */
  (uint16)0x0000,
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads 32 ... 47 */
  (uint16)0x0000,
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads 64 ... 79 */
  (uint16)0x0000,
/* Pads  80 ...  95 : PORT80_SAI0_SAI0_MCLK_IN_OUT */
  (uint16)( SHL_PAD_U16(0)
          ),
/* Pads 96 ... 111 */
  (uint16)0x0000,
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 */
  (uint16)0x0000,
/* Pads 144 ... 159 */
  (uint16)0x0000,
/* Pads 160 ... 175 */
  (uint16)0x0000,
/* Pads 176 ... 191 */
  (uint16)0x0000,
/* Pads 192 ... 207 */
  (uint16)0x0000,
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 */
  (uint16)0x0000,
/* Pads 240 ... 255 */
  (uint16)0x0000,
/* Pads 256 ... 271 */
  (uint16)0x0000
}

[!ENDVAR!]




[!VAR "CHECK_4"!]

/*  Mode PORT_GPIO_MODE: */
{
/* Pads   0 ...  15 : PORT0_GPIO |
PORT1_GPIO |
PORT2_GPIO |
PORT3_GPIO |
PORT4_GPIO |
PORT5_GPIO |
PORT6_GPIO |
PORT7_GPIO |
PORT8_GPIO |
PORT9_GPIO |
PORT10_GPIO |
PORT11_GPIO |
PORT12_GPIO |
PORT13_GPIO |
PORT14_GPIO |
PORT15_GPIO */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_GPIO |
PORT17_GPIO |
PORT18_GPIO |
PORT19_GPIO |
PORT26_GPIO |
PORT27_GPIO |
PORT28_GPIO |
PORT29_GPIO |
PORT30_GPIO |
PORT31_GPIO */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  32 ...  47 : PORT32_GPIO |
PORT33_GPIO |
PORT34_GPIO |
PORT35_GPIO |
PORT36_GPIO |
PORT37_GPIO |
PORT38_GPIO |
PORT39_GPIO |
PORT40_GPIO |
PORT41_GPIO |
PORT42_GPIO |
PORT43_GPIO |
PORT44_GPIO |
PORT45_GPIO |
PORT46_GPIO |
PORT47_GPIO */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  48 ...  63 : PORT60_GPIO |
PORT61_GPIO |
PORT62_GPIO |
PORT63_GPIO */
  (uint16)( SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  64 ...  79 : PORT64_GPIO |
PORT65_GPIO |
PORT66_GPIO |
PORT67_GPIO |
PORT68_GPIO |
PORT69_GPIO |
PORT70_GPIO |
PORT71_GPIO |
PORT72_GPIO |
PORT73_GPIO |
PORT74_GPIO |
PORT75_GPIO |
PORT76_GPIO |
PORT77_GPIO |
PORT78_GPIO |
PORT79_GPIO */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT80_GPIO |
PORT81_GPIO |
PORT82_GPIO |
PORT83_GPIO |
PORT84_GPIO |
PORT85_GPIO |
PORT86_GPIO |
PORT87_GPIO |
PORT88_GPIO |
PORT89_GPIO |
PORT90_GPIO |
PORT91_GPIO |
PORT92_GPIO |
PORT93_GPIO |
PORT94_GPIO |
PORT95_GPIO */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT96_GPIO |
PORT97_GPIO |
PORT98_GPIO |
PORT99_GPIO |
PORT100_GPIO |
PORT101_GPIO |
PORT102_GPIO |
PORT103_GPIO |
PORT104_GPIO |
PORT105_GPIO |
PORT106_GPIO |
PORT107_GPIO |
PORT108_GPIO |
PORT109_GPIO |
PORT110_GPIO |
PORT111_GPIO */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 112 ... 127 : PORT112_GPIO |
PORT113_GPIO |
PORT114_GPIO |
PORT115_GPIO |
PORT116_GPIO |
PORT117_GPIO |
PORT118_GPIO |
PORT119_GPIO |
PORT120_GPIO |
PORT121_GPIO |
PORT122_GPIO |
PORT123_GPIO |
PORT124_GPIO |
PORT125_GPIO |
PORT126_GPIO |
PORT127_GPIO */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 128 ... 143 : PORT128_GPIO |
PORT129_GPIO |
PORT130_GPIO |
PORT131_GPIO |
PORT132_GPIO |
PORT133_GPIO |
PORT134_GPIO |
PORT135_GPIO |
PORT136_GPIO |
PORT137_GPIO |
PORT138_GPIO |
PORT139_GPIO |
PORT140_GPIO |
PORT141_GPIO |
PORT142_GPIO |
PORT143_GPIO */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 144 ... 159 : PORT144_GPIO |
PORT145_GPIO |
PORT146_GPIO |
PORT147_GPIO |
PORT148_GPIO |
PORT149_GPIO |
PORT150_GPIO |
PORT151_GPIO |
PORT152_GPIO |
PORT153_GPIO |
PORT154_GPIO |
PORT155_GPIO |
PORT156_GPIO |
PORT157_GPIO |
PORT158_GPIO |
PORT159_GPIO */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 160 ... 175 : PORT160_GPIO |
PORT161_GPIO |
PORT162_GPIO |
PORT163_GPIO |
PORT164_GPIO |
PORT165_GPIO |
PORT166_GPIO |
PORT167_GPIO |
PORT168_GPIO |
PORT169_GPIO |
PORT170_GPIO |
PORT171_GPIO |
PORT172_GPIO |
PORT173_GPIO |
PORT174_GPIO |
PORT175_GPIO */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 176 ... 191 : PORT176_GPIO |
PORT177_GPIO |
PORT178_GPIO |
PORT179_GPIO |
PORT180_GPIO |
PORT181_GPIO |
PORT182_GPIO |
PORT183_GPIO |
PORT184_GPIO |
PORT185_GPIO |
PORT186_GPIO |
PORT187_GPIO |
PORT188_GPIO |
PORT189_GPIO |
PORT190_GPIO |
PORT191_GPIO */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 192 ... 207 : PORT192_GPIO |
PORT193_GPIO |
PORT194_GPIO |
PORT195_GPIO |
PORT196_GPIO |
PORT197_GPIO |
PORT198_GPIO |
PORT199_GPIO |
PORT200_GPIO |
PORT201_GPIO |
PORT202_GPIO |
PORT205_GPIO |
PORT206_GPIO */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14)
          ),
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 : PORT224_GPIO |
PORT225_GPIO */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1)
          ),
/* Pads 240 ... 255 : PORT252_GPIO |
PORT253_GPIO |
PORT254_GPIO |
PORT255_GPIO */
  (uint16)( SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 256 ... 271 : PORT256_GPIO |
PORT257_GPIO |
PORT258_GPIO |
PORT259_GPIO |
PORT260_GPIO |
PORT261_GPIO |
PORT262_GPIO |
PORT263_GPIO */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7)
          )
}
,
/*  Mode PORT_ALT1_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_EMIOS0_E0UC_0_X_OUT |
PORT1_EMIOS0_E0UC_1_G_OUT |
PORT2_EMIOS0_E0UC_2_G_OUT |
PORT3_EMIOS0_E0UC_3_G_OUT |
PORT4_EMIOS0_E0UC_4_G_OUT |
PORT5_EMIOS0_E0UC_5_G_OUT |
PORT6_EMIOS0_E0UC_6_G_OUT |
PORT7_EMIOS0_E0UC_7_G_OUT |
PORT8_EMIOS0_E0UC_8_X_OUT |
PORT9_EMIOS0_E0UC_9_H_OUT |
PORT10_EMIOS0_E0UC_10_H_OUT |
PORT11_EMIOS0_E0UC_11_H_OUT |
PORT12_EMIOS0_E0UC_28_Y_OUT |
PORT13_DSPI_0_dSOUT |
PORT14_DSPI_0_dSCLK_OUT |
PORT15_DSPI_0_dCS0 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_FlexCAN_0_TX |
PORT17_EMIOS0_E0UC_31_Y_OUT |
PORT18_LIN_0_LIN0TX |
PORT19_EMIOS0_E0UC_31_Y_OUT |
PORT26_DSPI_1_dSOUT |
PORT27_EMIOS0_E0UC_3_G_OUT |
PORT28_EMIOS0_E0UC_4_G_OUT |
PORT29_EMIOS0_E0UC_5_G_OUT |
PORT30_EMIOS0_E0UC_6_G_OUT |
PORT31_EMIOS0_E0UC_7_G_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  32 ...  47 : PORT32_DCI_TDI |
PORT33_DCI_TDO |
PORT34_DSPI_1_dSCLK_OUT |
PORT35_DSPI_1_dCS0 |
PORT36_EMIOS1_E1UC_31_Y_OUT |
PORT37_DSPI_1_dSOUT |
PORT38_LIN_1_LIN1TX |
PORT39_EMIOS1_E1UC_29_Y_OUT |
PORT40_LIN_2_LIN2TX |
PORT41_EMIOS0_E0UC_7_G_OUT |
PORT42_FlexCAN_1_TX |
PORT43_ADC_0_ADC0_MA_2 |
PORT44_EMIOS0_E0UC_12_H_OUT |
PORT45_EMIOS0_E0UC_13_H_OUT |
PORT46_EMIOS0_E0UC_14_H_OUT |
PORT47_EMIOS0_E0UC_15_H_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  48 ...  63 : PORT60_DSPI_0_dCS5 |
PORT61_DSPI_1_dCS0 |
PORT62_DSPI_1_dCS1 |
PORT63_DSPI_1_dCS2 */
  (uint16)( SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  64 ...  79 : PORT64_EMIOS0_E0UC_16_X_OUT |
PORT65_EMIOS0_E0UC_17_Y_OUT |
PORT66_EMIOS0_E0UC_18_Y_OUT |
PORT67_EMIOS0_E0UC_19_Y_OUT |
PORT68_EMIOS0_E0UC_20_Y_OUT |
PORT69_EMIOS0_E0UC_21_Y_OUT |
PORT70_EMIOS0_E0UC_22_X_OUT |
PORT71_EMIOS0_E0UC_23_X_OUT |
PORT72_FlexCAN_2_TX |
PORT73_EMIOS0_E0UC_23_X_OUT |
PORT74_LIN_3_LIN3TX |
PORT75_EMIOS0_E0UC_24_X_OUT |
PORT76_EMIOS1_E1UC_19_Y_OUT |
PORT77_DSPI_2_dSOUT |
PORT78_DSPI_2_dSCLK_OUT |
PORT79_DSPI_2_dCS0 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT80_EMIOS0_E0UC_10_H_OUT |
PORT81_EMIOS0_E0UC_11_H_OUT |
PORT82_EMIOS0_E0UC_12_H_OUT |
PORT83_EMIOS0_E0UC_13_H_OUT |
PORT84_EMIOS0_E0UC_14_H_OUT |
PORT85_EMIOS0_E0UC_22_X_OUT |
PORT86_EMIOS0_E0UC_23_X_OUT |
PORT87_SPI_0_SCLK_0_OUT |
PORT88_FlexCAN_3_TX |
PORT89_EMIOS1_E1UC_1_H_OUT |
PORT90_DSPI_0_dCS1 |
PORT91_DSPI_0_dCS2 |
PORT92_EMIOS1_E1UC_25_Y_OUT |
PORT93_EMIOS1_E1UC_26_Y_OUT |
PORT94_FlexCAN_4_TX |
PORT95_EMIOS1_E1UC_4_H_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT96_FlexCAN_5_TX |
PORT97_EMIOS1_E1UC_24_X_OUT |
PORT98_EMIOS1_E1UC_11_H_OUT |
PORT99_EMIOS1_E1UC_12_H_OUT |
PORT100_EMIOS1_E1UC_13_H_OUT |
PORT101_EMIOS1_E1UC_14_H_OUT |
PORT102_EMIOS1_E1UC_15_H_OUT |
PORT103_EMIOS1_E1UC_16_X_OUT |
PORT104_EMIOS1_E1UC_17_Y_OUT |
PORT105_EMIOS1_E1UC_18_Y_OUT |
PORT106_EMIOS0_E0UC_24_X_OUT |
PORT107_EMIOS0_E0UC_25_Y_OUT |
PORT108_EMIOS0_E0UC_26_Y_OUT |
PORT109_EMIOS0_E0UC_27_Y_OUT |
PORT110_EMIOS1_E1UC_0_X_OUT |
PORT111_EMIOS1_E1UC_1_H_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 112 ... 127 : PORT112_EMIOS1_E1UC_2_H_OUT |
PORT113_EMIOS1_E1UC_3_H_OUT |
PORT114_EMIOS1_E1UC_4_H_OUT |
PORT115_EMIOS1_E1UC_5_H_OUT |
PORT116_EMIOS1_E1UC_6_H_OUT |
PORT117_EMIOS1_E1UC_7_H_OUT |
PORT118_EMIOS1_E1UC_8_X_OUT |
PORT119_EMIOS1_E1UC_9_H_OUT |
PORT120_EMIOS1_E1UC_10_H_OUT |
PORT121_DCI_TCK |
PORT122_DCI_TMS_OUT |
PORT123_DSPI_3_dSOUT |
PORT124_DSPI_3_dSCLK_OUT |
PORT125_SPI_0_SOUT_0 |
PORT126_SPI_0_SCLK_0_OUT |
PORT127_SPI_1_SOUT_1 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 128 ... 143 : PORT128_EMIOS0_E0UC_28_Y_OUT |
PORT129_EMIOS0_E0UC_29_Y_OUT |
PORT130_EMIOS0_E0UC_30_Y_OUT |
PORT131_EMIOS0_E0UC_31_Y_OUT |
PORT132_EMIOS1_E1UC_28_Y_OUT |
PORT133_EMIOS1_E1UC_29_Y_OUT |
PORT134_EMIOS1_E1UC_30_Y_OUT |
PORT135_EMIOS1_E1UC_31_Y_OUT |
PORT140_DSPI_3_dCS0 |
PORT141_DSPI_3_dCS1 |
PORT142_SAI2_SAI2_D0_OUT |
PORT143_SPI_0_CS0_0 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 144 ... 159 : PORT144_SPI_0_CS1_0 |
PORT145_SPI_0_SOUT_0 |
PORT146_SPI_1_CS0_1 |
PORT147_SPI_1_CS1_1 |
PORT148_SPI_1_SCLK_1_OUT |
PORT155_FlexCAN_2_TX |
PORT156_EMIOS1_E1UC_10_H_OUT |
PORT157_SPI_3_CS1_3 |
PORT158_FlexCAN_1_TX |
PORT159_SPI_2_CS1_2 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 160 ... 175 : PORT160_FlexCAN_1_TX |
PORT161_SPI_2_CS3_2 |
PORT162_FlexCAN_4_TX |
PORT163_EMIOS1_E1UC_0_X_OUT |
PORT164_FlexCAN_5_TX |
PORT165_EMIOS0_E0UC_10_H_OUT |
PORT166_FlexCAN_2_TX |
PORT167_EMIOS0_E0UC_12_H_OUT |
PORT168_FlexCAN_3_TX |
PORT169_EMIOS1_E1UC_29_Y_OUT |
PORT170_SPI_0_SOUT_0 |
PORT171_SPI_0_SCLK_0_OUT |
PORT172_SPI_0_CS0_0 |
PORT173_SPI_2_CS3_2 |
PORT174_FlexCAN_3_TX |
PORT175_SPI_0_CS2_0 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 176 ... 191 : PORT176_SPI_1_SOUT_1 |
PORT177_SAI0_SAI0_D0_OUT |
PORT178_DCI_MDO_0 |
PORT179_DCI_MDO_1 |
PORT180_DCI_MDO_2 |
PORT181_DCI_MDO_3 |
PORT182_DCI_MDO_4 |
PORT183_DCI_MDO_5 |
PORT184_DCI_EVTI |
PORT185_DCI_MSEO0 |
PORT186_DCI_MCKO |
PORT187_DCI_MSEO1 |
PORT188_DCI_EVTO |
PORT189_DCI_MDO_6 |
PORT190_DCI_MDO_7 |
PORT191_DCI_MDO_8 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 192 ... 207 : PORT192_DCI_MDO_9 |
PORT193_DCI_MDO_10 |
PORT194_DCI_MDO_11 |
PORT195_SAI0_SAI0_D1_OUT |
PORT196_SAI0_SAI0_D2_OUT |
PORT197_SAI0_SAI0_D3_OUT |
PORT199_DCI_MDO_12 |
PORT200_DCI_MDO_13 |
PORT201_DCI_MDO_14 |
PORT202_DCI_MDO_15 |
PORT206_SAI0_SAI0_MCLK_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(14)
          ),
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 */
  (uint16)0x0000,
/* Pads 240 ... 255 : PORT252_SPI_2_CS0_2 |
PORT253_SPI_2_SOUT_2 |
PORT254_SPI_2_SCLK_2_OUT |
PORT255_EMIOS1_E1UC_21_Y_OUT */
  (uint16)( SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 256 ... 271 : PORT256_DSPI_0_dCS1 |
PORT257_DSPI_0_dCS0 |
PORT258_DSPI_0_dSCLK_OUT |
PORT260_DSPI_0_dSOUT |
PORT261_SPI_2_CS3_2 |
PORT262_SPI_2_CS2_2 |
PORT263_SPI_2_CS1_2 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7)
          )
}
,
/*  Mode PORT_ALT2_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_CGM_CLKOUT0 |
PORT3_LIN_5_LIN5TX |
PORT4_DSPI_1_dCS0 |
PORT5_LIN_4_LIN4TX |
PORT6_DSPI_1_dCS1 |
PORT7_LIN_3_LIN3TX |
PORT8_EMIOS0_E0UC_14_H_OUT |
PORT9_DSPI_1_dCS2 |
PORT10_IIC_0_SDA0_OUT |
PORT11_IIC_0_SCL0_OUT |
PORT12_DSPI_1_dCS3 |
PORT13_EMIOS0_E0UC_29_Y_OUT |
PORT14_DSPI_0_dCS0 |
PORT15_DSPI_0_dSCLK_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_EMIOS0_E0UC_30_Y_OUT |
PORT17_EMIOS0_E0UC_5_G_OUT |
PORT18_IIC_0_SDA0_OUT |
PORT19_IIC_0_SCL0_OUT |
PORT26_FlexCAN_3_TX |
PORT27_DSPI_0_dCS0 |
PORT28_DSPI_0_dCS1 |
PORT29_DSPI_0_dCS2 |
PORT30_DSPI_0_dCS3 |
PORT31_DSPI_0_dCS4 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  32 ...  47 : PORT34_FlexCAN_4_TX |
PORT35_ADC_0_ADC0_MA_0 |
PORT36_FlexRay_FR_B_TX_EN |
PORT37_FlexCAN_3_TX |
PORT38_EMIOS1_E1UC_28_Y_OUT |
PORT39_CMP1_CMP1_O |
PORT40_EMIOS0_E0UC_3_G_OUT |
PORT42_FlexCAN_4_TX |
PORT43_EMIOS0_E0UC_1_G_OUT |
PORT44_FlexRay_FR_DBG_0 |
PORT45_DSPI_2_dSOUT |
PORT46_DSPI_2_dSCLK_OUT |
PORT47_DSPI_2_dCS0 */
  (uint16)( SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  48 ...  63 : PORT60_EMIOS0_E0UC_24_X_OUT |
PORT61_EMIOS0_E0UC_25_Y_OUT |
PORT62_EMIOS0_E0UC_26_Y_OUT |
PORT63_EMIOS0_E0UC_27_Y_OUT */
  (uint16)( SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  64 ...  79 : PORT64_IIC_1_SCL1_OUT |
PORT65_FlexCAN_5_TX |
PORT66_FlexRay_FR_A_TX_EN |
PORT67_DSPI_1_dSOUT |
PORT68_DSPI_1_dSCLK_OUT |
PORT69_DSPI_1_dCS0 |
PORT70_DSPI_0_dCS3 |
PORT71_DSPI_0_dCS2 |
PORT72_EMIOS0_E0UC_22_X_OUT |
PORT73_IIC_2_SCL2_OUT |
PORT74_DSPI_1_dCS3 |
PORT75_DSPI_1_dCS4 |
PORT77_EMIOS1_E1UC_20_Y_OUT |
PORT78_EMIOS1_E1UC_21_Y_OUT |
PORT79_EMIOS1_E1UC_22_X_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT80_DSPI_1_dCS3 |
PORT81_DSPI_1_dCS4 |
PORT82_DSPI_2_dCS0 |
PORT83_DSPI_2_dCS1 |
PORT84_DSPI_2_dCS2 |
PORT85_DSPI_2_dCS3 |
PORT86_DSPI_1_dCS1 |
PORT87_DSPI_1_dCS2 |
PORT88_DSPI_0_dCS4 |
PORT89_DSPI_0_dCS5 |
PORT90_LIN_4_LIN4TX |
PORT91_EMIOS1_E1UC_3_H_OUT |
PORT92_LIN_5_LIN5TX |
PORT93_EMIOS0_E0UC_22_X_OUT |
PORT94_EMIOS1_E1UC_27_Y_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14)
          ),
/* Pads  96 ... 111 : PORT96_EMIOS1_E1UC_23_X_OUT |
PORT97_ENET0_MII_RMII_0_TX_CLK_OUT |
PORT98_DSPI_3_dSOUT |
PORT99_DSPI_3_dCS0 |
PORT100_DSPI_3_dSCLK_OUT |
PORT101_EMIOS0_E0UC_2_G_OUT |
PORT102_LIN_6_LIN6TX |
PORT103_EMIOS1_E1UC_30_Y_OUT |
PORT104_LIN_7_LIN7TX |
PORT105_DSPI_2_dSCLK_OUT |
PORT106_EMIOS1_E1UC_31_Y_OUT |
PORT107_SPI_0_CS0_0 |
PORT108_SPI_0_SOUT_0 |
PORT109_SPI_0_SCLK_0_OUT |
PORT110_LIN_8_LIN8TX |
PORT111_SPI_2_SOUT_2 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 112 ... 127 : PORT113_DSPI_1_dSOUT |
PORT114_DSPI_1_dSCLK_OUT |
PORT115_DSPI_1_dCS0 |
PORT116_SPI_3_SOUT_3 |
PORT117_IIC_3_SDA3_OUT |
PORT118_SPI_3_SCLK_3_OUT |
PORT119_DSPI_2_dCS3 |
PORT120_DSPI_2_dCS2 |
PORT123_SPI_0_CS0_0 |
PORT124_SPI_0_CS1_0 |
PORT125_DSPI_3_dCS0 |
PORT126_DSPI_3_dCS1 */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14)
          ),
/* Pads 128 ... 143 : PORT128_LIN_8_LIN8TX |
PORT129_IIC_1_SCL1_OUT |
PORT130_LIN_9_LIN9TX |
PORT131_IIC_2_SCL2_OUT |
PORT132_SPI_0_SOUT_0 |
PORT133_SPI_0_SCLK_0_OUT |
PORT134_SPI_0_CS0_0 |
PORT135_SPI_0_CS1_0 |
PORT139_ENET0_ENET0_TMR1_OUT |
PORT140_DSPI_2_dCS0 |
PORT141_DSPI_2_dCS1 |
PORT143_DSPI_2_dCS2 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(15)
          ),
/* Pads 144 ... 159 : PORT144_DSPI_2_dCS3 |
PORT145_SAI2_SAI2_BCLK_OUT |
PORT146_SPI_2_CS0_2 |
PORT147_SPI_2_CS1_2 |
PORT148_EMIOS1_E1UC_18_Y_OUT |
PORT149_SAI2_SAI2_D0_OUT |
PORT150_SAI2_SAI2_BCLK_OUT |
PORT152_SAI2_SAI2_SYNC_OUT |
PORT153_FlexCAN_4_TX |
PORT154_EMIOS1_E1UC_16_X_OUT |
PORT155_EMIOS1_E1UC_11_H_OUT |
PORT158_FlexCAN_4_TX |
PORT159_EMIOS1_E1UC_13_H_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 160 ... 175 : PORT160_SPI_2_CS2_2 |
PORT161_EMIOS0_E0UC_6_G_OUT |
PORT164_LIN_8_LIN8TX |
PORT165_EMIOS1_E1UC_4_H_OUT |
PORT166_LIN_2_LIN2TX |
PORT167_EMIOS1_E1UC_6_H_OUT |
PORT168_LIN_3_LIN3TX |
PORT170_EMIOS1_E1UC_30_Y_OUT |
PORT171_EMIOS1_E1UC_31_Y_OUT |
PORT172_EMIOS0_E0UC_0_X_OUT |
PORT173_SPI_3_CS2_3 |
PORT174_SPI_3_CS3_3 |
PORT175_EMIOS0_E0UC_3_G_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 176 ... 191 : PORT176_SPI_3_SOUT_3 */
  (uint16)( SHL_PAD_U16(0)
          ),
/* Pads 192 ... 207 : PORT195_ENET0_ENET0_TMR2_OUT |
PORT197_DCI_TCK_ALT |
PORT198_DCI_TDI_ALT |
PORT205_DCI_TDO_ALT |
PORT206_DCI_TMS_ALT_OUT */
  (uint16)( SHL_PAD_U16(3) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14)
          ),
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 : PORT224_IIC_0_SDA0_OUT |
PORT225_IIC_0_SCL0_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1)
          ),
/* Pads 240 ... 255 : PORT252_DSPI_0_dCS4 |
PORT253_EMIOS1_E1UC_23_X_OUT |
PORT254_EMIOS1_E1UC_22_X_OUT */
  (uint16)( SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14)
          ),
/* Pads 256 ... 271 : PORT260_EMIOS1_E1UC_28_Y_OUT |
PORT261_DSPI_0_dCS3 |
PORT262_DSPI_0_dCS2 |
PORT263_DSPI_0_dCS5 */
  (uint16)( SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7)
          )
}
,
/*  Mode PORT_ALT3_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_EMIOS0_E0UC_13_H_OUT |
PORT2_ADC_0_ADC0_MA_2 |
PORT3_DSPI_1_dCS4 |
PORT4_EMIOS0_E0UC_24_X_OUT |
PORT10_LIN_2_LIN2TX |
PORT12_EMIOS0_E0UC_26_Y_OUT |
PORT13_EMIOS0_E0UC_25_Y_OUT |
PORT14_EMIOS0_E0UC_0_X_OUT |
PORT15_EMIOS0_E0UC_1_G_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(10) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_LIN_0_LIN0TX |
PORT18_EMIOS0_E0UC_30_Y_OUT |
PORT19_EMIOS0_E0UC_8_X_OUT |
PORT26_CMP2_CMP2_O |
PORT28_HSM_DO1 |
PORT30_FlexRay_FR_DBG_1 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(10) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14)
          ),
/* Pads  32 ...  47 : PORT38_EMIOS0_E0UC_17_Y_OUT |
PORT39_EMIOS0_E0UC_18_Y_OUT |
PORT41_SSCM_SSCM_DBG_7 |
PORT42_ADC_0_ADC0_MA_1 |
PORT45_FlexRay_FR_DBG_1 */
  (uint16)( SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(13)
          ),
/* Pads  48 ...  63 : PORT60_HSM_DO0 |
PORT61_ENET0_ENET0_TMR0_OUT |
PORT62_FlexRay_FR_DBG_0 |
PORT63_FlexRay_FR_DBG_1 */
  (uint16)( SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  64 ...  79 : PORT65_IIC_1_SDA1_OUT |
PORT68_FlexRay_FR_B_TX |
PORT69_ADC_0_ADC0_MA_2 |
PORT70_ADC_0_ADC0_MA_1 |
PORT71_ADC_0_ADC0_MA_0 |
PORT72_FlexCAN_3_TX |
PORT74_EMIOS1_E1UC_30_Y_OUT |
PORT75_CGM_CLKOUT1 |
PORT79_SPI_2_SCLK_2_OUT */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT81_SPI_0_CS3_0 |
PORT85_SPI_0_CS2_0 |
PORT88_FlexCAN_2_TX |
PORT89_EMIOS0_E0UC_14_H_OUT |
PORT90_EMIOS1_E1UC_2_H_OUT |
PORT91_EMIOS0_E0UC_20_Y_OUT |
PORT92_EMIOS0_E0UC_16_X_OUT |
PORT94_FlexCAN_1_TX */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(5) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14)
          ),
/* Pads  96 ... 111 : PORT96_ENET0_MII_RMII_0_MDC |
PORT98_FlexCAN_7_TX |
PORT100_LIN_10_LIN10TX |
PORT102_CGM_CLKOUT1 |
PORT103_CGM_CLKOUT0 |
PORT104_DSPI_2_dCS0 |
PORT105_EMIOS0_E0UC_0_X_OUT |
PORT107_SPI_2_CS0_2 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(2) |
SHL_PAD_U16(4) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(11)
          ),
/* Pads 112 ... 127 : PORT112_ENET0_MII_RMII_0_TXD_1 |
PORT115_ENET0_MII_0_TX_ER |
PORT116_IIC_3_SCL3_OUT |
PORT118_ADC_0_ADC0_MA_2 |
PORT119_ADC_0_ADC0_MA_1 |
PORT120_ADC_0_ADC0_MA_0 |
PORT123_EMIOS1_E1UC_5_H_OUT |
PORT124_EMIOS1_E1UC_25_Y_OUT |
PORT125_EMIOS1_E1UC_26_Y_OUT |
PORT126_EMIOS1_E1UC_27_Y_OUT |
PORT127_EMIOS1_E1UC_17_Y_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 128 ... 143 : PORT128_IIC_1_SDA1_OUT |
PORT130_IIC_2_SDA2_OUT |
PORT133_SPI_1_CS2_1 |
PORT134_SPI_1_CS0_1 |
PORT135_SPI_1_CS1_1 |
PORT143_SAI2_SAI2_MCLK_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(2) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(15)
          ),
/* Pads 144 ... 159 : PORT144_SAI2_SAI2_SYNC_OUT |
PORT146_SPI_3_CS0_3 |
PORT147_SPI_3_CS1_3 |
PORT151_SAI2_SAI2_MCLK_OUT |
PORT153_EMIOS1_E1UC_17_Y_OUT |
PORT157_EMIOS1_E1UC_15_H_OUT |
PORT158_SPI_3_CS2_3 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(7) |
SHL_PAD_U16(9) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14)
          ),
/* Pads 160 ... 175 : PORT160_FlexCAN_3_TX |
PORT161_EMIOS1_E1UC_1_H_OUT |
PORT162_EMIOS1_E1UC_2_H_OUT |
PORT163_EMIOS1_E1UC_3_H_OUT |
PORT164_EMIOS1_E1UC_1_H_OUT |
PORT166_EMIOS0_E0UC_11_H_OUT |
PORT168_EMIOS0_E0UC_13_H_OUT |
PORT170_LIN_15_LIN15TX |
PORT171_LIN_14_LIN14TX |
PORT173_SPI_1_SCLK_1_OUT |
PORT174_SPI_1_CS0_1 |
PORT175_LIN_13_LIN13TX */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(6) |
SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 176 ... 191 : PORT176_SPI_0_CS3_0 */
  (uint16)( SHL_PAD_U16(0)
          ),
/* Pads 192 ... 207 */
  (uint16)0x0000,
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 : PORT224_LIN_12_LIN12TX */
  (uint16)( SHL_PAD_U16(0)
          ),
/* Pads 240 ... 255 : PORT252_EMIOS1_E1UC_24_X_OUT */
  (uint16)( SHL_PAD_U16(12)
          ),
/* Pads 256 ... 271 : PORT261_EMIOS1_E1UC_27_Y_OUT |
PORT262_EMIOS1_E1UC_26_Y_OUT |
PORT263_EMIOS1_E1UC_25_Y_OUT */
  (uint16)( SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7)
          )
}
,
/*  Mode PORT_ALT4_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT13_FlexCAN_0_TX |
PORT14_EMIOS0_E0UC_23_X_OUT |
PORT15_EMIOS0_E0UC_21_Y_OUT */
  (uint16)( SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_EMIOS0_E0UC_4_G_OUT |
PORT26_SAI0_SAI0_SYNC_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(10)
          ),
/* Pads  32 ...  47 : PORT34_SSCM_SSCM_DBG_0 |
PORT35_SSCM_SSCM_DBG_1 |
PORT37_FlexRay_FR_A_TX |
PORT38_SSCM_SSCM_DBG_4 |
PORT39_SSCM_SSCM_DBG_5 |
PORT40_SSCM_SSCM_DBG_6 |
PORT42_CMP0_CMP0_O |
PORT46_FlexRay_FR_DBG_2 |
PORT47_FlexRay_FR_DBG_3 */
  (uint16)( SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads  64 ...  79 : PORT70_ADC_1_ADC1_MA_1 |
PORT71_ADC_1_ADC1_MA_0 |
PORT72_IIC_2_SDA2_OUT |
PORT74_IIC_3_SDA3_OUT |
PORT75_IIC_3_SCL3_OUT */
  (uint16)( SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11)
          ),
/* Pads  80 ...  95 : PORT80_FlexCAN_6_TX |
PORT81_SAI0_SAI0_BCLK_OUT |
PORT82_SAI0_SAI0_D3_OUT |
PORT83_SAI0_SAI0_D2_OUT |
PORT84_SAI0_SAI0_D1_OUT |
PORT85_SAI0_SAI0_D0_OUT |
PORT86_SAI1_SAI1_SYNC_OUT |
PORT88_EMIOS0_E0UC_15_H_OUT |
PORT90_EMIOS0_E0UC_19_Y_OUT |
PORT92_FCCU_EOUT1_OUT |
PORT94_ENET0_MII_RMII_0_MDIO_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14)
          ),
/* Pads  96 ... 111 : PORT98_LIN_11_LIN11TX |
PORT102_EMIOS0_E0UC_3_G_OUT |
PORT104_FlexCAN_7_TX |
PORT108_ENET0_MII_0_TXD_2 |
PORT109_ENET0_MII_0_TXD_3 */
  (uint16)( SHL_PAD_U16(2) |
SHL_PAD_U16(6) |
SHL_PAD_U16(8) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13)
          ),
/* Pads 112 ... 127 : PORT113_ENET0_MII_RMII_0_TXD_0 |
PORT114_ENET0_MII_RMII_0_TX_EN |
PORT118_ADC_1_ADC1_MA_2 |
PORT119_SPI_3_CS0_3 |
PORT120_ADC_1_ADC1_MA_0 |
PORT125_FCCU_EOUT1_OUT |
PORT127_FCCU_EOUT0_OUT */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(13) |
SHL_PAD_U16(15)
          ),
/* Pads 128 ... 143 : PORT133_SPI_2_CS2_2 |
PORT134_SPI_2_CS0_2 |
PORT135_SPI_2_CS1_2 */
  (uint16)( SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7)
          ),
/* Pads 144 ... 159 : PORT146_SAI1_SAI1_D0_OUT |
PORT147_SAI1_SAI1_BCLK_OUT |
PORT158_FlexCAN_6_TX */
  (uint16)( SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(14)
          ),
/* Pads 160 ... 175 : PORT160_EMIOS1_E1UC_12_H_OUT |
PORT164_EMIOS0_E0UC_9_H_OUT |
PORT166_EMIOS1_E1UC_5_H_OUT |
PORT168_EMIOS1_E1UC_7_H_OUT |
PORT173_EMIOS0_E0UC_1_G_OUT |
PORT174_EMIOS0_E0UC_2_G_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(4) |
SHL_PAD_U16(6) |
SHL_PAD_U16(8) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14)
          ),
/* Pads 176 ... 191 : PORT176_EMIOS0_E0UC_4_G_OUT */
  (uint16)( SHL_PAD_U16(0)
          ),
/* Pads 192 ... 207 */
  (uint16)0x0000,
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 */
  (uint16)0x0000,
/* Pads 240 ... 255 */
  (uint16)0x0000,
/* Pads 256 ... 271 */
  (uint16)0x0000
}
,
/*  Mode PORT_ALT5_FUNC_MODE: */
{
/* Pads 0 ... 15 */
  (uint16)0x0000,
/* Pads  16 ...  31 : PORT26_EMIOS0_E0UC_29_Y_OUT */
  (uint16)( SHL_PAD_U16(10)
          ),
/* Pads  32 ...  47 : PORT36_SSCM_SSCM_DBG_2 |
PORT46_FlexCAN_4_TX */
  (uint16)( SHL_PAD_U16(4) |
SHL_PAD_U16(14)
          ),
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads  64 ...  79 : PORT72_LIN_6_LIN6TX */
  (uint16)( SHL_PAD_U16(8)
          ),
/* Pads  80 ...  95 : PORT86_EMIOS0_E0UC_30_Y_OUT |
PORT90_FCCU_EOUT0_OUT */
  (uint16)( SHL_PAD_U16(6) |
SHL_PAD_U16(10)
          ),
/* Pads 96 ... 111 */
  (uint16)0x0000,
/* Pads 112 ... 127 : PORT119_ADC_1_ADC1_MA_1 */
  (uint16)( SHL_PAD_U16(7)
          ),
/* Pads 128 ... 143 : PORT134_HSM_DO0 |
PORT135_HSM_DO1 */
  (uint16)( SHL_PAD_U16(6) |
SHL_PAD_U16(7)
          ),
/* Pads 144 ... 159 */
  (uint16)0x0000,
/* Pads 160 ... 175 */
  (uint16)0x0000,
/* Pads 176 ... 191 */
  (uint16)0x0000,
/* Pads 192 ... 207 */
  (uint16)0x0000,
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 */
  (uint16)0x0000,
/* Pads 240 ... 255 */
  (uint16)0x0000,
/* Pads 256 ... 271 */
  (uint16)0x0000
}
,
/*  Mode PORT_ALT6_FUNC_MODE: */
{
/* Pads 0 ... 15 */
  (uint16)0x0000,
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads  32 ...  47 : PORT42_LIN_6_LIN6TX */
  (uint16)( SHL_PAD_U16(10)
          ),
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads 64 ... 79 */
  (uint16)0x0000,
/* Pads  80 ...  95 : PORT87_SAI1_SAI1_MCLK_OUT */
  (uint16)( SHL_PAD_U16(7)
          ),
/* Pads 96 ... 111 */
  (uint16)0x0000,
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 */
  (uint16)0x0000,
/* Pads 144 ... 159 : PORT158_EMIOS1_E1UC_14_H_OUT */
  (uint16)( SHL_PAD_U16(14)
          ),
/* Pads 160 ... 175 */
  (uint16)0x0000,
/* Pads 176 ... 191 */
  (uint16)0x0000,
/* Pads 192 ... 207 */
  (uint16)0x0000,
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 */
  (uint16)0x0000,
/* Pads 240 ... 255 */
  (uint16)0x0000,
/* Pads 256 ... 271 */
  (uint16)0x0000
}
,
/*  Mode PORT_ALT7_FUNC_MODE: */
{
/* Pads 0 ... 15 */
  (uint16)0x0000,
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads  32 ...  47 : PORT37_SSCM_SSCM_DBG_3 */
  (uint16)( SHL_PAD_U16(5)
          ),
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads 64 ... 79 */
  (uint16)0x0000,
/* Pads  80 ...  95 : PORT80_SAI0_SAI0_MCLK_OUT */
  (uint16)( SHL_PAD_U16(0)
          ),
/* Pads 96 ... 111 */
  (uint16)0x0000,
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 */
  (uint16)0x0000,
/* Pads 144 ... 159 */
  (uint16)0x0000,
/* Pads 160 ... 175 */
  (uint16)0x0000,
/* Pads 176 ... 191 */
  (uint16)0x0000,
/* Pads 192 ... 207 */
  (uint16)0x0000,
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 */
  (uint16)0x0000,
/* Pads 240 ... 255 */
  (uint16)0x0000,
/* Pads 256 ... 271 */
  (uint16)0x0000
}
,
/*  Mode PORT_ONLY_OUTPUT_MODE: */
{
/* Pads 0 ... 15 */
  (uint16)0x0000,
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads 32 ... 47 */
  (uint16)0x0000,
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads 64 ... 79 */
  (uint16)0x0000,
/* Pads 80 ... 95 */
  (uint16)0x0000,
/* Pads  96 ... 111 : PORT102_PMCDIG_EXTREGC */
  (uint16)( SHL_PAD_U16(6)
          ),
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 */
  (uint16)0x0000,
/* Pads 144 ... 159 */
  (uint16)0x0000,
/* Pads 160 ... 175 */
  (uint16)0x0000,
/* Pads 176 ... 191 */
  (uint16)0x0000,
/* Pads 192 ... 207 */
  (uint16)0x0000,
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 */
  (uint16)0x0000,
/* Pads 240 ... 255 */
  (uint16)0x0000,
/* Pads 256 ... 271 */
  (uint16)0x0000
}
,
/*  Mode PORT_ONLY_INPUT_MODE: */
{
/* Pads   0 ...  15 : PORT0_WKPU_WKPU_19 |
PORT1_WKPU_WKPU_2 |
PORT1_WKPU_NMI_0 |
PORT2_WKPU_WKPU_3 |
PORT4_WKPU_WKPU_9 |
PORT15_WKPU_WKPU_10 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(4) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT17_WKPU_WKPU_4 |
PORT19_WKPU_WKPU_11 |
PORT20_GPI |
PORT21_GPI |
PORT22_GPI |
PORT23_GPI |
PORT24_GPI |
PORT24_WKPU_WKPU_25 |
PORT24_XOSC_OSC32K_XTAL |
PORT25_GPI |
PORT25_WKPU_WKPU_26 |
PORT25_XOSC_OSC32K_EXTAL |
PORT26_WKPU_WKPU_8 */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(8) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(9) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10)
          ),
/* Pads  32 ...  47 : PORT39_WKPU_WKPU_12 |
PORT41_WKPU_WKPU_13 |
PORT43_WKPU_WKPU_5 */
  (uint16)( SHL_PAD_U16(7) |
SHL_PAD_U16(9) |
SHL_PAD_U16(11)
          ),
/* Pads  48 ...  63 : PORT48_GPI |
PORT48_WKPU_WKPU_27 |
PORT49_GPI |
PORT49_WKPU_WKPU_28 |
PORT50_GPI |
PORT51_GPI |
PORT52_GPI |
PORT53_GPI |
PORT54_GPI |
PORT55_GPI |
PORT56_GPI |
PORT57_GPI |
PORT58_GPI |
PORT59_GPI */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11)
          ),
/* Pads  64 ...  79 : PORT64_WKPU_WKPU_6 |
PORT67_WKPU_WKPU_29 |
PORT69_WKPU_WKPU_30 |
PORT73_WKPU_WKPU_7 |
PORT75_WKPU_WKPU_14 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(3) |
SHL_PAD_U16(5) |
SHL_PAD_U16(9) |
SHL_PAD_U16(11)
          ),
/* Pads  80 ...  95 : PORT89_WKPU_WKPU_22 |
PORT90_FCCU_EOUT0_IN |
PORT91_WKPU_WKPU_15 |
PORT92_FCCU_EOUT1_IN |
PORT93_WKPU_WKPU_16 */
  (uint16)( SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13)
          ),
/* Pads  96 ... 111 : PORT99_WKPU_WKPU_17 |
PORT101_WKPU_WKPU_18 |
PORT103_WKPU_WKPU_20 |
PORT105_WKPU_WKPU_21 */
  (uint16)( SHL_PAD_U16(3) |
SHL_PAD_U16(5) |
SHL_PAD_U16(7) |
SHL_PAD_U16(9)
          ),
/* Pads 112 ... 127 : PORT122_DCI_TMS_IN |
PORT125_FCCU_EOUT1_IN |
PORT127_FCCU_EOUT0_IN */
  (uint16)( SHL_PAD_U16(10) |
SHL_PAD_U16(13) |
SHL_PAD_U16(15)
          ),
/* Pads 128 ... 143 : PORT129_WKPU_WKPU_24 |
PORT131_WKPU_WKPU_23 */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(3)
          ),
/* Pads 144 ... 159 : PORT157_WKPU_WKPU_31 */
  (uint16)( SHL_PAD_U16(13)
          ),
/* Pads 160 ... 175 */
  (uint16)0x0000,
/* Pads 176 ... 191 */
  (uint16)0x0000,
/* Pads 192 ... 207 : PORT206_DCI_TMS_ALT_IN */
  (uint16)( SHL_PAD_U16(14)
          ),
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 */
  (uint16)0x0000,
/* Pads 240 ... 255 */
  (uint16)0x0000,
/* Pads 256 ... 271 */
  (uint16)0x0000
}
,
/*  Mode PORT_ANALOG_INPUT_MODE: */
{
/* Pads   0 ...  15 : PORT3_ADC_1_ADC1_S_0 |
PORT4_CMP1_CMP1_13 |
PORT7_ADC_1_ADC1_S_8 |
PORT8_ADC_1_ADC1_S_9 |
PORT9_ADC_1_ADC1_S_10 |
PORT10_ADC_1_ADC1_S_11 |
PORT11_ADC_1_ADC1_S_12 |
PORT12_CMP1_CMP1_15 |
PORT13_CMP1_CMP1_14 |
PORT14_CMP1_CMP1_12 |
PORT15_CMP1_CMP1_10 */
  (uint16)( SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_CMP0_CMP0_2 |
PORT17_CMP0_CMP0_3 |
PORT20_ADC_1_ADC1_P_0 |
PORT21_ADC_1_ADC1_P_1 |
PORT22_ADC_1_ADC1_P_2 |
PORT23_ADC_1_ADC1_P_3 |
PORT24_ADC_0_ADC0_S_0 |
PORT25_ADC_0_ADC0_S_1 |
PORT26_ADC_0_ADC0_S_2 |
PORT27_ADC_0_ADC0_S_3 |
PORT28_ADC_0_ADC0_X_0 |
PORT29_ADC_0_ADC0_X_1 |
PORT30_ADC_0_ADC0_X_2 |
PORT31_ADC_0_ADC0_X_3 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  32 ...  47 : PORT38_CMP0_CMP0_7 */
  (uint16)( SHL_PAD_U16(6)
          ),
/* Pads  48 ...  63 : PORT48_ADC_1_ADC1_P_4 |
PORT49_ADC_1_ADC1_P_5 |
PORT50_ADC_1_ADC1_P_6 |
PORT51_ADC_1_ADC1_P_7 |
PORT52_ADC_1_ADC1_P_8 |
PORT53_ADC_1_ADC1_P_9 |
PORT54_ADC_1_ADC1_P_10 |
PORT55_ADC_1_ADC1_P_11 |
PORT56_ADC_1_ADC1_P_12 |
PORT57_ADC_1_ADC1_P_13 |
PORT58_ADC_1_ADC1_P_14 |
PORT59_ADC_1_ADC1_P_15 |
PORT60_ADC_0_ADC0_S_4 |
PORT61_ADC_0_ADC0_S_5 |
PORT62_ADC_0_ADC0_S_6 |
PORT63_ADC_0_ADC0_S_7 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  64 ...  79 : PORT76_ADC_1_ADC1_S_13 |
PORT77_ADC_1_ADC1_X_3 */
  (uint16)( SHL_PAD_U16(12) |
SHL_PAD_U16(13)
          ),
/* Pads  80 ...  95 : PORT80_ADC_0_ADC0_S_8 |
PORT80_CMP2_CMP2_16 |
PORT81_ADC_0_ADC0_S_9 |
PORT81_CMP2_CMP2_17 |
PORT82_ADC_0_ADC0_S_10 |
PORT82_CMP2_CMP2_18 |
PORT83_ADC_0_ADC0_S_11 |
PORT83_CMP2_CMP2_19 |
PORT84_ADC_0_ADC0_S_12 |
PORT84_CMP2_CMP2_20 |
PORT85_ADC_0_ADC0_S_13 |
PORT85_CMP2_CMP2_21 |
PORT86_ADC_0_ADC0_S_14 |
PORT86_CMP2_CMP2_22 |
PORT87_ADC_0_ADC0_S_15 |
PORT87_CMP2_CMP2_23 |
PORT88_CMP0_CMP0_5 |
PORT89_CMP0_CMP0_4 |
PORT90_CMP1_CMP1_8 |
PORT91_CMP1_CMP1_9 |
PORT92_CMP0_CMP0_6 |
PORT93_CMP1_CMP1_11 |
PORT94_ADC_1_ADC1_X_2 |
PORT95_ADC_1_ADC1_X_1 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT96_ADC_1_ADC1_X_0 |
PORT97_ADC_1_ADC1_S_7 |
PORT102_CMP0_CMP0_1 |
PORT103_CMP0_CMP0_0 |
PORT108_ADC_1_ADC1_S_2 |
PORT109_ADC_1_ADC1_S_1 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13)
          ),
/* Pads 112 ... 127 : PORT112_ADC_1_ADC1_S_3 |
PORT113_ADC_1_ADC1_S_4 |
PORT114_ADC_1_ADC1_S_5 |
PORT115_ADC_1_ADC1_S_6 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3)
          ),
/* Pads 128 ... 143 : PORT136_ADC_0_ADC0_S_16 |
PORT137_ADC_0_ADC0_S_17 |
PORT138_ADC_0_ADC0_S_18 |
PORT139_ADC_0_ADC0_S_19 |
PORT140_ADC_0_ADC0_S_20 |
PORT141_ADC_0_ADC0_S_21 |
PORT142_ADC_0_ADC0_S_22 |
PORT143_ADC_0_ADC0_S_23 */
  (uint16)( SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 144 ... 159 : PORT144_ADC_0_ADC0_S_24 |
PORT145_ADC_0_ADC0_S_25 |
PORT146_ADC_0_ADC0_S_26 |
PORT147_ADC_0_ADC0_S_27 |
PORT149_ADC_0_ADC0_S_28 |
PORT150_ADC_0_ADC0_S_29 |
PORT151_ADC_0_ADC0_S_30 |
PORT152_ADC_0_ADC0_S_31 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8)
          ),
/* Pads 160 ... 175 */
  (uint16)0x0000,
/* Pads 176 ... 191 : PORT177_ADC_0_ADC0_S_47 */
  (uint16)( SHL_PAD_U16(1)
          ),
/* Pads 192 ... 207 : PORT195_ADC_0_ADC0_S_46 |
PORT196_ADC_0_ADC0_S_45 |
PORT197_ADC_0_ADC0_S_44 |
PORT206_ADC_1_ADC1_S_15 */
  (uint16)( SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(14)
          ),
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 */
  (uint16)0x0000,
/* Pads 240 ... 255 */
  (uint16)0x0000,
/* Pads 256 ... 271 */
  (uint16)0x0000
}
,
/*  Mode PORT_INPUT1_MODE: */
{
/* Pads   0 ...  15 : PORT0_EMIOS0_E0UC_0_X_IN |
PORT1_EMIOS0_E0UC_1_G_IN |
PORT2_EMIOS0_E0UC_2_G_IN |
PORT3_EMIOS0_E0UC_3_G_IN |
PORT4_EMIOS0_E0UC_4_G_IN |
PORT5_EMIOS0_E0UC_5_G_IN |
PORT6_EMIOS0_E0UC_6_G_IN |
PORT7_EMIOS0_E0UC_7_G_IN |
PORT8_EMIOS0_E0UC_8_X_IN |
PORT9_EMIOS0_E0UC_9_H_IN |
PORT10_EMIOS0_E0UC_10_H_IN |
PORT11_EMIOS0_E0UC_11_H_IN |
PORT12_EMIOS0_E0UC_28_Y_IN |
PORT13_EMIOS0_E0UC_29_Y_IN |
PORT14_EMIOS0_E0UC_0_X_IN |
PORT15_EMIOS0_E0UC_1_G_IN */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_EMIOS0_E0UC_30_Y_IN |
PORT17_EMIOS0_E0UC_31_Y_IN |
PORT18_EMIOS0_E0UC_30_Y_IN |
PORT19_EMIOS0_E0UC_31_Y_IN |
PORT26_FlexCAN_6_RX |
PORT27_EMIOS0_E0UC_3_G_IN |
PORT28_EMIOS0_E0UC_4_G_IN |
PORT29_EMIOS0_E0UC_5_G_IN |
PORT30_EMIOS0_E0UC_6_G_IN |
PORT31_EMIOS0_E0UC_7_G_IN */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  32 ...  47 : PORT34_SIUL2_EIRQ5 |
PORT35_SIUL2_EIRQ6 |
PORT36_EMIOS1_E1UC_31_Y_IN |
PORT37_SIUL2_EIRQ7 |
PORT38_EMIOS1_E1UC_28_Y_IN |
PORT39_EMIOS1_E1UC_29_Y_IN |
PORT40_EMIOS0_E0UC_3_G_IN |
PORT41_EMIOS0_E0UC_7_G_IN |
PORT43_FlexCAN_1_RX |
PORT44_EMIOS0_E0UC_12_H_IN |
PORT45_EMIOS0_E0UC_13_H_IN |
PORT46_EMIOS0_E0UC_14_H_IN |
PORT47_EMIOS0_E0UC_15_H_IN */
  (uint16)( SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  48 ...  63 : PORT60_EMIOS0_E0UC_24_X_IN |
PORT61_EMIOS0_E0UC_25_Y_IN |
PORT62_EMIOS0_E0UC_26_Y_IN |
PORT63_EMIOS0_E0UC_27_Y_IN */
  (uint16)( SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  64 ...  79 : PORT64_EMIOS0_E0UC_16_X_IN |
PORT65_EMIOS0_E0UC_17_Y_IN |
PORT66_EMIOS0_E0UC_18_Y_IN |
PORT67_EMIOS0_E0UC_19_Y_IN |
PORT68_EMIOS0_E0UC_20_Y_IN |
PORT69_EMIOS0_E0UC_21_Y_IN |
PORT70_EMIOS0_E0UC_22_X_IN |
PORT71_EMIOS0_E0UC_23_X_IN |
PORT72_EMIOS0_E0UC_22_X_IN |
PORT73_EMIOS0_E0UC_23_X_IN |
PORT74_EMIOS1_E1UC_30_Y_IN |
PORT75_EMIOS0_E0UC_24_X_IN |
PORT76_EMIOS1_E1UC_19_Y_IN |
PORT77_EMIOS1_E1UC_20_Y_IN |
PORT78_EMIOS1_E1UC_21_Y_IN |
PORT79_EMIOS1_E1UC_22_X_IN */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT80_EMIOS0_E0UC_10_H_IN |
PORT81_EMIOS0_E0UC_11_H_IN |
PORT82_EMIOS0_E0UC_12_H_IN |
PORT83_EMIOS0_E0UC_13_H_IN |
PORT84_EMIOS0_E0UC_14_H_IN |
PORT85_EMIOS0_E0UC_22_X_IN |
PORT86_EMIOS0_E0UC_23_X_IN |
PORT87_SPI_0_SCLK_0_IN |
PORT88_EMIOS0_E0UC_15_H_IN |
PORT89_EMIOS1_E1UC_1_H_IN |
PORT90_EMIOS1_E1UC_2_H_IN |
PORT91_EMIOS1_E1UC_3_H_IN |
PORT92_EMIOS1_E1UC_25_Y_IN |
PORT93_EMIOS1_E1UC_26_Y_IN |
PORT94_EMIOS1_E1UC_27_Y_IN |
PORT95_EMIOS1_E1UC_4_H_IN */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT96_EMIOS1_E1UC_23_X_IN |
PORT97_EMIOS1_E1UC_24_X_IN |
PORT98_EMIOS1_E1UC_11_H_IN |
PORT99_EMIOS1_E1UC_12_H_IN |
PORT100_EMIOS1_E1UC_13_H_IN |
PORT101_EMIOS1_E1UC_14_H_IN |
PORT102_EMIOS1_E1UC_15_H_IN |
PORT103_EMIOS1_E1UC_16_X_IN |
PORT104_EMIOS1_E1UC_17_Y_IN |
PORT105_EMIOS1_E1UC_18_Y_IN |
PORT106_EMIOS0_E0UC_24_X_IN |
PORT107_EMIOS0_E0UC_25_Y_IN |
PORT108_EMIOS0_E0UC_26_Y_IN |
PORT109_EMIOS0_E0UC_27_Y_IN |
PORT110_EMIOS1_E1UC_0_X_IN |
PORT111_EMIOS1_E1UC_1_H_IN */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 112 ... 127 : PORT112_EMIOS1_E1UC_2_H_IN |
PORT113_EMIOS1_E1UC_3_H_IN |
PORT114_EMIOS1_E1UC_4_H_IN |
PORT115_EMIOS1_E1UC_5_H_IN |
PORT116_EMIOS1_E1UC_6_H_IN |
PORT117_EMIOS1_E1UC_7_H_IN |
PORT118_EMIOS1_E1UC_8_X_IN |
PORT119_EMIOS1_E1UC_9_H_IN |
PORT120_EMIOS1_E1UC_10_H_IN |
PORT123_EMIOS1_E1UC_5_H_IN |
PORT124_EMIOS1_E1UC_25_Y_IN |
PORT125_EMIOS1_E1UC_26_Y_IN |
PORT126_EMIOS1_E1UC_27_Y_IN |
PORT127_EMIOS1_E1UC_17_Y_IN */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 128 ... 143 : PORT128_EMIOS0_E0UC_28_Y_IN |
PORT129_EMIOS0_E0UC_29_Y_IN |
PORT130_EMIOS0_E0UC_30_Y_IN |
PORT131_EMIOS0_E0UC_31_Y_IN |
PORT132_EMIOS1_E1UC_28_Y_IN |
PORT133_EMIOS1_E1UC_29_Y_IN |
PORT134_EMIOS1_E1UC_30_Y_IN |
PORT135_EMIOS1_E1UC_31_Y_IN |
PORT139_DSPI_3_dSIN |
PORT140_DSPI_2_dSS |
PORT142_SPI_0_SIN_0 |
PORT143_SPI_0_SS_0 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 144 ... 159 : PORT144_SAI2_SAI2_SYNC_IN |
PORT145_SPI_1_SIN_1 |
PORT146_SPI_1_SS_1 |
PORT147_SAI1_SAI1_BCLK_IN |
PORT148_EMIOS1_E1UC_18_Y_IN |
PORT149_SAI2_SAI2_D0_IN |
PORT150_SAI2_SAI2_BCLK_IN |
PORT151_SAI2_SAI2_MCLK_IN |
PORT152_SAI2_SAI2_SYNC_IN |
PORT153_EMIOS1_E1UC_17_Y_IN |
PORT154_EMIOS1_E1UC_16_X_IN |
PORT155_EMIOS1_E1UC_11_H_IN |
PORT156_EMIOS1_E1UC_10_H_IN |
PORT157_EMIOS1_E1UC_15_H_IN |
PORT158_EMIOS1_E1UC_14_H_IN |
PORT159_EMIOS1_E1UC_13_H_IN */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 160 ... 175 : PORT160_EMIOS1_E1UC_12_H_IN |
PORT161_EMIOS1_E1UC_1_H_IN |
PORT162_EMIOS1_E1UC_2_H_IN |
PORT163_EMIOS1_E1UC_0_X_IN |
PORT164_EMIOS1_E1UC_1_H_IN |
PORT165_EMIOS1_E1UC_4_H_IN |
PORT166_EMIOS1_E1UC_5_H_IN |
PORT167_EMIOS1_E1UC_6_H_IN |
PORT168_EMIOS1_E1UC_7_H_IN |
PORT169_EMIOS1_E1UC_29_Y_IN |
PORT170_EMIOS1_E1UC_30_Y_IN |
PORT171_EMIOS1_E1UC_31_Y_IN |
PORT172_EMIOS0_E0UC_0_X_IN |
PORT173_EMIOS0_E0UC_1_G_IN |
PORT174_EMIOS0_E0UC_2_G_IN |
PORT175_EMIOS0_E0UC_3_G_IN */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 176 ... 191 : PORT176_EMIOS0_E0UC_4_G_IN |
PORT177_SAI0_SAI0_D0_IN */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1)
          ),
/* Pads 192 ... 207 : PORT195_SAI0_SAI0_D1_IN |
PORT196_SAI0_SAI0_D2_IN |
PORT197_SAI0_SAI0_D3_IN |
PORT206_SAI0_SAI0_MCLK_IN */
  (uint16)( SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(14)
          ),
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 : PORT224_IIC_0_SDA0_IN |
PORT225_LIN_12_LIN12RX */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1)
          ),
/* Pads 240 ... 255 : PORT252_EMIOS1_E1UC_24_X_IN |
PORT253_EMIOS1_E1UC_23_X_IN |
PORT254_EMIOS1_E1UC_22_X_IN |
PORT255_EMIOS1_E1UC_21_Y_IN */
  (uint16)( SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 256 ... 271 : PORT257_DSPI_0_dSS |
PORT258_DSPI_0_dSCLK_IN |
PORT259_DSPI_0_dSIN |
PORT260_EMIOS1_E1UC_28_Y_IN |
PORT261_EMIOS1_E1UC_27_Y_IN |
PORT262_EMIOS1_E1UC_26_Y_IN |
PORT263_EMIOS1_E1UC_25_Y_IN */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7)
          )
}
,
/*  Mode PORT_INPUT2_MODE: */
{
/* Pads   0 ...  15 : PORT0_EMIOS0_E0UC_13_H_IN |
PORT1_FlexCAN_3_RX |
PORT3_SIUL2_EIRQ0 |
PORT4_LIN_5_LIN5RX |
PORT6_SIUL2_EIRQ1 |
PORT7_SIUL2_EIRQ2 |
PORT8_EMIOS0_E0UC_14_H_IN |
PORT9_ENET0_MII_RMII_0_RXD_0 |
PORT10_IIC_0_SDA0_IN |
PORT11_SIUL2_EIRQ16 |
PORT12_SIUL2_EIRQ17 |
PORT13_EMIOS0_E0UC_25_Y_IN |
PORT14_SIUL2_EIRQ4 |
PORT15_FlexCAN_0_RX */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_EMIOS0_E0UC_4_G_IN |
PORT17_FlexCAN_0_RX |
PORT18_IIC_0_SDA0_IN |
PORT19_LIN_0_LIN0RX |
PORT26_SAI0_SAI0_SYNC_IN |
PORT27_DSPI_0_dSS */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11)
          ),
/* Pads  32 ...  47 : PORT34_DSPI_1_dSCLK_IN |
PORT35_FlexCAN_1_RX |
PORT36_SIUL2_EIRQ18 |
PORT38_EMIOS0_E0UC_17_Y_IN |
PORT39_LIN_1_LIN1RX |
PORT41_LIN_2_LIN2RX |
PORT43_FlexCAN_4_RX |
PORT44_SIUL2_EIRQ19 |
PORT46_SIUL2_EIRQ8 |
PORT47_SIUL2_EIRQ20 */
  (uint16)( SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(9) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  48 ...  63 : PORT61_DSPI_1_dSS */
  (uint16)( SHL_PAD_U16(13)
          ),
/* Pads  64 ...  79 : PORT64_FlexCAN_5_RX |
PORT65_IIC_1_SDA1_IN |
PORT66_SIUL2_EIRQ21 |
PORT67_FlexRay_FR_A_RX |
PORT68_SIUL2_EIRQ9 |
PORT69_FlexRay_FR_B_RX |
PORT70_SIUL2_EIRQ22 |
PORT71_SIUL2_EIRQ23 |
PORT72_IIC_2_SDA2_IN |
PORT73_FlexCAN_2_RX |
PORT74_SIUL2_EIRQ10 |
PORT75_LIN_3_LIN3RX |
PORT76_SIUL2_EIRQ11 |
PORT77_ENET0_MII_0_RXD_3 |
PORT78_SIUL2_EIRQ12 |
PORT79_DSPI_2_dSS */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT80_SAI0_SAI0_MCLK_IN |
PORT81_SAI0_SAI0_BCLK_IN |
PORT82_DSPI_2_dSS |
PORT83_SAI0_SAI0_D2_IN |
PORT84_SAI0_SAI0_D1_IN |
PORT85_SAI0_SAI0_D0_IN |
PORT86_SAI1_SAI1_SYNC_IN |
PORT87_SAI1_SAI1_MCLK_IN |
PORT89_FlexCAN_2_RX |
PORT90_EMIOS0_E0UC_19_Y_IN |
PORT91_LIN_4_LIN4RX |
PORT92_EMIOS0_E0UC_16_X_IN |
PORT93_LIN_5_LIN5RX |
PORT94_ENET0_MII_RMII_0_MDIO_IN |
PORT95_SIUL2_EIRQ13 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT97_SIUL2_EIRQ14 |
PORT99_FlexCAN_7_RX |
PORT100_DSPI_3_dSCLK_IN |
PORT101_LIN_10_LIN10RX |
PORT102_EMIOS0_E0UC_3_G_IN |
PORT103_EMIOS1_E1UC_30_Y_IN |
PORT104_SIUL2_EIRQ15 |
PORT105_FlexCAN_7_RX |
PORT106_EMIOS1_E1UC_31_Y_IN |
PORT107_SPI_0_SS_0 |
PORT109_SPI_0_SCLK_0_IN |
PORT110_SPI_2_SIN_2 |
PORT111_LIN_8_LIN8RX */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 112 ... 127 : PORT112_DSPI_1_dSIN |
PORT114_DSPI_1_dSCLK_IN |
PORT115_DSPI_1_dSS |
PORT116_IIC_3_SCL3_IN |
PORT117_IIC_3_SDA3_IN |
PORT118_SPI_3_SCLK_3_IN |
PORT119_SPI_3_SS_3 |
PORT123_SPI_0_SS_0 |
PORT124_DSPI_3_dSCLK_IN |
PORT125_DSPI_3_dSS |
PORT126_SPI_0_SCLK_0_IN */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14)
          ),
/* Pads 128 ... 143 : PORT128_IIC_1_SDA1_IN |
PORT129_LIN_8_LIN8RX |
PORT130_IIC_2_SDA2_IN |
PORT131_LIN_9_LIN9RX |
PORT132_GLITCH_FILTER2_INP |
PORT133_SPI_0_SCLK_0_IN |
PORT134_SPI_0_SS_0 |
PORT135_GLITCH_FILTER3_INP |
PORT139_ENET0_ENET0_TMR1_IN |
PORT140_DSPI_3_dSS |
PORT142_SAI2_SAI2_D0_IN |
PORT143_SAI2_SAI2_MCLK_IN */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 144 ... 159 : PORT145_SAI2_SAI2_BCLK_IN |
PORT146_SPI_2_SS_2 |
PORT148_SPI_1_SCLK_1_IN |
PORT154_FlexCAN_4_RX |
PORT156_FlexCAN_2_RX |
PORT157_FlexCAN_1_RX |
PORT159_FlexCAN_1_RX */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(4) |
SHL_PAD_U16(10) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(15)
          ),
/* Pads 160 ... 175 : PORT161_FlexCAN_4_RX |
PORT163_EMIOS1_E1UC_3_H_IN |
PORT164_EMIOS0_E0UC_9_H_IN |
PORT165_FlexCAN_2_RX |
PORT166_EMIOS0_E0UC_11_H_IN |
PORT167_FlexCAN_3_RX |
PORT168_EMIOS0_E0UC_13_H_IN |
PORT169_LIN_15_LIN15RX |
PORT170_GLITCH_FILTER3_INP |
PORT171_SPI_0_SCLK_0_IN |
PORT172_LIN_14_LIN14RX |
PORT173_FlexCAN_3_RX |
PORT174_SPI_1_SS_1 |
PORT175_SPI_1_SIN_1 */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 176 ... 191 : PORT176_LIN_13_LIN13RX */
  (uint16)( SHL_PAD_U16(0)
          ),
/* Pads 192 ... 207 : PORT195_ENET0_ENET0_TMR2_IN */
  (uint16)( SHL_PAD_U16(3)
          ),
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 : PORT225_IIC_0_SCL0_IN */
  (uint16)( SHL_PAD_U16(1)
          ),
/* Pads 240 ... 255 : PORT252_SPI_2_SS_2 |
PORT254_SPI_2_SCLK_2_IN |
PORT255_SPI_2_SIN_2 */
  (uint16)( SHL_PAD_U16(12) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 256 ... 271 : PORT260_GLITCH_FILTER2_INP */
  (uint16)( SHL_PAD_U16(4)
          )
}
,
/*  Mode PORT_INPUT3_MODE: */
{
/* Pads   0 ...  15 : PORT0_FlexCAN_1_RX |
PORT3_ENET0_MII_0_RX_CLK |
PORT4_DSPI_1_dSS |
PORT6_LIN_4_LIN4RX |
PORT7_ENET0_MII_0_RXD_2 |
PORT8_SIUL2_EIRQ3 |
PORT10_DSPI_1_dSIN |
PORT11_LIN_2_LIN2RX |
PORT12_DSPI_0_dSIN |
PORT13_GLITCH_FILTER0_INP |
PORT14_DSPI_0_dSCLK_IN |
PORT15_DSPI_0_dSCLK_IN */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_GLITCH_FILTER1_INP |
PORT17_LIN_0_LIN0RX |
PORT18_GLITCH_FILTER1_INP |
PORT19_IIC_0_SCL0_IN |
PORT26_EMIOS0_E0UC_29_Y_IN */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(10)
          ),
/* Pads  32 ...  47 : PORT35_FlexCAN_4_RX |
PORT36_FlexCAN_3_RX |
PORT38_GLITCH_FILTER2_INP |
PORT39_EMIOS0_E0UC_18_Y_IN |
PORT43_EMIOS0_E0UC_1_G_IN |
PORT44_DSPI_2_dSIN |
PORT46_DSPI_2_dSCLK_IN |
PORT47_DSPI_2_dSS */
  (uint16)( SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  48 ...  63 : PORT61_ENET0_ENET0_TMR0_IN */
  (uint16)( SHL_PAD_U16(13)
          ),
/* Pads  64 ...  79 : PORT64_LIN_11_LIN11RX |
PORT66_DSPI_1_dSIN |
PORT68_DSPI_1_dSCLK_IN |
PORT69_DSPI_1_dSS |
PORT73_FlexCAN_3_RX |
PORT74_IIC_3_SDA3_IN |
PORT75_IIC_3_SCL3_IN |
PORT76_DSPI_2_dSIN |
PORT78_DSPI_2_dSCLK_IN |
PORT79_SPI_2_SCLK_2_IN */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(2) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT82_SAI0_SAI0_D3_IN |
PORT83_GLITCH_FILTER1_INP |
PORT84_GLITCH_FILTER2_INP |
PORT85_GLITCH_FILTER3_INP |
PORT86_EMIOS0_E0UC_30_Y_IN |
PORT89_FlexCAN_3_RX |
PORT91_EMIOS0_E0UC_20_Y_IN |
PORT93_EMIOS0_E0UC_22_X_IN |
PORT95_FlexCAN_1_RX */
  (uint16)( SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(9) |
SHL_PAD_U16(11) |
SHL_PAD_U16(13) |
SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT97_FlexCAN_5_RX |
PORT99_DSPI_3_dSS |
PORT101_DSPI_3_dSIN |
PORT103_LIN_6_LIN6RX |
PORT104_DSPI_2_dSS |
PORT105_LIN_7_LIN7RX |
PORT106_SPI_0_SIN_0 |
PORT107_SPI_2_SS_2 */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(3) |
SHL_PAD_U16(5) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11)
          ),
/* Pads 112 ... 127 : PORT117_SPI_3_SIN_3 |
PORT126_FCCU_EIN_ERR */
  (uint16)( SHL_PAD_U16(5) |
SHL_PAD_U16(14)
          ),
/* Pads 128 ... 143 : PORT128_GLITCH_FILTER0_INP |
PORT129_IIC_1_SCL1_IN |
PORT130_GLITCH_FILTER1_INP |
PORT131_IIC_2_SCL2_IN |
PORT133_GLITCH_FILTER2_INP |
PORT134_SPI_1_SS_1 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6)
          ),
/* Pads 144 ... 159 : PORT146_SPI_3_SS_3 |
PORT148_FCCU_EIN_ERR |
PORT157_FlexCAN_4_RX |
PORT159_FlexCAN_3_RX */
  (uint16)( SHL_PAD_U16(2) |
SHL_PAD_U16(4) |
SHL_PAD_U16(13) |
SHL_PAD_U16(15)
          ),
/* Pads 160 ... 175 : PORT161_EMIOS0_E0UC_6_G_IN |
PORT163_SIUL2_EIRQ31 |
PORT165_LIN_2_LIN2RX |
PORT167_LIN_3_LIN3RX |
PORT169_SPI_0_SIN_0 |
PORT171_GLITCH_FILTER3_INP |
PORT172_SPI_0_SS_0 |
PORT173_SPI_1_SCLK_1_IN |
PORT175_SPI_3_SIN_3 */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(3) |
SHL_PAD_U16(5) |
SHL_PAD_U16(7) |
SHL_PAD_U16(9) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(15)
          ),
/* Pads 176 ... 191 */
  (uint16)0x0000,
/* Pads 192 ... 207 */
  (uint16)0x0000,
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 */
  (uint16)0x0000,
/* Pads 240 ... 255 */
  (uint16)0x0000,
/* Pads 256 ... 271 */
  (uint16)0x0000
}
,
/*  Mode PORT_INPUT4_MODE: */
{
/* Pads   0 ...  15 : PORT4_EMIOS0_E0UC_24_X_IN |
PORT8_LIN_3_LIN3RX |
PORT10_ENET0_MII_0_COL |
PORT11_IIC_0_SCL0_IN |
PORT12_EMIOS0_E0UC_26_Y_IN |
PORT14_DSPI_0_dSS |
PORT15_DSPI_0_dSS */
  (uint16)( SHL_PAD_U16(4) |
SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT17_EMIOS0_E0UC_5_G_IN |
PORT19_EMIOS0_E0UC_8_X_IN */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(3)
          ),
/* Pads  32 ...  47 : PORT35_DSPI_1_dSS |
PORT36_DSPI_1_dSIN |
PORT39_GLITCH_FILTER2_INP |
PORT47_FlexCAN_4_RX */
  (uint16)( SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(7) |
SHL_PAD_U16(15)
          ),
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads  64 ...  79 : PORT64_IIC_1_SCL1_IN |
PORT73_IIC_2_SCL2_IN |
PORT74_GLITCH_FILTER3_INP |
PORT76_ENET0_MII_0_CRS */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(12)
          ),
/* Pads  80 ...  95 : PORT82_GLITCH_FILTER0_INP |
PORT89_EMIOS0_E0UC_14_H_IN |
PORT95_FlexCAN_4_RX */
  (uint16)( SHL_PAD_U16(2) |
SHL_PAD_U16(9) |
SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT97_ENET0_MII_RMII_0_TX_CLK_IN |
PORT101_EMIOS0_E0UC_2_G_IN |
PORT103_GLITCH_FILTER3_INP |
PORT105_DSPI_2_dSCLK_IN |
PORT106_GLITCH_FILTER3_INP */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(5) |
SHL_PAD_U16(7) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10)
          ),
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 : PORT129_GLITCH_FILTER0_INP |
PORT131_GLITCH_FILTER1_INP |
PORT134_SPI_2_SS_2 */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(3) |
SHL_PAD_U16(6)
          ),
/* Pads 144 ... 159 : PORT146_SAI1_SAI1_D0_IN |
PORT157_FlexCAN_6_RX */
  (uint16)( SHL_PAD_U16(2) |
SHL_PAD_U16(13)
          ),
/* Pads 160 ... 175 : PORT163_FlexCAN_5_RX |
PORT165_EMIOS0_E0UC_10_H_IN |
PORT167_EMIOS0_E0UC_12_H_IN |
PORT169_GLITCH_FILTER2_INP */
  (uint16)( SHL_PAD_U16(3) |
SHL_PAD_U16(5) |
SHL_PAD_U16(7) |
SHL_PAD_U16(9)
          ),
/* Pads 176 ... 191 */
  (uint16)0x0000,
/* Pads 192 ... 207 */
  (uint16)0x0000,
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 */
  (uint16)0x0000,
/* Pads 240 ... 255 */
  (uint16)0x0000,
/* Pads 256 ... 271 */
  (uint16)0x0000
}
,
/*  Mode PORT_INPUT5_MODE: */
{
/* Pads   0 ...  15 : PORT8_ENET0_MII_RMII_0_RXD_1 |
PORT11_ENET0_MII_RMII_0_RX_ER |
PORT12_GLITCH_FILTER0_INP |
PORT14_EMIOS0_E0UC_23_X_IN |
PORT15_EMIOS0_E0UC_21_Y_IN */
  (uint16)( SHL_PAD_U16(8) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT17_GLITCH_FILTER1_INP |
PORT19_GLITCH_FILTER1_INP */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(3)
          ),
/* Pads  32 ...  47 : PORT36_GLITCH_FILTER3_INP */
  (uint16)( SHL_PAD_U16(4)
          ),
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads 64 ... 79 */
  (uint16)0x0000,
/* Pads  80 ...  95 : PORT95_ENET0_MII_RMII_0_RX_DV */
  (uint16)( SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT105_EMIOS0_E0UC_0_X_IN */
  (uint16)( SHL_PAD_U16(9)
          ),
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 : PORT134_GLITCH_FILTER3_INP */
  (uint16)( SHL_PAD_U16(6)
          ),
/* Pads 144 ... 159 */
  (uint16)0x0000,
/* Pads 160 ... 175 : PORT163_LIN_8_LIN8RX */
  (uint16)( SHL_PAD_U16(3)
          ),
/* Pads 176 ... 191 */
  (uint16)0x0000,
/* Pads 192 ... 207 */
  (uint16)0x0000,
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 */
  (uint16)0x0000,
/* Pads 240 ... 255 */
  (uint16)0x0000,
/* Pads 256 ... 271 */
  (uint16)0x0000
}
,
/*  Mode PORT_INPUT6_MODE: */
{
/* Pads 0 ... 15 */
  (uint16)0x0000,
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads 32 ... 47 */
  (uint16)0x0000,
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads 64 ... 79 */
  (uint16)0x0000,
/* Pads 80 ... 95 */
  (uint16)0x0000,
/* Pads 96 ... 111 */
  (uint16)0x0000,
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 */
  (uint16)0x0000,
/* Pads 144 ... 159 */
  (uint16)0x0000,
/* Pads 160 ... 175 */
  (uint16)0x0000,
/* Pads 176 ... 191 */
  (uint16)0x0000,
/* Pads 192 ... 207 */
  (uint16)0x0000,
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 */
  (uint16)0x0000,
/* Pads 240 ... 255 */
  (uint16)0x0000,
/* Pads 256 ... 271 */
  (uint16)0x0000
}
,
/*  Mode PORT_INOUT1_MODE: */
{
/* Pads   0 ...  15 : PORT0_EMIOS0_E0UC_0_X_IN_OUT |
PORT1_EMIOS0_E0UC_1_G_IN_OUT |
PORT2_EMIOS0_E0UC_2_G_IN_OUT |
PORT3_EMIOS0_E0UC_3_G_IN_OUT |
PORT4_EMIOS0_E0UC_4_G_IN_OUT |
PORT5_EMIOS0_E0UC_5_G_IN_OUT |
PORT6_EMIOS0_E0UC_6_G_IN_OUT |
PORT7_EMIOS0_E0UC_7_G_IN_OUT |
PORT8_EMIOS0_E0UC_8_X_IN_OUT |
PORT9_EMIOS0_E0UC_9_H_IN_OUT |
PORT10_EMIOS0_E0UC_10_H_IN_OUT |
PORT11_EMIOS0_E0UC_11_H_IN_OUT |
PORT12_EMIOS0_E0UC_28_Y_IN_OUT |
PORT14_DSPI_0_dSCLK_IN_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14)
          ),
/* Pads  16 ...  31 : PORT17_EMIOS0_E0UC_31_Y_IN_OUT |
PORT19_EMIOS0_E0UC_31_Y_IN_OUT |
PORT27_EMIOS0_E0UC_3_G_IN_OUT |
PORT28_EMIOS0_E0UC_4_G_IN_OUT |
PORT29_EMIOS0_E0UC_5_G_IN_OUT |
PORT30_EMIOS0_E0UC_6_G_IN_OUT |
PORT31_EMIOS0_E0UC_7_G_IN_OUT */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(3) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  32 ...  47 : PORT34_DSPI_1_dSCLK_IN_OUT |
PORT36_EMIOS1_E1UC_31_Y_IN_OUT |
PORT39_EMIOS1_E1UC_29_Y_IN_OUT |
PORT41_EMIOS0_E0UC_7_G_IN_OUT |
PORT44_EMIOS0_E0UC_12_H_IN_OUT |
PORT45_EMIOS0_E0UC_13_H_IN_OUT |
PORT46_EMIOS0_E0UC_14_H_IN_OUT |
PORT47_EMIOS0_E0UC_15_H_IN_OUT */
  (uint16)( SHL_PAD_U16(2) |
SHL_PAD_U16(4) |
SHL_PAD_U16(7) |
SHL_PAD_U16(9) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads  64 ...  79 : PORT64_EMIOS0_E0UC_16_X_IN_OUT |
PORT65_EMIOS0_E0UC_17_Y_IN_OUT |
PORT66_EMIOS0_E0UC_18_Y_IN_OUT |
PORT67_EMIOS0_E0UC_19_Y_IN_OUT |
PORT68_EMIOS0_E0UC_20_Y_IN_OUT |
PORT69_EMIOS0_E0UC_21_Y_IN_OUT |
PORT70_EMIOS0_E0UC_22_X_IN_OUT |
PORT71_EMIOS0_E0UC_23_X_IN_OUT |
PORT73_EMIOS0_E0UC_23_X_IN_OUT |
PORT75_EMIOS0_E0UC_24_X_IN_OUT |
PORT76_EMIOS1_E1UC_19_Y_IN_OUT |
PORT78_DSPI_2_dSCLK_IN_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(9) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14)
          ),
/* Pads  80 ...  95 : PORT80_EMIOS0_E0UC_10_H_IN_OUT |
PORT81_EMIOS0_E0UC_11_H_IN_OUT |
PORT82_EMIOS0_E0UC_12_H_IN_OUT |
PORT83_EMIOS0_E0UC_13_H_IN_OUT |
PORT84_EMIOS0_E0UC_14_H_IN_OUT |
PORT85_EMIOS0_E0UC_22_X_IN_OUT |
PORT86_EMIOS0_E0UC_23_X_IN_OUT |
PORT87_SPI_0_SCLK_0_IN_OUT |
PORT89_EMIOS1_E1UC_1_H_IN_OUT |
PORT92_EMIOS1_E1UC_25_Y_IN_OUT |
PORT93_EMIOS1_E1UC_26_Y_IN_OUT |
PORT95_EMIOS1_E1UC_4_H_IN_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(9) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(15)
          ),
/* Pads  96 ... 111 : PORT97_EMIOS1_E1UC_24_X_IN_OUT |
PORT98_EMIOS1_E1UC_11_H_IN_OUT |
PORT99_EMIOS1_E1UC_12_H_IN_OUT |
PORT100_EMIOS1_E1UC_13_H_IN_OUT |
PORT101_EMIOS1_E1UC_14_H_IN_OUT |
PORT102_EMIOS1_E1UC_15_H_IN_OUT |
PORT103_EMIOS1_E1UC_16_X_IN_OUT |
PORT104_EMIOS1_E1UC_17_Y_IN_OUT |
PORT105_EMIOS1_E1UC_18_Y_IN_OUT |
PORT106_EMIOS0_E0UC_24_X_IN_OUT |
PORT107_EMIOS0_E0UC_25_Y_IN_OUT |
PORT108_EMIOS0_E0UC_26_Y_IN_OUT |
PORT109_EMIOS0_E0UC_27_Y_IN_OUT |
PORT110_EMIOS1_E1UC_0_X_IN_OUT |
PORT111_EMIOS1_E1UC_1_H_IN_OUT */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 112 ... 127 : PORT112_EMIOS1_E1UC_2_H_IN_OUT |
PORT113_EMIOS1_E1UC_3_H_IN_OUT |
PORT114_EMIOS1_E1UC_4_H_IN_OUT |
PORT115_EMIOS1_E1UC_5_H_IN_OUT |
PORT116_EMIOS1_E1UC_6_H_IN_OUT |
PORT117_EMIOS1_E1UC_7_H_IN_OUT |
PORT118_EMIOS1_E1UC_8_X_IN_OUT |
PORT119_EMIOS1_E1UC_9_H_IN_OUT |
PORT120_EMIOS1_E1UC_10_H_IN_OUT |
PORT122_DCI_TMS_IN_OUT |
PORT124_DSPI_3_dSCLK_IN_OUT |
PORT126_SPI_0_SCLK_0_IN_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14)
          ),
/* Pads 128 ... 143 : PORT128_EMIOS0_E0UC_28_Y_IN_OUT |
PORT129_EMIOS0_E0UC_29_Y_IN_OUT |
PORT130_EMIOS0_E0UC_30_Y_IN_OUT |
PORT131_EMIOS0_E0UC_31_Y_IN_OUT |
PORT132_EMIOS1_E1UC_28_Y_IN_OUT |
PORT133_EMIOS1_E1UC_29_Y_IN_OUT |
PORT134_EMIOS1_E1UC_30_Y_IN_OUT |
PORT135_EMIOS1_E1UC_31_Y_IN_OUT |
PORT142_SAI2_SAI2_D0_IN_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(14)
          ),
/* Pads 144 ... 159 : PORT148_SPI_1_SCLK_1_IN_OUT |
PORT156_EMIOS1_E1UC_10_H_IN_OUT */
  (uint16)( SHL_PAD_U16(4) |
SHL_PAD_U16(12)
          ),
/* Pads 160 ... 175 : PORT163_EMIOS1_E1UC_0_X_IN_OUT |
PORT165_EMIOS0_E0UC_10_H_IN_OUT |
PORT167_EMIOS0_E0UC_12_H_IN_OUT |
PORT169_EMIOS1_E1UC_29_Y_IN_OUT |
PORT171_SPI_0_SCLK_0_IN_OUT */
  (uint16)( SHL_PAD_U16(3) |
SHL_PAD_U16(5) |
SHL_PAD_U16(7) |
SHL_PAD_U16(9) |
SHL_PAD_U16(11)
          ),
/* Pads 176 ... 191 : PORT177_SAI0_SAI0_D0_IN_OUT */
  (uint16)( SHL_PAD_U16(1)
          ),
/* Pads 192 ... 207 : PORT195_SAI0_SAI0_D1_IN_OUT |
PORT196_SAI0_SAI0_D2_IN_OUT |
PORT197_SAI0_SAI0_D3_IN_OUT |
PORT206_SAI0_SAI0_MCLK_IN_OUT */
  (uint16)( SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(14)
          ),
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 */
  (uint16)0x0000,
/* Pads 240 ... 255 : PORT254_SPI_2_SCLK_2_IN_OUT |
PORT255_EMIOS1_E1UC_21_Y_IN_OUT */
  (uint16)( SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 256 ... 271 : PORT258_DSPI_0_dSCLK_IN_OUT */
  (uint16)( SHL_PAD_U16(2)
          )
}
,
/*  Mode PORT_INOUT2_MODE: */
{
/* Pads   0 ...  15 : PORT8_EMIOS0_E0UC_14_H_IN_OUT |
PORT10_IIC_0_SDA0_IN_OUT |
PORT11_IIC_0_SCL0_IN_OUT |
PORT13_EMIOS0_E0UC_29_Y_IN_OUT |
PORT15_DSPI_0_dSCLK_IN_OUT */
  (uint16)( SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(13) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_EMIOS0_E0UC_30_Y_IN_OUT |
PORT17_EMIOS0_E0UC_5_G_IN_OUT |
PORT18_IIC_0_SDA0_IN_OUT |
PORT19_IIC_0_SCL0_IN_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3)
          ),
/* Pads  32 ...  47 : PORT38_EMIOS1_E1UC_28_Y_IN_OUT |
PORT40_EMIOS0_E0UC_3_G_IN_OUT |
PORT43_EMIOS0_E0UC_1_G_IN_OUT |
PORT46_DSPI_2_dSCLK_IN_OUT */
  (uint16)( SHL_PAD_U16(6) |
SHL_PAD_U16(8) |
SHL_PAD_U16(11) |
SHL_PAD_U16(14)
          ),
/* Pads  48 ...  63 : PORT60_EMIOS0_E0UC_24_X_IN_OUT |
PORT61_EMIOS0_E0UC_25_Y_IN_OUT |
PORT62_EMIOS0_E0UC_26_Y_IN_OUT |
PORT63_EMIOS0_E0UC_27_Y_IN_OUT */
  (uint16)( SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  64 ...  79 : PORT64_IIC_1_SCL1_IN_OUT |
PORT68_DSPI_1_dSCLK_IN_OUT |
PORT72_EMIOS0_E0UC_22_X_IN_OUT |
PORT73_IIC_2_SCL2_IN_OUT |
PORT77_EMIOS1_E1UC_20_Y_IN_OUT |
PORT78_EMIOS1_E1UC_21_Y_IN_OUT |
PORT79_EMIOS1_E1UC_22_X_IN_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(4) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT91_EMIOS1_E1UC_3_H_IN_OUT |
PORT93_EMIOS0_E0UC_22_X_IN_OUT |
PORT94_EMIOS1_E1UC_27_Y_IN_OUT */
  (uint16)( SHL_PAD_U16(11) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14)
          ),
/* Pads  96 ... 111 : PORT96_EMIOS1_E1UC_23_X_IN_OUT |
PORT97_ENET0_MII_RMII_0_TX_CLK_IN_OUT |
PORT100_DSPI_3_dSCLK_IN_OUT |
PORT101_EMIOS0_E0UC_2_G_IN_OUT |
PORT103_EMIOS1_E1UC_30_Y_IN_OUT |
PORT105_DSPI_2_dSCLK_IN_OUT |
PORT106_EMIOS1_E1UC_31_Y_IN_OUT |
PORT109_SPI_0_SCLK_0_IN_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(7) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(13)
          ),
/* Pads 112 ... 127 : PORT114_DSPI_1_dSCLK_IN_OUT |
PORT117_IIC_3_SDA3_IN_OUT |
PORT118_SPI_3_SCLK_3_IN_OUT */
  (uint16)( SHL_PAD_U16(2) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6)
          ),
/* Pads 128 ... 143 : PORT129_IIC_1_SCL1_IN_OUT |
PORT131_IIC_2_SCL2_IN_OUT |
PORT133_SPI_0_SCLK_0_IN_OUT |
PORT139_ENET0_ENET0_TMR1_IN_OUT */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(3) |
SHL_PAD_U16(5) |
SHL_PAD_U16(11)
          ),
/* Pads 144 ... 159 : PORT145_SAI2_SAI2_BCLK_IN_OUT |
PORT148_EMIOS1_E1UC_18_Y_IN_OUT |
PORT149_SAI2_SAI2_D0_IN_OUT |
PORT150_SAI2_SAI2_BCLK_IN_OUT |
PORT152_SAI2_SAI2_SYNC_IN_OUT |
PORT154_EMIOS1_E1UC_16_X_IN_OUT |
PORT155_EMIOS1_E1UC_11_H_IN_OUT |
PORT159_EMIOS1_E1UC_13_H_IN_OUT */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(15)
          ),
/* Pads 160 ... 175 : PORT161_EMIOS0_E0UC_6_G_IN_OUT |
PORT165_EMIOS1_E1UC_4_H_IN_OUT |
PORT167_EMIOS1_E1UC_6_H_IN_OUT |
PORT170_EMIOS1_E1UC_30_Y_IN_OUT |
PORT171_EMIOS1_E1UC_31_Y_IN_OUT |
PORT172_EMIOS0_E0UC_0_X_IN_OUT |
PORT175_EMIOS0_E0UC_3_G_IN_OUT */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(5) |
SHL_PAD_U16(7) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(15)
          ),
/* Pads 176 ... 191 */
  (uint16)0x0000,
/* Pads 192 ... 207 : PORT195_ENET0_ENET0_TMR2_IN_OUT |
PORT206_DCI_TMS_ALT_IN_OUT */
  (uint16)( SHL_PAD_U16(3) |
SHL_PAD_U16(14)
          ),
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 : PORT224_IIC_0_SDA0_IN_OUT |
PORT225_IIC_0_SCL0_IN_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1)
          ),
/* Pads 240 ... 255 : PORT253_EMIOS1_E1UC_23_X_IN_OUT |
PORT254_EMIOS1_E1UC_22_X_IN_OUT */
  (uint16)( SHL_PAD_U16(13) |
SHL_PAD_U16(14)
          ),
/* Pads 256 ... 271 : PORT260_EMIOS1_E1UC_28_Y_IN_OUT */
  (uint16)( SHL_PAD_U16(4)
          )
}
,
/*  Mode PORT_INOUT3_MODE: */
{
/* Pads   0 ...  15 : PORT0_EMIOS0_E0UC_13_H_IN_OUT |
PORT4_EMIOS0_E0UC_24_X_IN_OUT |
PORT12_EMIOS0_E0UC_26_Y_IN_OUT |
PORT13_EMIOS0_E0UC_25_Y_IN_OUT |
PORT14_EMIOS0_E0UC_0_X_IN_OUT |
PORT15_EMIOS0_E0UC_1_G_IN_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(4) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT18_EMIOS0_E0UC_30_Y_IN_OUT |
PORT19_EMIOS0_E0UC_8_X_IN_OUT */
  (uint16)( SHL_PAD_U16(2) |
SHL_PAD_U16(3)
          ),
/* Pads  32 ...  47 : PORT38_EMIOS0_E0UC_17_Y_IN_OUT |
PORT39_EMIOS0_E0UC_18_Y_IN_OUT */
  (uint16)( SHL_PAD_U16(6) |
SHL_PAD_U16(7)
          ),
/* Pads  48 ...  63 : PORT61_ENET0_ENET0_TMR0_IN_OUT */
  (uint16)( SHL_PAD_U16(13)
          ),
/* Pads  64 ...  79 : PORT65_IIC_1_SDA1_IN_OUT |
PORT74_EMIOS1_E1UC_30_Y_IN_OUT |
PORT79_SPI_2_SCLK_2_IN_OUT */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(10) |
SHL_PAD_U16(15)
          ),
/* Pads  80 ...  95 : PORT89_EMIOS0_E0UC_14_H_IN_OUT |
PORT90_EMIOS1_E1UC_2_H_IN_OUT |
PORT91_EMIOS0_E0UC_20_Y_IN_OUT |
PORT92_EMIOS0_E0UC_16_X_IN_OUT */
  (uint16)( SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12)
          ),
/* Pads  96 ... 111 : PORT105_EMIOS0_E0UC_0_X_IN_OUT */
  (uint16)( SHL_PAD_U16(9)
          ),
/* Pads 112 ... 127 : PORT116_IIC_3_SCL3_IN_OUT |
PORT123_EMIOS1_E1UC_5_H_IN_OUT |
PORT124_EMIOS1_E1UC_25_Y_IN_OUT |
PORT125_EMIOS1_E1UC_26_Y_IN_OUT |
PORT126_EMIOS1_E1UC_27_Y_IN_OUT |
PORT127_EMIOS1_E1UC_17_Y_IN_OUT */
  (uint16)( SHL_PAD_U16(4) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads 128 ... 143 : PORT128_IIC_1_SDA1_IN_OUT |
PORT130_IIC_2_SDA2_IN_OUT |
PORT143_SAI2_SAI2_MCLK_IN_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(2) |
SHL_PAD_U16(15)
          ),
/* Pads 144 ... 159 : PORT144_SAI2_SAI2_SYNC_IN_OUT |
PORT151_SAI2_SAI2_MCLK_IN_OUT |
PORT153_EMIOS1_E1UC_17_Y_IN_OUT |
PORT157_EMIOS1_E1UC_15_H_IN_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(7) |
SHL_PAD_U16(9) |
SHL_PAD_U16(13)
          ),
/* Pads 160 ... 175 : PORT161_EMIOS1_E1UC_1_H_IN_OUT |
PORT162_EMIOS1_E1UC_2_H_IN_OUT |
PORT163_EMIOS1_E1UC_3_H_IN_OUT |
PORT164_EMIOS1_E1UC_1_H_IN_OUT |
PORT166_EMIOS0_E0UC_11_H_IN_OUT |
PORT168_EMIOS0_E0UC_13_H_IN_OUT |
PORT173_SPI_1_SCLK_1_IN_OUT */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(6) |
SHL_PAD_U16(8) |
SHL_PAD_U16(13)
          ),
/* Pads 176 ... 191 */
  (uint16)0x0000,
/* Pads 192 ... 207 */
  (uint16)0x0000,
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 */
  (uint16)0x0000,
/* Pads 240 ... 255 : PORT252_EMIOS1_E1UC_24_X_IN_OUT */
  (uint16)( SHL_PAD_U16(12)
          ),
/* Pads 256 ... 271 : PORT261_EMIOS1_E1UC_27_Y_IN_OUT |
PORT262_EMIOS1_E1UC_26_Y_IN_OUT |
PORT263_EMIOS1_E1UC_25_Y_IN_OUT */
  (uint16)( SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7)
          )
}
,
/*  Mode PORT_INOUT4_MODE: */
{
/* Pads   0 ...  15 : PORT14_EMIOS0_E0UC_23_X_IN_OUT |
PORT15_EMIOS0_E0UC_21_Y_IN_OUT */
  (uint16)( SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          ),
/* Pads  16 ...  31 : PORT16_EMIOS0_E0UC_4_G_IN_OUT |
PORT26_SAI0_SAI0_SYNC_IN_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(10)
          ),
/* Pads 32 ... 47 */
  (uint16)0x0000,
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads  64 ...  79 : PORT72_IIC_2_SDA2_IN_OUT |
PORT74_IIC_3_SDA3_IN_OUT |
PORT75_IIC_3_SCL3_IN_OUT */
  (uint16)( SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11)
          ),
/* Pads  80 ...  95 : PORT81_SAI0_SAI0_BCLK_IN_OUT |
PORT82_SAI0_SAI0_D3_IN_OUT |
PORT83_SAI0_SAI0_D2_IN_OUT |
PORT84_SAI0_SAI0_D1_IN_OUT |
PORT85_SAI0_SAI0_D0_IN_OUT |
PORT86_SAI1_SAI1_SYNC_IN_OUT |
PORT88_EMIOS0_E0UC_15_H_IN_OUT |
PORT90_EMIOS0_E0UC_19_Y_IN_OUT |
PORT92_FCCU_EOUT1_IN_OUT |
PORT94_ENET0_MII_RMII_0_MDIO_IN_OUT */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14)
          ),
/* Pads  96 ... 111 : PORT102_EMIOS0_E0UC_3_G_IN_OUT */
  (uint16)( SHL_PAD_U16(6)
          ),
/* Pads 112 ... 127 : PORT125_FCCU_EOUT1_IN_OUT |
PORT127_FCCU_EOUT0_IN_OUT */
  (uint16)( SHL_PAD_U16(13) |
SHL_PAD_U16(15)
          ),
/* Pads 128 ... 143 */
  (uint16)0x0000,
/* Pads 144 ... 159 : PORT146_SAI1_SAI1_D0_IN_OUT |
PORT147_SAI1_SAI1_BCLK_IN_OUT */
  (uint16)( SHL_PAD_U16(2) |
SHL_PAD_U16(3)
          ),
/* Pads 160 ... 175 : PORT160_EMIOS1_E1UC_12_H_IN_OUT |
PORT164_EMIOS0_E0UC_9_H_IN_OUT |
PORT166_EMIOS1_E1UC_5_H_IN_OUT |
PORT168_EMIOS1_E1UC_7_H_IN_OUT |
PORT173_EMIOS0_E0UC_1_G_IN_OUT |
PORT174_EMIOS0_E0UC_2_G_IN_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(4) |
SHL_PAD_U16(6) |
SHL_PAD_U16(8) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14)
          ),
/* Pads 176 ... 191 : PORT176_EMIOS0_E0UC_4_G_IN_OUT */
  (uint16)( SHL_PAD_U16(0)
          ),
/* Pads 192 ... 207 */
  (uint16)0x0000,
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 */
  (uint16)0x0000,
/* Pads 240 ... 255 */
  (uint16)0x0000,
/* Pads 256 ... 271 */
  (uint16)0x0000
}
,
/*  Mode PORT_INOUT5_MODE: */
{
/* Pads 0 ... 15 */
  (uint16)0x0000,
/* Pads  16 ...  31 : PORT26_EMIOS0_E0UC_29_Y_IN_OUT */
  (uint16)( SHL_PAD_U16(10)
          ),
/* Pads 32 ... 47 */
  (uint16)0x0000,
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads 64 ... 79 */
  (uint16)0x0000,
/* Pads  80 ...  95 : PORT86_EMIOS0_E0UC_30_Y_IN_OUT |
PORT90_FCCU_EOUT0_IN_OUT */
  (uint16)( SHL_PAD_U16(6) |
SHL_PAD_U16(10)
          ),
/* Pads 96 ... 111 */
  (uint16)0x0000,
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 */
  (uint16)0x0000,
/* Pads 144 ... 159 */
  (uint16)0x0000,
/* Pads 160 ... 175 */
  (uint16)0x0000,
/* Pads 176 ... 191 */
  (uint16)0x0000,
/* Pads 192 ... 207 */
  (uint16)0x0000,
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 */
  (uint16)0x0000,
/* Pads 240 ... 255 */
  (uint16)0x0000,
/* Pads 256 ... 271 */
  (uint16)0x0000
}
,
/*  Mode PORT_INOUT6_MODE: */
{
/* Pads 0 ... 15 */
  (uint16)0x0000,
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads 32 ... 47 */
  (uint16)0x0000,
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads 64 ... 79 */
  (uint16)0x0000,
/* Pads  80 ...  95 : PORT87_SAI1_SAI1_MCLK_IN_OUT */
  (uint16)( SHL_PAD_U16(7)
          ),
/* Pads 96 ... 111 */
  (uint16)0x0000,
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 */
  (uint16)0x0000,
/* Pads 144 ... 159 : PORT158_EMIOS1_E1UC_14_H_IN_OUT */
  (uint16)( SHL_PAD_U16(14)
          ),
/* Pads 160 ... 175 */
  (uint16)0x0000,
/* Pads 176 ... 191 */
  (uint16)0x0000,
/* Pads 192 ... 207 */
  (uint16)0x0000,
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 */
  (uint16)0x0000,
/* Pads 240 ... 255 */
  (uint16)0x0000,
/* Pads 256 ... 271 */
  (uint16)0x0000
}
,
/*  Mode PORT_INOUT7_MODE: */
{
/* Pads 0 ... 15 */
  (uint16)0x0000,
/* Pads 16 ... 31 */
  (uint16)0x0000,
/* Pads 32 ... 47 */
  (uint16)0x0000,
/* Pads 48 ... 63 */
  (uint16)0x0000,
/* Pads 64 ... 79 */
  (uint16)0x0000,
/* Pads  80 ...  95 : PORT80_SAI0_SAI0_MCLK_IN_OUT */
  (uint16)( SHL_PAD_U16(0)
          ),
/* Pads 96 ... 111 */
  (uint16)0x0000,
/* Pads 112 ... 127 */
  (uint16)0x0000,
/* Pads 128 ... 143 */
  (uint16)0x0000,
/* Pads 144 ... 159 */
  (uint16)0x0000,
/* Pads 160 ... 175 */
  (uint16)0x0000,
/* Pads 176 ... 191 */
  (uint16)0x0000,
/* Pads 192 ... 207 */
  (uint16)0x0000,
/* Pads 208 ... 223 */
  (uint16)0x0000,
/* Pads 224 ... 239 */
  (uint16)0x0000,
/* Pads 240 ... 255 */
  (uint16)0x0000,
/* Pads 256 ... 271 */
  (uint16)0x0000
}

[!ENDVAR!]




[!VAR "CHECK_"!]

/*  Mode PORT_GPIO_MODE: */
{
/* Pads   0 ...  15 : PORT0_GPIO |
PORT1_GPIO |
PORT2_GPIO |
PORT3_GPIO |
PORT4_GPIO |
PORT5_GPIO |
PORT6_GPIO |
PORT7_GPIO |
PORT8_GPIO |
PORT9_GPIO |
PORT10_GPIO |
PORT11_GPIO |
PORT12_GPIO |
PORT13_GPIO |
PORT14_GPIO |
PORT15_GPIO */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          )
}
,
/*  Mode PORT_ALT1_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_EMIOS0_E0UC_0_X_OUT |
PORT1_EMIOS0_E0UC_1_G_OUT |
PORT2_EMIOS0_E0UC_2_G_OUT |
PORT3_EMIOS0_E0UC_3_G_OUT |
PORT4_EMIOS0_E0UC_4_G_OUT |
PORT5_EMIOS0_E0UC_5_G_OUT |
PORT6_EMIOS0_E0UC_6_G_OUT |
PORT7_EMIOS0_E0UC_7_G_OUT |
PORT8_EMIOS0_E0UC_8_X_OUT |
PORT9_EMIOS0_E0UC_9_H_OUT |
PORT10_EMIOS0_E0UC_10_H_OUT |
PORT11_EMIOS0_E0UC_11_H_OUT |
PORT12_EMIOS0_E0UC_28_Y_OUT |
PORT13_DSPI_0_dSOUT |
PORT14_DSPI_0_dSCLK_OUT |
PORT15_DSPI_0_dCS0 |
PORT16_GPIO |
PORT17_GPIO |
PORT18_GPIO |
PORT19_GPIO |
PORT26_GPIO |
PORT27_GPIO |
PORT28_GPIO |
PORT29_GPIO |
PORT30_GPIO |
PORT31_GPIO */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          )
}
,
/*  Mode PORT_ALT2_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_CGM_CLKOUT0 |
PORT3_LIN_5_LIN5TX |
PORT4_DSPI_1_dCS0 |
PORT5_LIN_4_LIN4TX |
PORT6_DSPI_1_dCS1 |
PORT7_LIN_3_LIN3TX |
PORT8_EMIOS0_E0UC_14_H_OUT |
PORT9_DSPI_1_dCS2 |
PORT10_IIC_0_SDA0_OUT |
PORT11_IIC_0_SCL0_OUT |
PORT12_DSPI_1_dCS3 |
PORT13_EMIOS0_E0UC_29_Y_OUT |
PORT14_DSPI_0_dCS0 |
PORT15_DSPI_0_dSCLK_OUT |
PORT16_FlexCAN_0_TX |
PORT17_EMIOS0_E0UC_31_Y_OUT |
PORT18_LIN_0_LIN0TX |
PORT19_EMIOS0_E0UC_31_Y_OUT |
PORT26_DSPI_1_dSOUT |
PORT27_EMIOS0_E0UC_3_G_OUT |
PORT28_EMIOS0_E0UC_4_G_OUT |
PORT29_EMIOS0_E0UC_5_G_OUT |
PORT30_EMIOS0_E0UC_6_G_OUT |
PORT31_EMIOS0_E0UC_7_G_OUT |
PORT32_GPIO |
PORT33_GPIO |
PORT34_GPIO |
PORT35_GPIO |
PORT36_GPIO |
PORT37_GPIO |
PORT38_GPIO |
PORT39_GPIO |
PORT40_GPIO |
PORT41_GPIO |
PORT42_GPIO |
PORT43_GPIO |
PORT44_GPIO |
PORT45_GPIO |
PORT46_GPIO |
PORT47_GPIO */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          )
}
,
/*  Mode PORT_ALT3_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT0_EMIOS0_E0UC_13_H_OUT |
PORT2_ADC_0_ADC0_MA_2 |
PORT3_DSPI_1_dCS4 |
PORT4_EMIOS0_E0UC_24_X_OUT |
PORT10_LIN_2_LIN2TX |
PORT12_EMIOS0_E0UC_26_Y_OUT |
PORT13_EMIOS0_E0UC_25_Y_OUT |
PORT14_EMIOS0_E0UC_0_X_OUT |
PORT15_EMIOS0_E0UC_1_G_OUT |
PORT16_EMIOS0_E0UC_30_Y_OUT |
PORT17_EMIOS0_E0UC_5_G_OUT |
PORT18_IIC_0_SDA0_OUT |
PORT19_IIC_0_SCL0_OUT |
PORT26_FlexCAN_3_TX |
PORT27_DSPI_0_dCS0 |
PORT28_DSPI_0_dCS1 |
PORT29_DSPI_0_dCS2 |
PORT30_DSPI_0_dCS3 |
PORT31_DSPI_0_dCS4 |
PORT32_DCI_TDI |
PORT33_DCI_TDO |
PORT34_DSPI_1_dSCLK_OUT |
PORT35_DSPI_1_dCS0 |
PORT36_EMIOS1_E1UC_31_Y_OUT |
PORT37_DSPI_1_dSOUT |
PORT38_LIN_1_LIN1TX |
PORT39_EMIOS1_E1UC_29_Y_OUT |
PORT40_LIN_2_LIN2TX |
PORT41_EMIOS0_E0UC_7_G_OUT |
PORT42_FlexCAN_1_TX |
PORT43_ADC_0_ADC0_MA_2 |
PORT44_EMIOS0_E0UC_12_H_OUT |
PORT45_EMIOS0_E0UC_13_H_OUT |
PORT46_EMIOS0_E0UC_14_H_OUT |
PORT47_EMIOS0_E0UC_15_H_OUT |
PORT60_GPIO |
PORT61_GPIO |
PORT62_GPIO |
PORT63_GPIO */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(10) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          )
}
,
/*  Mode PORT_ALT4_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT13_FlexCAN_0_TX |
PORT14_EMIOS0_E0UC_23_X_OUT |
PORT15_EMIOS0_E0UC_21_Y_OUT |
PORT16_LIN_0_LIN0TX |
PORT18_EMIOS0_E0UC_30_Y_OUT |
PORT19_EMIOS0_E0UC_8_X_OUT |
PORT26_CMP2_CMP2_O |
PORT28_HSM_DO1 |
PORT30_FlexRay_FR_DBG_1 |
PORT34_FlexCAN_4_TX |
PORT35_ADC_0_ADC0_MA_0 |
PORT36_FlexRay_FR_B_TX_EN |
PORT37_FlexCAN_3_TX |
PORT38_EMIOS1_E1UC_28_Y_OUT |
PORT39_CMP1_CMP1_O |
PORT40_EMIOS0_E0UC_3_G_OUT |
PORT42_FlexCAN_4_TX |
PORT43_EMIOS0_E0UC_1_G_OUT |
PORT44_FlexRay_FR_DBG_0 |
PORT45_DSPI_2_dSOUT |
PORT46_DSPI_2_dSCLK_OUT |
PORT47_DSPI_2_dCS0 |
PORT60_DSPI_0_dCS5 |
PORT61_DSPI_1_dCS0 |
PORT62_DSPI_1_dCS1 |
PORT63_DSPI_1_dCS2 |
PORT64_GPIO |
PORT65_GPIO |
PORT66_GPIO |
PORT67_GPIO |
PORT68_GPIO |
PORT69_GPIO |
PORT70_GPIO |
PORT71_GPIO |
PORT72_GPIO |
PORT73_GPIO |
PORT74_GPIO |
PORT75_GPIO |
PORT76_GPIO |
PORT77_GPIO |
PORT78_GPIO |
PORT79_GPIO */
  (uint16)( SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(0) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(10) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          )
}
,
/*  Mode PORT_ALT5_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT16_EMIOS0_E0UC_4_G_OUT |
PORT26_SAI0_SAI0_SYNC_OUT |
PORT38_EMIOS0_E0UC_17_Y_OUT |
PORT39_EMIOS0_E0UC_18_Y_OUT |
PORT41_SSCM_SSCM_DBG_7 |
PORT42_ADC_0_ADC0_MA_1 |
PORT45_FlexRay_FR_DBG_1 |
PORT60_EMIOS0_E0UC_24_X_OUT |
PORT61_EMIOS0_E0UC_25_Y_OUT |
PORT62_EMIOS0_E0UC_26_Y_OUT |
PORT63_EMIOS0_E0UC_27_Y_OUT |
PORT64_EMIOS0_E0UC_16_X_OUT |
PORT65_EMIOS0_E0UC_17_Y_OUT |
PORT66_EMIOS0_E0UC_18_Y_OUT |
PORT67_EMIOS0_E0UC_19_Y_OUT |
PORT68_EMIOS0_E0UC_20_Y_OUT |
PORT69_EMIOS0_E0UC_21_Y_OUT |
PORT70_EMIOS0_E0UC_22_X_OUT |
PORT71_EMIOS0_E0UC_23_X_OUT |
PORT72_FlexCAN_2_TX |
PORT73_EMIOS0_E0UC_23_X_OUT |
PORT74_LIN_3_LIN3TX |
PORT75_EMIOS0_E0UC_24_X_OUT |
PORT76_EMIOS1_E1UC_19_Y_OUT |
PORT77_DSPI_2_dSOUT |
PORT78_DSPI_2_dSCLK_OUT |
PORT79_DSPI_2_dCS0 |
PORT80_GPIO |
PORT81_GPIO |
PORT82_GPIO |
PORT83_GPIO |
PORT84_GPIO |
PORT85_GPIO |
PORT86_GPIO |
PORT87_GPIO |
PORT88_GPIO |
PORT89_GPIO |
PORT90_GPIO |
PORT91_GPIO |
PORT92_GPIO |
PORT93_GPIO |
PORT94_GPIO |
PORT95_GPIO */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(10) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(13) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          )
}
,
/*  Mode PORT_ALT6_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT26_EMIOS0_E0UC_29_Y_OUT |
PORT34_SSCM_SSCM_DBG_0 |
PORT35_SSCM_SSCM_DBG_1 |
PORT37_FlexRay_FR_A_TX |
PORT38_SSCM_SSCM_DBG_4 |
PORT39_SSCM_SSCM_DBG_5 |
PORT40_SSCM_SSCM_DBG_6 |
PORT42_CMP0_CMP0_O |
PORT46_FlexRay_FR_DBG_2 |
PORT47_FlexRay_FR_DBG_3 |
PORT60_HSM_DO0 |
PORT61_ENET0_ENET0_TMR0_OUT |
PORT62_FlexRay_FR_DBG_0 |
PORT63_FlexRay_FR_DBG_1 |
PORT64_IIC_1_SCL1_OUT |
PORT65_FlexCAN_5_TX |
PORT66_FlexRay_FR_A_TX_EN |
PORT67_DSPI_1_dSOUT |
PORT68_DSPI_1_dSCLK_OUT |
PORT69_DSPI_1_dCS0 |
PORT70_DSPI_0_dCS3 |
PORT71_DSPI_0_dCS2 |
PORT72_EMIOS0_E0UC_22_X_OUT |
PORT73_IIC_2_SCL2_OUT |
PORT74_DSPI_1_dCS3 |
PORT75_DSPI_1_dCS4 |
PORT77_EMIOS1_E1UC_20_Y_OUT |
PORT78_EMIOS1_E1UC_21_Y_OUT |
PORT79_EMIOS1_E1UC_22_X_OUT |
PORT80_EMIOS0_E0UC_10_H_OUT |
PORT81_EMIOS0_E0UC_11_H_OUT |
PORT82_EMIOS0_E0UC_12_H_OUT |
PORT83_EMIOS0_E0UC_13_H_OUT |
PORT84_EMIOS0_E0UC_14_H_OUT |
PORT85_EMIOS0_E0UC_22_X_OUT |
PORT86_EMIOS0_E0UC_23_X_OUT |
PORT87_SPI_0_SCLK_0_OUT |
PORT88_FlexCAN_3_TX |
PORT89_EMIOS1_E1UC_1_H_OUT |
PORT90_DSPI_0_dCS1 |
PORT91_DSPI_0_dCS2 |
PORT92_EMIOS1_E1UC_25_Y_OUT |
PORT93_EMIOS1_E1UC_26_Y_OUT |
PORT94_FlexCAN_4_TX |
PORT95_EMIOS1_E1UC_4_H_OUT |
PORT96_GPIO |
PORT97_GPIO |
PORT98_GPIO |
PORT99_GPIO |
PORT100_GPIO |
PORT101_GPIO |
PORT102_GPIO |
PORT103_GPIO |
PORT104_GPIO |
PORT105_GPIO |
PORT106_GPIO |
PORT107_GPIO |
PORT108_GPIO |
PORT109_GPIO |
PORT110_GPIO |
PORT111_GPIO */
  (uint16)( SHL_PAD_U16(10) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          )
}
,
/*  Mode PORT_ALT7_FUNC_MODE: */
{
/* Pads   0 ...  15 : PORT36_SSCM_SSCM_DBG_2 |
PORT46_FlexCAN_4_TX |
PORT65_IIC_1_SDA1_OUT |
PORT68_FlexRay_FR_B_TX |
PORT69_ADC_0_ADC0_MA_2 |
PORT70_ADC_0_ADC0_MA_1 |
PORT71_ADC_0_ADC0_MA_0 |
PORT72_FlexCAN_3_TX |
PORT74_EMIOS1_E1UC_30_Y_OUT |
PORT75_CGM_CLKOUT1 |
PORT79_SPI_2_SCLK_2_OUT |
PORT80_DSPI_1_dCS3 |
PORT81_DSPI_1_dCS4 |
PORT82_DSPI_2_dCS0 |
PORT83_DSPI_2_dCS1 |
PORT84_DSPI_2_dCS2 |
PORT85_DSPI_2_dCS3 |
PORT86_DSPI_1_dCS1 |
PORT87_DSPI_1_dCS2 |
PORT88_DSPI_0_dCS4 |
PORT89_DSPI_0_dCS5 |
PORT90_LIN_4_LIN4TX |
PORT91_EMIOS1_E1UC_3_H_OUT |
PORT92_LIN_5_LIN5TX |
PORT93_EMIOS0_E0UC_22_X_OUT |
PORT94_EMIOS1_E1UC_27_Y_OUT |
PORT96_FlexCAN_5_TX |
PORT97_EMIOS1_E1UC_24_X_OUT |
PORT98_EMIOS1_E1UC_11_H_OUT |
PORT99_EMIOS1_E1UC_12_H_OUT |
PORT100_EMIOS1_E1UC_13_H_OUT |
PORT101_EMIOS1_E1UC_14_H_OUT |
PORT102_EMIOS1_E1UC_15_H_OUT |
PORT103_EMIOS1_E1UC_16_X_OUT |
PORT104_EMIOS1_E1UC_17_Y_OUT |
PORT105_EMIOS1_E1UC_18_Y_OUT |
PORT106_EMIOS0_E0UC_24_X_OUT |
PORT107_EMIOS0_E0UC_25_Y_OUT |
PORT108_EMIOS0_E0UC_26_Y_OUT |
PORT109_EMIOS0_E0UC_27_Y_OUT |
PORT110_EMIOS1_E1UC_0_X_OUT |
PORT111_EMIOS1_E1UC_1_H_OUT |
PORT112_GPIO |
PORT113_GPIO |
PORT114_GPIO |
PORT115_GPIO |
PORT116_GPIO |
PORT117_GPIO |
PORT118_GPIO |
PORT119_GPIO |
PORT120_GPIO |
PORT121_GPIO |
PORT122_GPIO |
PORT123_GPIO |
PORT124_GPIO |
PORT125_GPIO |
PORT126_GPIO |
PORT127_GPIO */
  (uint16)( SHL_PAD_U16(4) |
SHL_PAD_U16(14) |
SHL_PAD_U16(1) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(15) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          )
}
,
/*  Mode PORT_ONLY_OUTPUT_MODE: */
{
/* Pads   0 ...  15 : PORT42_LIN_6_LIN6TX |
PORT70_ADC_1_ADC1_MA_1 |
PORT71_ADC_1_ADC1_MA_0 |
PORT72_IIC_2_SDA2_OUT |
PORT74_IIC_3_SDA3_OUT |
PORT75_IIC_3_SCL3_OUT |
PORT81_SPI_0_CS3_0 |
PORT85_SPI_0_CS2_0 |
PORT88_FlexCAN_2_TX |
PORT89_EMIOS0_E0UC_14_H_OUT |
PORT90_EMIOS1_E1UC_2_H_OUT |
PORT91_EMIOS0_E0UC_20_Y_OUT |
PORT92_EMIOS0_E0UC_16_X_OUT |
PORT94_FlexCAN_1_TX |
PORT96_EMIOS1_E1UC_23_X_OUT |
PORT97_ENET0_MII_RMII_0_TX_CLK_OUT |
PORT98_DSPI_3_dSOUT |
PORT99_DSPI_3_dCS0 |
PORT100_DSPI_3_dSCLK_OUT |
PORT101_EMIOS0_E0UC_2_G_OUT |
PORT102_LIN_6_LIN6TX |
PORT103_EMIOS1_E1UC_30_Y_OUT |
PORT104_LIN_7_LIN7TX |
PORT105_DSPI_2_dSCLK_OUT |
PORT106_EMIOS1_E1UC_31_Y_OUT |
PORT107_SPI_0_CS0_0 |
PORT108_SPI_0_SOUT_0 |
PORT109_SPI_0_SCLK_0_OUT |
PORT110_LIN_8_LIN8TX |
PORT111_SPI_2_SOUT_2 |
PORT112_EMIOS1_E1UC_2_H_OUT |
PORT113_EMIOS1_E1UC_3_H_OUT |
PORT114_EMIOS1_E1UC_4_H_OUT |
PORT115_EMIOS1_E1UC_5_H_OUT |
PORT116_EMIOS1_E1UC_6_H_OUT |
PORT117_EMIOS1_E1UC_7_H_OUT |
PORT118_EMIOS1_E1UC_8_X_OUT |
PORT119_EMIOS1_E1UC_9_H_OUT |
PORT120_EMIOS1_E1UC_10_H_OUT |
PORT121_DCI_TCK |
PORT122_DCI_TMS_OUT |
PORT123_DSPI_3_dSOUT |
PORT124_DSPI_3_dSCLK_OUT |
PORT125_SPI_0_SOUT_0 |
PORT126_SPI_0_SCLK_0_OUT |
PORT127_SPI_1_SOUT_1 |
PORT128_GPIO |
PORT129_GPIO |
PORT130_GPIO |
PORT131_GPIO |
PORT132_GPIO |
PORT133_GPIO |
PORT134_GPIO |
PORT135_GPIO |
PORT136_GPIO |
PORT137_GPIO |
PORT138_GPIO |
PORT139_GPIO |
PORT140_GPIO |
PORT141_GPIO |
PORT142_GPIO |
PORT143_GPIO */
  (uint16)( SHL_PAD_U16(10) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(1) |
SHL_PAD_U16(5) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          )
}
,
/*  Mode PORT_ONLY_INPUT_MODE: */
{
/* Pads   0 ...  15 : PORT0_WKPU_WKPU_19 |
PORT1_WKPU_WKPU_2 |
PORT1_WKPU_NMI_0 |
PORT2_WKPU_WKPU_3 |
PORT4_WKPU_WKPU_9 |
PORT15_WKPU_WKPU_10 |
PORT37_SSCM_SSCM_DBG_3 |
PORT72_LIN_6_LIN6TX |
PORT80_FlexCAN_6_TX |
PORT81_SAI0_SAI0_BCLK_OUT |
PORT82_SAI0_SAI0_D3_OUT |
PORT83_SAI0_SAI0_D2_OUT |
PORT84_SAI0_SAI0_D1_OUT |
PORT85_SAI0_SAI0_D0_OUT |
PORT86_SAI1_SAI1_SYNC_OUT |
PORT88_EMIOS0_E0UC_15_H_OUT |
PORT90_EMIOS0_E0UC_19_Y_OUT |
PORT92_FCCU_EOUT1_OUT |
PORT94_ENET0_MII_RMII_0_MDIO_OUT |
PORT96_ENET0_MII_RMII_0_MDC |
PORT98_FlexCAN_7_TX |
PORT100_LIN_10_LIN10TX |
PORT102_CGM_CLKOUT1 |
PORT103_CGM_CLKOUT0 |
PORT104_DSPI_2_dCS0 |
PORT105_EMIOS0_E0UC_0_X_OUT |
PORT107_SPI_2_CS0_2 |
PORT113_DSPI_1_dSOUT |
PORT114_DSPI_1_dSCLK_OUT |
PORT115_DSPI_1_dCS0 |
PORT116_SPI_3_SOUT_3 |
PORT117_IIC_3_SDA3_OUT |
PORT118_SPI_3_SCLK_3_OUT |
PORT119_DSPI_2_dCS3 |
PORT120_DSPI_2_dCS2 |
PORT123_SPI_0_CS0_0 |
PORT124_SPI_0_CS1_0 |
PORT125_DSPI_3_dCS0 |
PORT126_DSPI_3_dCS1 |
PORT128_EMIOS0_E0UC_28_Y_OUT |
PORT129_EMIOS0_E0UC_29_Y_OUT |
PORT130_EMIOS0_E0UC_30_Y_OUT |
PORT131_EMIOS0_E0UC_31_Y_OUT |
PORT132_EMIOS1_E1UC_28_Y_OUT |
PORT133_EMIOS1_E1UC_29_Y_OUT |
PORT134_EMIOS1_E1UC_30_Y_OUT |
PORT135_EMIOS1_E1UC_31_Y_OUT |
PORT140_DSPI_3_dCS0 |
PORT141_DSPI_3_dCS1 |
PORT142_SAI2_SAI2_D0_OUT |
PORT143_SPI_0_CS0_0 |
PORT144_GPIO |
PORT145_GPIO |
PORT146_GPIO |
PORT147_GPIO |
PORT148_GPIO |
PORT149_GPIO |
PORT150_GPIO |
PORT151_GPIO |
PORT152_GPIO |
PORT153_GPIO |
PORT154_GPIO |
PORT155_GPIO |
PORT156_GPIO |
PORT157_GPIO |
PORT158_GPIO |
PORT159_GPIO */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(4) |
SHL_PAD_U16(15) |
SHL_PAD_U16(5) |
SHL_PAD_U16(8) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14) |
SHL_PAD_U16(0) |
SHL_PAD_U16(2) |
SHL_PAD_U16(4) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(11) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          )
}
,
/*  Mode PORT_ANALOG_INPUT_MODE: */
{
/* Pads   0 ...  15 : PORT3_ADC_1_ADC1_S_0 |
PORT4_CMP1_CMP1_13 |
PORT7_ADC_1_ADC1_S_8 |
PORT8_ADC_1_ADC1_S_9 |
PORT9_ADC_1_ADC1_S_10 |
PORT10_ADC_1_ADC1_S_11 |
PORT11_ADC_1_ADC1_S_12 |
PORT12_CMP1_CMP1_15 |
PORT13_CMP1_CMP1_14 |
PORT14_CMP1_CMP1_12 |
PORT15_CMP1_CMP1_10 |
PORT17_WKPU_WKPU_4 |
PORT19_WKPU_WKPU_11 |
PORT20_GPI |
PORT21_GPI |
PORT22_GPI |
PORT23_GPI |
PORT24_GPI |
PORT24_WKPU_WKPU_25 |
PORT24_XOSC_OSC32K_XTAL |
PORT25_GPI |
PORT25_WKPU_WKPU_26 |
PORT25_XOSC_OSC32K_EXTAL |
PORT26_WKPU_WKPU_8 |
PORT86_EMIOS0_E0UC_30_Y_OUT |
PORT90_FCCU_EOUT0_OUT |
PORT98_LIN_11_LIN11TX |
PORT102_EMIOS0_E0UC_3_G_OUT |
PORT104_FlexCAN_7_TX |
PORT108_ENET0_MII_0_TXD_2 |
PORT109_ENET0_MII_0_TXD_3 |
PORT112_ENET0_MII_RMII_0_TXD_1 |
PORT115_ENET0_MII_0_TX_ER |
PORT116_IIC_3_SCL3_OUT |
PORT118_ADC_0_ADC0_MA_2 |
PORT119_ADC_0_ADC0_MA_1 |
PORT120_ADC_0_ADC0_MA_0 |
PORT123_EMIOS1_E1UC_5_H_OUT |
PORT124_EMIOS1_E1UC_25_Y_OUT |
PORT125_EMIOS1_E1UC_26_Y_OUT |
PORT126_EMIOS1_E1UC_27_Y_OUT |
PORT127_EMIOS1_E1UC_17_Y_OUT |
PORT128_LIN_8_LIN8TX |
PORT129_IIC_1_SCL1_OUT |
PORT130_LIN_9_LIN9TX |
PORT131_IIC_2_SCL2_OUT |
PORT132_SPI_0_SOUT_0 |
PORT133_SPI_0_SCLK_0_OUT |
PORT134_SPI_0_CS0_0 |
PORT135_SPI_0_CS1_0 |
PORT139_ENET0_ENET0_TMR1_OUT |
PORT140_DSPI_2_dCS0 |
PORT141_DSPI_2_dCS1 |
PORT143_DSPI_2_dCS2 |
PORT144_SPI_0_CS1_0 |
PORT145_SPI_0_SOUT_0 |
PORT146_SPI_1_CS0_1 |
PORT147_SPI_1_CS1_1 |
PORT148_SPI_1_SCLK_1_OUT |
PORT155_FlexCAN_2_TX |
PORT156_EMIOS1_E1UC_10_H_OUT |
PORT157_SPI_3_CS1_3 |
PORT158_FlexCAN_1_TX |
PORT159_SPI_2_CS1_2 |
PORT160_GPIO |
PORT161_GPIO |
PORT162_GPIO |
PORT163_GPIO |
PORT164_GPIO |
PORT165_GPIO |
PORT166_GPIO |
PORT167_GPIO |
PORT168_GPIO |
PORT169_GPIO |
PORT170_GPIO |
PORT171_GPIO |
PORT172_GPIO |
PORT173_GPIO |
PORT174_GPIO |
PORT175_GPIO */
  (uint16)( SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(1) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(8) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(9) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(6) |
SHL_PAD_U16(10) |
SHL_PAD_U16(2) |
SHL_PAD_U16(6) |
SHL_PAD_U16(8) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(0) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(15) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          )
}
,
/*  Mode PORT_INPUT1_MODE: */
{
/* Pads   0 ...  15 : PORT0_EMIOS0_E0UC_0_X_IN |
PORT1_EMIOS0_E0UC_1_G_IN |
PORT2_EMIOS0_E0UC_2_G_IN |
PORT3_EMIOS0_E0UC_3_G_IN |
PORT4_EMIOS0_E0UC_4_G_IN |
PORT5_EMIOS0_E0UC_5_G_IN |
PORT6_EMIOS0_E0UC_6_G_IN |
PORT7_EMIOS0_E0UC_7_G_IN |
PORT8_EMIOS0_E0UC_8_X_IN |
PORT9_EMIOS0_E0UC_9_H_IN |
PORT10_EMIOS0_E0UC_10_H_IN |
PORT11_EMIOS0_E0UC_11_H_IN |
PORT12_EMIOS0_E0UC_28_Y_IN |
PORT13_EMIOS0_E0UC_29_Y_IN |
PORT14_EMIOS0_E0UC_0_X_IN |
PORT15_EMIOS0_E0UC_1_G_IN |
PORT16_CMP0_CMP0_2 |
PORT17_CMP0_CMP0_3 |
PORT20_ADC_1_ADC1_P_0 |
PORT21_ADC_1_ADC1_P_1 |
PORT22_ADC_1_ADC1_P_2 |
PORT23_ADC_1_ADC1_P_3 |
PORT24_ADC_0_ADC0_S_0 |
PORT25_ADC_0_ADC0_S_1 |
PORT26_ADC_0_ADC0_S_2 |
PORT27_ADC_0_ADC0_S_3 |
PORT28_ADC_0_ADC0_X_0 |
PORT29_ADC_0_ADC0_X_1 |
PORT30_ADC_0_ADC0_X_2 |
PORT31_ADC_0_ADC0_X_3 |
PORT39_WKPU_WKPU_12 |
PORT41_WKPU_WKPU_13 |
PORT43_WKPU_WKPU_5 |
PORT87_SAI1_SAI1_MCLK_OUT |
PORT113_ENET0_MII_RMII_0_TXD_0 |
PORT114_ENET0_MII_RMII_0_TX_EN |
PORT118_ADC_1_ADC1_MA_2 |
PORT119_SPI_3_CS0_3 |
PORT120_ADC_1_ADC1_MA_0 |
PORT125_FCCU_EOUT1_OUT |
PORT127_FCCU_EOUT0_OUT |
PORT128_IIC_1_SDA1_OUT |
PORT130_IIC_2_SDA2_OUT |
PORT133_SPI_1_CS2_1 |
PORT134_SPI_1_CS0_1 |
PORT135_SPI_1_CS1_1 |
PORT143_SAI2_SAI2_MCLK_OUT |
PORT144_DSPI_2_dCS3 |
PORT145_SAI2_SAI2_BCLK_OUT |
PORT146_SPI_2_CS0_2 |
PORT147_SPI_2_CS1_2 |
PORT148_EMIOS1_E1UC_18_Y_OUT |
PORT149_SAI2_SAI2_D0_OUT |
PORT150_SAI2_SAI2_BCLK_OUT |
PORT152_SAI2_SAI2_SYNC_OUT |
PORT153_FlexCAN_4_TX |
PORT154_EMIOS1_E1UC_16_X_OUT |
PORT155_EMIOS1_E1UC_11_H_OUT |
PORT158_FlexCAN_4_TX |
PORT159_EMIOS1_E1UC_13_H_OUT |
PORT160_FlexCAN_1_TX |
PORT161_SPI_2_CS3_2 |
PORT162_FlexCAN_4_TX |
PORT163_EMIOS1_E1UC_0_X_OUT |
PORT164_FlexCAN_5_TX |
PORT165_EMIOS0_E0UC_10_H_OUT |
PORT166_FlexCAN_2_TX |
PORT167_EMIOS0_E0UC_12_H_OUT |
PORT168_FlexCAN_3_TX |
PORT169_EMIOS1_E1UC_29_Y_OUT |
PORT170_SPI_0_SOUT_0 |
PORT171_SPI_0_SCLK_0_OUT |
PORT172_SPI_0_CS0_0 |
PORT173_SPI_2_CS3_2 |
PORT174_FlexCAN_3_TX |
PORT175_SPI_0_CS2_0 |
PORT176_GPIO |
PORT177_GPIO |
PORT178_GPIO |
PORT179_GPIO |
PORT180_GPIO |
PORT181_GPIO |
PORT182_GPIO |
PORT183_GPIO |
PORT184_GPIO |
PORT185_GPIO |
PORT186_GPIO |
PORT187_GPIO |
PORT188_GPIO |
PORT189_GPIO |
PORT190_GPIO |
PORT191_GPIO */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(7) |
SHL_PAD_U16(9) |
SHL_PAD_U16(11) |
SHL_PAD_U16(7) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(13) |
SHL_PAD_U16(15) |
SHL_PAD_U16(0) |
SHL_PAD_U16(2) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(15) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          )
}
,
/*  Mode PORT_INPUT2_MODE: */
{
/* Pads   0 ...  15 : PORT0_EMIOS0_E0UC_13_H_IN |
PORT1_FlexCAN_3_RX |
PORT3_SIUL2_EIRQ0 |
PORT4_LIN_5_LIN5RX |
PORT6_SIUL2_EIRQ1 |
PORT7_SIUL2_EIRQ2 |
PORT8_EMIOS0_E0UC_14_H_IN |
PORT9_ENET0_MII_RMII_0_RXD_0 |
PORT10_IIC_0_SDA0_IN |
PORT11_SIUL2_EIRQ16 |
PORT12_SIUL2_EIRQ17 |
PORT13_EMIOS0_E0UC_25_Y_IN |
PORT14_SIUL2_EIRQ4 |
PORT15_FlexCAN_0_RX |
PORT16_EMIOS0_E0UC_30_Y_IN |
PORT17_EMIOS0_E0UC_31_Y_IN |
PORT18_EMIOS0_E0UC_30_Y_IN |
PORT19_EMIOS0_E0UC_31_Y_IN |
PORT26_FlexCAN_6_RX |
PORT27_EMIOS0_E0UC_3_G_IN |
PORT28_EMIOS0_E0UC_4_G_IN |
PORT29_EMIOS0_E0UC_5_G_IN |
PORT30_EMIOS0_E0UC_6_G_IN |
PORT31_EMIOS0_E0UC_7_G_IN |
PORT38_CMP0_CMP0_7 |
PORT48_GPI |
PORT48_WKPU_WKPU_27 |
PORT49_GPI |
PORT49_WKPU_WKPU_28 |
PORT50_GPI |
PORT51_GPI |
PORT52_GPI |
PORT53_GPI |
PORT54_GPI |
PORT55_GPI |
PORT56_GPI |
PORT57_GPI |
PORT58_GPI |
PORT59_GPI |
PORT80_SAI0_SAI0_MCLK_OUT |
PORT119_ADC_1_ADC1_MA_1 |
PORT133_SPI_2_CS2_2 |
PORT134_SPI_2_CS0_2 |
PORT135_SPI_2_CS1_2 |
PORT144_SAI2_SAI2_SYNC_OUT |
PORT146_SPI_3_CS0_3 |
PORT147_SPI_3_CS1_3 |
PORT151_SAI2_SAI2_MCLK_OUT |
PORT153_EMIOS1_E1UC_17_Y_OUT |
PORT157_EMIOS1_E1UC_15_H_OUT |
PORT158_SPI_3_CS2_3 |
PORT160_SPI_2_CS2_2 |
PORT161_EMIOS0_E0UC_6_G_OUT |
PORT164_LIN_8_LIN8TX |
PORT165_EMIOS1_E1UC_4_H_OUT |
PORT166_LIN_2_LIN2TX |
PORT167_EMIOS1_E1UC_6_H_OUT |
PORT168_LIN_3_LIN3TX |
PORT170_EMIOS1_E1UC_30_Y_OUT |
PORT171_EMIOS1_E1UC_31_Y_OUT |
PORT172_EMIOS0_E0UC_0_X_OUT |
PORT173_SPI_3_CS2_3 |
PORT174_SPI_3_CS3_3 |
PORT175_EMIOS0_E0UC_3_G_OUT |
PORT176_SPI_1_SOUT_1 |
PORT177_SAI0_SAI0_D0_OUT |
PORT178_DCI_MDO_0 |
PORT179_DCI_MDO_1 |
PORT180_DCI_MDO_2 |
PORT181_DCI_MDO_3 |
PORT182_DCI_MDO_4 |
PORT183_DCI_MDO_5 |
PORT184_DCI_EVTI |
PORT185_DCI_MSEO0 |
PORT186_DCI_MCKO |
PORT187_DCI_MSEO1 |
PORT188_DCI_EVTO |
PORT189_DCI_MDO_6 |
PORT190_DCI_MDO_7 |
PORT191_DCI_MDO_8 |
PORT192_GPIO |
PORT193_GPIO |
PORT194_GPIO |
PORT195_GPIO |
PORT196_GPIO |
PORT197_GPIO |
PORT198_GPIO |
PORT199_GPIO |
PORT200_GPIO |
PORT201_GPIO |
PORT202_GPIO |
PORT205_GPIO |
PORT206_GPIO */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(6) |
SHL_PAD_U16(0) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(0) |
SHL_PAD_U16(7) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(0) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(7) |
SHL_PAD_U16(9) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14)
          )
}
,
/*  Mode PORT_INPUT3_MODE: */
{
/* Pads   0 ...  15 : PORT0_FlexCAN_1_RX |
PORT3_ENET0_MII_0_RX_CLK |
PORT4_DSPI_1_dSS |
PORT6_LIN_4_LIN4RX |
PORT7_ENET0_MII_0_RXD_2 |
PORT8_SIUL2_EIRQ3 |
PORT10_DSPI_1_dSIN |
PORT11_LIN_2_LIN2RX |
PORT12_DSPI_0_dSIN |
PORT13_GLITCH_FILTER0_INP |
PORT14_DSPI_0_dSCLK_IN |
PORT15_DSPI_0_dSCLK_IN |
PORT16_EMIOS0_E0UC_4_G_IN |
PORT17_FlexCAN_0_RX |
PORT18_IIC_0_SDA0_IN |
PORT19_LIN_0_LIN0RX |
PORT26_SAI0_SAI0_SYNC_IN |
PORT27_DSPI_0_dSS |
PORT34_SIUL2_EIRQ5 |
PORT35_SIUL2_EIRQ6 |
PORT36_EMIOS1_E1UC_31_Y_IN |
PORT37_SIUL2_EIRQ7 |
PORT38_EMIOS1_E1UC_28_Y_IN |
PORT39_EMIOS1_E1UC_29_Y_IN |
PORT40_EMIOS0_E0UC_3_G_IN |
PORT41_EMIOS0_E0UC_7_G_IN |
PORT43_FlexCAN_1_RX |
PORT44_EMIOS0_E0UC_12_H_IN |
PORT45_EMIOS0_E0UC_13_H_IN |
PORT46_EMIOS0_E0UC_14_H_IN |
PORT47_EMIOS0_E0UC_15_H_IN |
PORT48_ADC_1_ADC1_P_4 |
PORT49_ADC_1_ADC1_P_5 |
PORT50_ADC_1_ADC1_P_6 |
PORT51_ADC_1_ADC1_P_7 |
PORT52_ADC_1_ADC1_P_8 |
PORT53_ADC_1_ADC1_P_9 |
PORT54_ADC_1_ADC1_P_10 |
PORT55_ADC_1_ADC1_P_11 |
PORT56_ADC_1_ADC1_P_12 |
PORT57_ADC_1_ADC1_P_13 |
PORT58_ADC_1_ADC1_P_14 |
PORT59_ADC_1_ADC1_P_15 |
PORT60_ADC_0_ADC0_S_4 |
PORT61_ADC_0_ADC0_S_5 |
PORT62_ADC_0_ADC0_S_6 |
PORT63_ADC_0_ADC0_S_7 |
PORT64_WKPU_WKPU_6 |
PORT67_WKPU_WKPU_29 |
PORT69_WKPU_WKPU_30 |
PORT73_WKPU_WKPU_7 |
PORT75_WKPU_WKPU_14 |
PORT134_HSM_DO0 |
PORT135_HSM_DO1 |
PORT146_SAI1_SAI1_D0_OUT |
PORT147_SAI1_SAI1_BCLK_OUT |
PORT158_FlexCAN_6_TX |
PORT160_FlexCAN_3_TX |
PORT161_EMIOS1_E1UC_1_H_OUT |
PORT162_EMIOS1_E1UC_2_H_OUT |
PORT163_EMIOS1_E1UC_3_H_OUT |
PORT164_EMIOS1_E1UC_1_H_OUT |
PORT166_EMIOS0_E0UC_11_H_OUT |
PORT168_EMIOS0_E0UC_13_H_OUT |
PORT170_LIN_15_LIN15TX |
PORT171_LIN_14_LIN14TX |
PORT173_SPI_1_SCLK_1_OUT |
PORT174_SPI_1_CS0_1 |
PORT175_LIN_13_LIN13TX |
PORT176_SPI_3_SOUT_3 |
PORT192_DCI_MDO_9 |
PORT193_DCI_MDO_10 |
PORT194_DCI_MDO_11 |
PORT195_SAI0_SAI0_D1_OUT |
PORT196_SAI0_SAI0_D2_OUT |
PORT197_SAI0_SAI0_D3_OUT |
PORT199_DCI_MDO_12 |
PORT200_DCI_MDO_13 |
PORT201_DCI_MDO_14 |
PORT202_DCI_MDO_15 |
PORT206_SAI0_SAI0_MCLK_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(0) |
SHL_PAD_U16(3) |
SHL_PAD_U16(5) |
SHL_PAD_U16(9) |
SHL_PAD_U16(11) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(14) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(6) |
SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(0) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(14)
          )
}
,
/*  Mode PORT_INPUT4_MODE: */
{
/* Pads   0 ...  15 : PORT4_EMIOS0_E0UC_24_X_IN |
PORT8_LIN_3_LIN3RX |
PORT10_ENET0_MII_0_COL |
PORT11_IIC_0_SCL0_IN |
PORT12_EMIOS0_E0UC_26_Y_IN |
PORT14_DSPI_0_dSS |
PORT15_DSPI_0_dSS |
PORT16_GLITCH_FILTER1_INP |
PORT17_LIN_0_LIN0RX |
PORT18_GLITCH_FILTER1_INP |
PORT19_IIC_0_SCL0_IN |
PORT26_EMIOS0_E0UC_29_Y_IN |
PORT34_DSPI_1_dSCLK_IN |
PORT35_FlexCAN_1_RX |
PORT36_SIUL2_EIRQ18 |
PORT38_EMIOS0_E0UC_17_Y_IN |
PORT39_LIN_1_LIN1RX |
PORT41_LIN_2_LIN2RX |
PORT43_FlexCAN_4_RX |
PORT44_SIUL2_EIRQ19 |
PORT46_SIUL2_EIRQ8 |
PORT47_SIUL2_EIRQ20 |
PORT60_EMIOS0_E0UC_24_X_IN |
PORT61_EMIOS0_E0UC_25_Y_IN |
PORT62_EMIOS0_E0UC_26_Y_IN |
PORT63_EMIOS0_E0UC_27_Y_IN |
PORT76_ADC_1_ADC1_S_13 |
PORT77_ADC_1_ADC1_X_3 |
PORT89_WKPU_WKPU_22 |
PORT90_FCCU_EOUT0_IN |
PORT91_WKPU_WKPU_15 |
PORT92_FCCU_EOUT1_IN |
PORT93_WKPU_WKPU_16 |
PORT102_PMCDIG_EXTREGC |
PORT160_EMIOS1_E1UC_12_H_OUT |
PORT164_EMIOS0_E0UC_9_H_OUT |
PORT166_EMIOS1_E1UC_5_H_OUT |
PORT168_EMIOS1_E1UC_7_H_OUT |
PORT173_EMIOS0_E0UC_1_G_OUT |
PORT174_EMIOS0_E0UC_2_G_OUT |
PORT176_SPI_0_CS3_0 |
PORT195_ENET0_ENET0_TMR2_OUT |
PORT197_DCI_TCK_ALT |
PORT198_DCI_TDI_ALT |
PORT205_DCI_TDO_ALT |
PORT206_DCI_TMS_ALT_OUT |
PORT224_GPIO |
PORT225_GPIO */
  (uint16)( SHL_PAD_U16(4) |
SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(10) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(9) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(6) |
SHL_PAD_U16(0) |
SHL_PAD_U16(4) |
SHL_PAD_U16(6) |
SHL_PAD_U16(8) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(0) |
SHL_PAD_U16(3) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1)
          )
}
,
/*  Mode PORT_INPUT5_MODE: */
{
/* Pads   0 ...  15 : PORT8_ENET0_MII_RMII_0_RXD_1 |
PORT11_ENET0_MII_RMII_0_RX_ER |
PORT12_GLITCH_FILTER0_INP |
PORT14_EMIOS0_E0UC_23_X_IN |
PORT15_EMIOS0_E0UC_21_Y_IN |
PORT17_EMIOS0_E0UC_5_G_IN |
PORT19_EMIOS0_E0UC_8_X_IN |
PORT35_FlexCAN_4_RX |
PORT36_FlexCAN_3_RX |
PORT38_GLITCH_FILTER2_INP |
PORT39_EMIOS0_E0UC_18_Y_IN |
PORT43_EMIOS0_E0UC_1_G_IN |
PORT44_DSPI_2_dSIN |
PORT46_DSPI_2_dSCLK_IN |
PORT47_DSPI_2_dSS |
PORT61_DSPI_1_dSS |
PORT64_EMIOS0_E0UC_16_X_IN |
PORT65_EMIOS0_E0UC_17_Y_IN |
PORT66_EMIOS0_E0UC_18_Y_IN |
PORT67_EMIOS0_E0UC_19_Y_IN |
PORT68_EMIOS0_E0UC_20_Y_IN |
PORT69_EMIOS0_E0UC_21_Y_IN |
PORT70_EMIOS0_E0UC_22_X_IN |
PORT71_EMIOS0_E0UC_23_X_IN |
PORT72_EMIOS0_E0UC_22_X_IN |
PORT73_EMIOS0_E0UC_23_X_IN |
PORT74_EMIOS1_E1UC_30_Y_IN |
PORT75_EMIOS0_E0UC_24_X_IN |
PORT76_EMIOS1_E1UC_19_Y_IN |
PORT77_EMIOS1_E1UC_20_Y_IN |
PORT78_EMIOS1_E1UC_21_Y_IN |
PORT79_EMIOS1_E1UC_22_X_IN |
PORT80_ADC_0_ADC0_S_8 |
PORT80_CMP2_CMP2_16 |
PORT81_ADC_0_ADC0_S_9 |
PORT81_CMP2_CMP2_17 |
PORT82_ADC_0_ADC0_S_10 |
PORT82_CMP2_CMP2_18 |
PORT83_ADC_0_ADC0_S_11 |
PORT83_CMP2_CMP2_19 |
PORT84_ADC_0_ADC0_S_12 |
PORT84_CMP2_CMP2_20 |
PORT85_ADC_0_ADC0_S_13 |
PORT85_CMP2_CMP2_21 |
PORT86_ADC_0_ADC0_S_14 |
PORT86_CMP2_CMP2_22 |
PORT87_ADC_0_ADC0_S_15 |
PORT87_CMP2_CMP2_23 |
PORT88_CMP0_CMP0_5 |
PORT89_CMP0_CMP0_4 |
PORT90_CMP1_CMP1_8 |
PORT91_CMP1_CMP1_9 |
PORT92_CMP0_CMP0_6 |
PORT93_CMP1_CMP1_11 |
PORT94_ADC_1_ADC1_X_2 |
PORT95_ADC_1_ADC1_X_1 |
PORT99_WKPU_WKPU_17 |
PORT101_WKPU_WKPU_18 |
PORT103_WKPU_WKPU_20 |
PORT105_WKPU_WKPU_21 |
PORT158_EMIOS1_E1UC_14_H_OUT |
PORT176_EMIOS0_E0UC_4_G_OUT |
PORT252_GPIO |
PORT253_GPIO |
PORT254_GPIO |
PORT255_GPIO */
  (uint16)( SHL_PAD_U16(8) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(1) |
SHL_PAD_U16(3) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(13) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(0) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(3) |
SHL_PAD_U16(5) |
SHL_PAD_U16(7) |
SHL_PAD_U16(9) |
SHL_PAD_U16(14) |
SHL_PAD_U16(0) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          )
}
,
/*  Mode PORT_INPUT6_MODE: */
{
/* Pads   0 ...  15 : PORT17_GLITCH_FILTER1_INP |
PORT19_GLITCH_FILTER1_INP |
PORT35_DSPI_1_dSS |
PORT36_DSPI_1_dSIN |
PORT39_GLITCH_FILTER2_INP |
PORT47_FlexCAN_4_RX |
PORT61_ENET0_ENET0_TMR0_IN |
PORT64_FlexCAN_5_RX |
PORT65_IIC_1_SDA1_IN |
PORT66_SIUL2_EIRQ21 |
PORT67_FlexRay_FR_A_RX |
PORT68_SIUL2_EIRQ9 |
PORT69_FlexRay_FR_B_RX |
PORT70_SIUL2_EIRQ22 |
PORT71_SIUL2_EIRQ23 |
PORT72_IIC_2_SDA2_IN |
PORT73_FlexCAN_2_RX |
PORT74_SIUL2_EIRQ10 |
PORT75_LIN_3_LIN3RX |
PORT76_SIUL2_EIRQ11 |
PORT77_ENET0_MII_0_RXD_3 |
PORT78_SIUL2_EIRQ12 |
PORT79_DSPI_2_dSS |
PORT80_EMIOS0_E0UC_10_H_IN |
PORT81_EMIOS0_E0UC_11_H_IN |
PORT82_EMIOS0_E0UC_12_H_IN |
PORT83_EMIOS0_E0UC_13_H_IN |
PORT84_EMIOS0_E0UC_14_H_IN |
PORT85_EMIOS0_E0UC_22_X_IN |
PORT86_EMIOS0_E0UC_23_X_IN |
PORT87_SPI_0_SCLK_0_IN |
PORT88_EMIOS0_E0UC_15_H_IN |
PORT89_EMIOS1_E1UC_1_H_IN |
PORT90_EMIOS1_E1UC_2_H_IN |
PORT91_EMIOS1_E1UC_3_H_IN |
PORT92_EMIOS1_E1UC_25_Y_IN |
PORT93_EMIOS1_E1UC_26_Y_IN |
PORT94_EMIOS1_E1UC_27_Y_IN |
PORT95_EMIOS1_E1UC_4_H_IN |
PORT96_ADC_1_ADC1_X_0 |
PORT97_ADC_1_ADC1_S_7 |
PORT102_CMP0_CMP0_1 |
PORT103_CMP0_CMP0_0 |
PORT108_ADC_1_ADC1_S_2 |
PORT109_ADC_1_ADC1_S_1 |
PORT122_DCI_TMS_IN |
PORT125_FCCU_EOUT1_IN |
PORT127_FCCU_EOUT0_IN |
PORT224_IIC_0_SDA0_OUT |
PORT225_IIC_0_SCL0_OUT |
PORT252_SPI_2_CS0_2 |
PORT253_SPI_2_SOUT_2 |
PORT254_SPI_2_SCLK_2_OUT |
PORT255_EMIOS1_E1UC_21_Y_OUT |
PORT256_GPIO |
PORT257_GPIO |
PORT258_GPIO |
PORT259_GPIO |
PORT260_GPIO |
PORT261_GPIO |
PORT262_GPIO |
PORT263_GPIO */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(3) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(7) |
SHL_PAD_U16(15) |
SHL_PAD_U16(13) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(10) |
SHL_PAD_U16(13) |
SHL_PAD_U16(15) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7)
          )
}
,
/*  Mode PORT_INOUT1_MODE: */
{
/* Pads   0 ...  15 : PORT0_EMIOS0_E0UC_0_X_IN_OUT |
PORT1_EMIOS0_E0UC_1_G_IN_OUT |
PORT2_EMIOS0_E0UC_2_G_IN_OUT |
PORT3_EMIOS0_E0UC_3_G_IN_OUT |
PORT4_EMIOS0_E0UC_4_G_IN_OUT |
PORT5_EMIOS0_E0UC_5_G_IN_OUT |
PORT6_EMIOS0_E0UC_6_G_IN_OUT |
PORT7_EMIOS0_E0UC_7_G_IN_OUT |
PORT8_EMIOS0_E0UC_8_X_IN_OUT |
PORT9_EMIOS0_E0UC_9_H_IN_OUT |
PORT10_EMIOS0_E0UC_10_H_IN_OUT |
PORT11_EMIOS0_E0UC_11_H_IN_OUT |
PORT12_EMIOS0_E0UC_28_Y_IN_OUT |
PORT14_DSPI_0_dSCLK_IN_OUT |
PORT36_GLITCH_FILTER3_INP |
PORT64_LIN_11_LIN11RX |
PORT66_DSPI_1_dSIN |
PORT68_DSPI_1_dSCLK_IN |
PORT69_DSPI_1_dSS |
PORT73_FlexCAN_3_RX |
PORT74_IIC_3_SDA3_IN |
PORT75_IIC_3_SCL3_IN |
PORT76_DSPI_2_dSIN |
PORT78_DSPI_2_dSCLK_IN |
PORT79_SPI_2_SCLK_2_IN |
PORT80_SAI0_SAI0_MCLK_IN |
PORT81_SAI0_SAI0_BCLK_IN |
PORT82_DSPI_2_dSS |
PORT83_SAI0_SAI0_D2_IN |
PORT84_SAI0_SAI0_D1_IN |
PORT85_SAI0_SAI0_D0_IN |
PORT86_SAI1_SAI1_SYNC_IN |
PORT87_SAI1_SAI1_MCLK_IN |
PORT89_FlexCAN_2_RX |
PORT90_EMIOS0_E0UC_19_Y_IN |
PORT91_LIN_4_LIN4RX |
PORT92_EMIOS0_E0UC_16_X_IN |
PORT93_LIN_5_LIN5RX |
PORT94_ENET0_MII_RMII_0_MDIO_IN |
PORT95_SIUL2_EIRQ13 |
PORT96_EMIOS1_E1UC_23_X_IN |
PORT97_EMIOS1_E1UC_24_X_IN |
PORT98_EMIOS1_E1UC_11_H_IN |
PORT99_EMIOS1_E1UC_12_H_IN |
PORT100_EMIOS1_E1UC_13_H_IN |
PORT101_EMIOS1_E1UC_14_H_IN |
PORT102_EMIOS1_E1UC_15_H_IN |
PORT103_EMIOS1_E1UC_16_X_IN |
PORT104_EMIOS1_E1UC_17_Y_IN |
PORT105_EMIOS1_E1UC_18_Y_IN |
PORT106_EMIOS0_E0UC_24_X_IN |
PORT107_EMIOS0_E0UC_25_Y_IN |
PORT108_EMIOS0_E0UC_26_Y_IN |
PORT109_EMIOS0_E0UC_27_Y_IN |
PORT110_EMIOS1_E1UC_0_X_IN |
PORT111_EMIOS1_E1UC_1_H_IN |
PORT112_ADC_1_ADC1_S_3 |
PORT113_ADC_1_ADC1_S_4 |
PORT114_ADC_1_ADC1_S_5 |
PORT115_ADC_1_ADC1_S_6 |
PORT129_WKPU_WKPU_24 |
PORT131_WKPU_WKPU_23 |
PORT224_LIN_12_LIN12TX |
PORT252_DSPI_0_dCS4 |
PORT253_EMIOS1_E1UC_23_X_OUT |
PORT254_EMIOS1_E1UC_22_X_OUT |
PORT256_DSPI_0_dCS1 |
PORT257_DSPI_0_dCS0 |
PORT258_DSPI_0_dSCLK_OUT |
PORT260_DSPI_0_dSOUT |
PORT261_SPI_2_CS3_2 |
PORT262_SPI_2_CS2_2 |
PORT263_SPI_2_CS1_2 */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14) |
SHL_PAD_U16(4) |
SHL_PAD_U16(0) |
SHL_PAD_U16(2) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(1) |
SHL_PAD_U16(3) |
SHL_PAD_U16(0) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7)
          )
}
,
/*  Mode PORT_INOUT2_MODE: */
{
/* Pads   0 ...  15 : PORT8_EMIOS0_E0UC_14_H_IN_OUT |
PORT10_IIC_0_SDA0_IN_OUT |
PORT11_IIC_0_SCL0_IN_OUT |
PORT13_EMIOS0_E0UC_29_Y_IN_OUT |
PORT15_DSPI_0_dSCLK_IN_OUT |
PORT17_EMIOS0_E0UC_31_Y_IN_OUT |
PORT19_EMIOS0_E0UC_31_Y_IN_OUT |
PORT27_EMIOS0_E0UC_3_G_IN_OUT |
PORT28_EMIOS0_E0UC_4_G_IN_OUT |
PORT29_EMIOS0_E0UC_5_G_IN_OUT |
PORT30_EMIOS0_E0UC_6_G_IN_OUT |
PORT31_EMIOS0_E0UC_7_G_IN_OUT |
PORT64_IIC_1_SCL1_IN |
PORT73_IIC_2_SCL2_IN |
PORT74_GLITCH_FILTER3_INP |
PORT76_ENET0_MII_0_CRS |
PORT82_SAI0_SAI0_D3_IN |
PORT83_GLITCH_FILTER1_INP |
PORT84_GLITCH_FILTER2_INP |
PORT85_GLITCH_FILTER3_INP |
PORT86_EMIOS0_E0UC_30_Y_IN |
PORT89_FlexCAN_3_RX |
PORT91_EMIOS0_E0UC_20_Y_IN |
PORT93_EMIOS0_E0UC_22_X_IN |
PORT95_FlexCAN_1_RX |
PORT97_SIUL2_EIRQ14 |
PORT99_FlexCAN_7_RX |
PORT100_DSPI_3_dSCLK_IN |
PORT101_LIN_10_LIN10RX |
PORT102_EMIOS0_E0UC_3_G_IN |
PORT103_EMIOS1_E1UC_30_Y_IN |
PORT104_SIUL2_EIRQ15 |
PORT105_FlexCAN_7_RX |
PORT106_EMIOS1_E1UC_31_Y_IN |
PORT107_SPI_0_SS_0 |
PORT109_SPI_0_SCLK_0_IN |
PORT110_SPI_2_SIN_2 |
PORT111_LIN_8_LIN8RX |
PORT112_EMIOS1_E1UC_2_H_IN |
PORT113_EMIOS1_E1UC_3_H_IN |
PORT114_EMIOS1_E1UC_4_H_IN |
PORT115_EMIOS1_E1UC_5_H_IN |
PORT116_EMIOS1_E1UC_6_H_IN |
PORT117_EMIOS1_E1UC_7_H_IN |
PORT118_EMIOS1_E1UC_8_X_IN |
PORT119_EMIOS1_E1UC_9_H_IN |
PORT120_EMIOS1_E1UC_10_H_IN |
PORT123_EMIOS1_E1UC_5_H_IN |
PORT124_EMIOS1_E1UC_25_Y_IN |
PORT125_EMIOS1_E1UC_26_Y_IN |
PORT126_EMIOS1_E1UC_27_Y_IN |
PORT127_EMIOS1_E1UC_17_Y_IN |
PORT136_ADC_0_ADC0_S_16 |
PORT137_ADC_0_ADC0_S_17 |
PORT138_ADC_0_ADC0_S_18 |
PORT139_ADC_0_ADC0_S_19 |
PORT140_ADC_0_ADC0_S_20 |
PORT141_ADC_0_ADC0_S_21 |
PORT142_ADC_0_ADC0_S_22 |
PORT143_ADC_0_ADC0_S_23 |
PORT157_WKPU_WKPU_31 |
PORT252_EMIOS1_E1UC_24_X_OUT |
PORT260_EMIOS1_E1UC_28_Y_OUT |
PORT261_DSPI_0_dCS3 |
PORT262_DSPI_0_dCS2 |
PORT263_DSPI_0_dCS5 */
  (uint16)( SHL_PAD_U16(8) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(13) |
SHL_PAD_U16(15) |
SHL_PAD_U16(1) |
SHL_PAD_U16(3) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(0) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(12) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(9) |
SHL_PAD_U16(11) |
SHL_PAD_U16(13) |
SHL_PAD_U16(15) |
SHL_PAD_U16(1) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(13) |
SHL_PAD_U16(12) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7)
          )
}
,
/*  Mode PORT_INOUT3_MODE: */
{
/* Pads   0 ...  15 : PORT0_EMIOS0_E0UC_13_H_IN_OUT |
PORT4_EMIOS0_E0UC_24_X_IN_OUT |
PORT12_EMIOS0_E0UC_26_Y_IN_OUT |
PORT13_EMIOS0_E0UC_25_Y_IN_OUT |
PORT14_EMIOS0_E0UC_0_X_IN_OUT |
PORT15_EMIOS0_E0UC_1_G_IN_OUT |
PORT16_EMIOS0_E0UC_30_Y_IN_OUT |
PORT17_EMIOS0_E0UC_5_G_IN_OUT |
PORT18_IIC_0_SDA0_IN_OUT |
PORT19_IIC_0_SCL0_IN_OUT |
PORT34_DSPI_1_dSCLK_IN_OUT |
PORT36_EMIOS1_E1UC_31_Y_IN_OUT |
PORT39_EMIOS1_E1UC_29_Y_IN_OUT |
PORT41_EMIOS0_E0UC_7_G_IN_OUT |
PORT44_EMIOS0_E0UC_12_H_IN_OUT |
PORT45_EMIOS0_E0UC_13_H_IN_OUT |
PORT46_EMIOS0_E0UC_14_H_IN_OUT |
PORT47_EMIOS0_E0UC_15_H_IN_OUT |
PORT82_GLITCH_FILTER0_INP |
PORT89_EMIOS0_E0UC_14_H_IN |
PORT95_FlexCAN_4_RX |
PORT97_FlexCAN_5_RX |
PORT99_DSPI_3_dSS |
PORT101_DSPI_3_dSIN |
PORT103_LIN_6_LIN6RX |
PORT104_DSPI_2_dSS |
PORT105_LIN_7_LIN7RX |
PORT106_SPI_0_SIN_0 |
PORT107_SPI_2_SS_2 |
PORT112_DSPI_1_dSIN |
PORT114_DSPI_1_dSCLK_IN |
PORT115_DSPI_1_dSS |
PORT116_IIC_3_SCL3_IN |
PORT117_IIC_3_SDA3_IN |
PORT118_SPI_3_SCLK_3_IN |
PORT119_SPI_3_SS_3 |
PORT123_SPI_0_SS_0 |
PORT124_DSPI_3_dSCLK_IN |
PORT125_DSPI_3_dSS |
PORT126_SPI_0_SCLK_0_IN |
PORT128_EMIOS0_E0UC_28_Y_IN |
PORT129_EMIOS0_E0UC_29_Y_IN |
PORT130_EMIOS0_E0UC_30_Y_IN |
PORT131_EMIOS0_E0UC_31_Y_IN |
PORT132_EMIOS1_E1UC_28_Y_IN |
PORT133_EMIOS1_E1UC_29_Y_IN |
PORT134_EMIOS1_E1UC_30_Y_IN |
PORT135_EMIOS1_E1UC_31_Y_IN |
PORT139_DSPI_3_dSIN |
PORT140_DSPI_2_dSS |
PORT142_SPI_0_SIN_0 |
PORT143_SPI_0_SS_0 |
PORT144_ADC_0_ADC0_S_24 |
PORT145_ADC_0_ADC0_S_25 |
PORT146_ADC_0_ADC0_S_26 |
PORT147_ADC_0_ADC0_S_27 |
PORT149_ADC_0_ADC0_S_28 |
PORT150_ADC_0_ADC0_S_29 |
PORT151_ADC_0_ADC0_S_30 |
PORT152_ADC_0_ADC0_S_31 |
PORT261_EMIOS1_E1UC_27_Y_OUT |
PORT262_EMIOS1_E1UC_26_Y_OUT |
PORT263_EMIOS1_E1UC_25_Y_OUT */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(4) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(2) |
SHL_PAD_U16(4) |
SHL_PAD_U16(7) |
SHL_PAD_U16(9) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(2) |
SHL_PAD_U16(9) |
SHL_PAD_U16(15) |
SHL_PAD_U16(1) |
SHL_PAD_U16(3) |
SHL_PAD_U16(5) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(0) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7)
          )
}
,
/*  Mode PORT_INOUT4_MODE: */
{
/* Pads   0 ...  15 : PORT14_EMIOS0_E0UC_23_X_IN_OUT |
PORT15_EMIOS0_E0UC_21_Y_IN_OUT |
PORT18_EMIOS0_E0UC_30_Y_IN_OUT |
PORT19_EMIOS0_E0UC_8_X_IN_OUT |
PORT38_EMIOS1_E1UC_28_Y_IN_OUT |
PORT40_EMIOS0_E0UC_3_G_IN_OUT |
PORT43_EMIOS0_E0UC_1_G_IN_OUT |
PORT46_DSPI_2_dSCLK_IN_OUT |
PORT95_ENET0_MII_RMII_0_RX_DV |
PORT97_ENET0_MII_RMII_0_TX_CLK_IN |
PORT101_EMIOS0_E0UC_2_G_IN |
PORT103_GLITCH_FILTER3_INP |
PORT105_DSPI_2_dSCLK_IN |
PORT106_GLITCH_FILTER3_INP |
PORT117_SPI_3_SIN_3 |
PORT126_FCCU_EIN_ERR |
PORT128_IIC_1_SDA1_IN |
PORT129_LIN_8_LIN8RX |
PORT130_IIC_2_SDA2_IN |
PORT131_LIN_9_LIN9RX |
PORT132_GLITCH_FILTER2_INP |
PORT133_SPI_0_SCLK_0_IN |
PORT134_SPI_0_SS_0 |
PORT135_GLITCH_FILTER3_INP |
PORT139_ENET0_ENET0_TMR1_IN |
PORT140_DSPI_3_dSS |
PORT142_SAI2_SAI2_D0_IN |
PORT143_SAI2_SAI2_MCLK_IN |
PORT144_SAI2_SAI2_SYNC_IN |
PORT145_SPI_1_SIN_1 |
PORT146_SPI_1_SS_1 |
PORT147_SAI1_SAI1_BCLK_IN |
PORT148_EMIOS1_E1UC_18_Y_IN |
PORT149_SAI2_SAI2_D0_IN |
PORT150_SAI2_SAI2_BCLK_IN |
PORT151_SAI2_SAI2_MCLK_IN |
PORT152_SAI2_SAI2_SYNC_IN |
PORT153_EMIOS1_E1UC_17_Y_IN |
PORT154_EMIOS1_E1UC_16_X_IN |
PORT155_EMIOS1_E1UC_11_H_IN |
PORT156_EMIOS1_E1UC_10_H_IN |
PORT157_EMIOS1_E1UC_15_H_IN |
PORT158_EMIOS1_E1UC_14_H_IN |
PORT159_EMIOS1_E1UC_13_H_IN */
  (uint16)( SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(6) |
SHL_PAD_U16(8) |
SHL_PAD_U16(11) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(1) |
SHL_PAD_U16(5) |
SHL_PAD_U16(7) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(5) |
SHL_PAD_U16(14) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15)
          )
}
,
/*  Mode PORT_INOUT5_MODE: */
{
/* Pads   0 ...  15 : PORT16_EMIOS0_E0UC_4_G_IN_OUT |
PORT26_SAI0_SAI0_SYNC_IN_OUT |
PORT38_EMIOS0_E0UC_17_Y_IN_OUT |
PORT39_EMIOS0_E0UC_18_Y_IN_OUT |
PORT60_EMIOS0_E0UC_24_X_IN_OUT |
PORT61_EMIOS0_E0UC_25_Y_IN_OUT |
PORT62_EMIOS0_E0UC_26_Y_IN_OUT |
PORT63_EMIOS0_E0UC_27_Y_IN_OUT |
PORT64_EMIOS0_E0UC_16_X_IN_OUT |
PORT65_EMIOS0_E0UC_17_Y_IN_OUT |
PORT66_EMIOS0_E0UC_18_Y_IN_OUT |
PORT67_EMIOS0_E0UC_19_Y_IN_OUT |
PORT68_EMIOS0_E0UC_20_Y_IN_OUT |
PORT69_EMIOS0_E0UC_21_Y_IN_OUT |
PORT70_EMIOS0_E0UC_22_X_IN_OUT |
PORT71_EMIOS0_E0UC_23_X_IN_OUT |
PORT73_EMIOS0_E0UC_23_X_IN_OUT |
PORT75_EMIOS0_E0UC_24_X_IN_OUT |
PORT76_EMIOS1_E1UC_19_Y_IN_OUT |
PORT78_DSPI_2_dSCLK_IN_OUT |
PORT105_EMIOS0_E0UC_0_X_IN |
PORT128_GLITCH_FILTER0_INP |
PORT129_IIC_1_SCL1_IN |
PORT130_GLITCH_FILTER1_INP |
PORT131_IIC_2_SCL2_IN |
PORT133_GLITCH_FILTER2_INP |
PORT134_SPI_1_SS_1 |
PORT145_SAI2_SAI2_BCLK_IN |
PORT146_SPI_2_SS_2 |
PORT148_SPI_1_SCLK_1_IN |
PORT154_FlexCAN_4_RX |
PORT156_FlexCAN_2_RX |
PORT157_FlexCAN_1_RX |
PORT159_FlexCAN_1_RX |
PORT160_EMIOS1_E1UC_12_H_IN |
PORT161_EMIOS1_E1UC_1_H_IN |
PORT162_EMIOS1_E1UC_2_H_IN |
PORT163_EMIOS1_E1UC_0_X_IN |
PORT164_EMIOS1_E1UC_1_H_IN |
PORT165_EMIOS1_E1UC_4_H_IN |
PORT166_EMIOS1_E1UC_5_H_IN |
PORT167_EMIOS1_E1UC_6_H_IN |
PORT168_EMIOS1_E1UC_7_H_IN |
PORT169_EMIOS1_E1UC_29_Y_IN |
PORT170_EMIOS1_E1UC_30_Y_IN |
PORT171_EMIOS1_E1UC_31_Y_IN |
PORT172_EMIOS0_E0UC_0_X_IN |
PORT173_EMIOS0_E0UC_1_G_IN |
PORT174_EMIOS0_E0UC_2_G_IN |
PORT175_EMIOS0_E0UC_3_G_IN |
PORT177_ADC_0_ADC0_S_47 |
PORT206_DCI_TMS_ALT_IN */
  (uint16)( SHL_PAD_U16(0) |
SHL_PAD_U16(10) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(9) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(14) |
SHL_PAD_U16(9) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(4) |
SHL_PAD_U16(10) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(15) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(1) |
SHL_PAD_U16(14)
          )
}
,
/*  Mode PORT_INOUT6_MODE: */
{
/* Pads   0 ...  15 : PORT26_EMIOS0_E0UC_29_Y_IN_OUT |
PORT61_ENET0_ENET0_TMR0_IN_OUT |
PORT64_IIC_1_SCL1_IN_OUT |
PORT68_DSPI_1_dSCLK_IN_OUT |
PORT72_EMIOS0_E0UC_22_X_IN_OUT |
PORT73_IIC_2_SCL2_IN_OUT |
PORT77_EMIOS1_E1UC_20_Y_IN_OUT |
PORT78_EMIOS1_E1UC_21_Y_IN_OUT |
PORT79_EMIOS1_E1UC_22_X_IN_OUT |
PORT80_EMIOS0_E0UC_10_H_IN_OUT |
PORT81_EMIOS0_E0UC_11_H_IN_OUT |
PORT82_EMIOS0_E0UC_12_H_IN_OUT |
PORT83_EMIOS0_E0UC_13_H_IN_OUT |
PORT84_EMIOS0_E0UC_14_H_IN_OUT |
PORT85_EMIOS0_E0UC_22_X_IN_OUT |
PORT86_EMIOS0_E0UC_23_X_IN_OUT |
PORT87_SPI_0_SCLK_0_IN_OUT |
PORT89_EMIOS1_E1UC_1_H_IN_OUT |
PORT92_EMIOS1_E1UC_25_Y_IN_OUT |
PORT93_EMIOS1_E1UC_26_Y_IN_OUT |
PORT95_EMIOS1_E1UC_4_H_IN_OUT |
PORT129_GLITCH_FILTER0_INP |
PORT131_GLITCH_FILTER1_INP |
PORT134_SPI_2_SS_2 |
PORT146_SPI_3_SS_3 |
PORT148_FCCU_EIN_ERR |
PORT157_FlexCAN_4_RX |
PORT159_FlexCAN_3_RX |
PORT161_FlexCAN_4_RX |
PORT163_EMIOS1_E1UC_3_H_IN |
PORT164_EMIOS0_E0UC_9_H_IN |
PORT165_FlexCAN_2_RX |
PORT166_EMIOS0_E0UC_11_H_IN |
PORT167_FlexCAN_3_RX |
PORT168_EMIOS0_E0UC_13_H_IN |
PORT169_LIN_15_LIN15RX |
PORT170_GLITCH_FILTER3_INP |
PORT171_SPI_0_SCLK_0_IN |
PORT172_LIN_14_LIN14RX |
PORT173_FlexCAN_3_RX |
PORT174_SPI_1_SS_1 |
PORT175_SPI_1_SIN_1 |
PORT176_EMIOS0_E0UC_4_G_IN |
PORT177_SAI0_SAI0_D0_IN |
PORT195_ADC_0_ADC0_S_46 |
PORT196_ADC_0_ADC0_S_45 |
PORT197_ADC_0_ADC0_S_44 |
PORT206_ADC_1_ADC1_S_15 */
  (uint16)( SHL_PAD_U16(10) |
SHL_PAD_U16(13) |
SHL_PAD_U16(0) |
SHL_PAD_U16(4) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(9) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(15) |
SHL_PAD_U16(1) |
SHL_PAD_U16(3) |
SHL_PAD_U16(6) |
SHL_PAD_U16(2) |
SHL_PAD_U16(4) |
SHL_PAD_U16(13) |
SHL_PAD_U16(15) |
SHL_PAD_U16(1) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(0) |
SHL_PAD_U16(1) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(14)
          )
}
,
/*  Mode PORT_INOUT7_MODE: */
{
/* Pads   0 ...  15 : PORT65_IIC_1_SDA1_IN_OUT |
PORT74_EMIOS1_E1UC_30_Y_IN_OUT |
PORT79_SPI_2_SCLK_2_IN_OUT |
PORT91_EMIOS1_E1UC_3_H_IN_OUT |
PORT93_EMIOS0_E0UC_22_X_IN_OUT |
PORT94_EMIOS1_E1UC_27_Y_IN_OUT |
PORT97_EMIOS1_E1UC_24_X_IN_OUT |
PORT98_EMIOS1_E1UC_11_H_IN_OUT |
PORT99_EMIOS1_E1UC_12_H_IN_OUT |
PORT100_EMIOS1_E1UC_13_H_IN_OUT |
PORT101_EMIOS1_E1UC_14_H_IN_OUT |
PORT102_EMIOS1_E1UC_15_H_IN_OUT |
PORT103_EMIOS1_E1UC_16_X_IN_OUT |
PORT104_EMIOS1_E1UC_17_Y_IN_OUT |
PORT105_EMIOS1_E1UC_18_Y_IN_OUT |
PORT106_EMIOS0_E0UC_24_X_IN_OUT |
PORT107_EMIOS0_E0UC_25_Y_IN_OUT |
PORT108_EMIOS0_E0UC_26_Y_IN_OUT |
PORT109_EMIOS0_E0UC_27_Y_IN_OUT |
PORT110_EMIOS1_E1UC_0_X_IN_OUT |
PORT111_EMIOS1_E1UC_1_H_IN_OUT |
PORT134_GLITCH_FILTER3_INP |
PORT146_SAI1_SAI1_D0_IN |
PORT157_FlexCAN_6_RX |
PORT161_EMIOS0_E0UC_6_G_IN |
PORT163_SIUL2_EIRQ31 |
PORT165_LIN_2_LIN2RX |
PORT167_LIN_3_LIN3RX |
PORT169_SPI_0_SIN_0 |
PORT171_GLITCH_FILTER3_INP |
PORT172_SPI_0_SS_0 |
PORT173_SPI_1_SCLK_1_IN |
PORT175_SPI_3_SIN_3 |
PORT176_LIN_13_LIN13RX |
PORT195_SAI0_SAI0_D1_IN |
PORT196_SAI0_SAI0_D2_IN |
PORT197_SAI0_SAI0_D3_IN |
PORT206_SAI0_SAI0_MCLK_IN */
  (uint16)( SHL_PAD_U16(1) |
SHL_PAD_U16(10) |
SHL_PAD_U16(15) |
SHL_PAD_U16(11) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(1) |
SHL_PAD_U16(2) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(6) |
SHL_PAD_U16(7) |
SHL_PAD_U16(8) |
SHL_PAD_U16(9) |
SHL_PAD_U16(10) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(14) |
SHL_PAD_U16(15) |
SHL_PAD_U16(6) |
SHL_PAD_U16(2) |
SHL_PAD_U16(13) |
SHL_PAD_U16(1) |
SHL_PAD_U16(3) |
SHL_PAD_U16(5) |
SHL_PAD_U16(7) |
SHL_PAD_U16(9) |
SHL_PAD_U16(11) |
SHL_PAD_U16(12) |
SHL_PAD_U16(13) |
SHL_PAD_U16(15) |
SHL_PAD_U16(0) |
SHL_PAD_U16(3) |
SHL_PAD_U16(4) |
SHL_PAD_U16(5) |
SHL_PAD_U16(14)
          )
}

[!ENDVAR!]




[!VAR "INOUT_SETTINGS_1"!]
  /* Inout settings for pad PORT0:      {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_0_X_IN_OUT input func */
  {0U, 17U, 0U, 2U}, 
  /* EMIOS0_E0UC_13_H_IN_OUT input func */
  {0U, 19U, 13U, 2U}, 
  /* Inout settings for pad PORT1:      {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_1_G_IN_OUT input func */
  {1U, 17U, 1U, 2U}, 
  /* Inout settings for pad PORT2:      {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_2_G_IN_OUT input func */
  {2U, 17U, 2U, 2U}, 
  /* Inout settings for pad PORT3:      {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_3_G_IN_OUT input func */
  {3U, 17U, 3U, 2U}, 
  /* Inout settings for pad PORT4:      {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_4_G_IN_OUT input func */
  {4U, 17U, 4U, 2U}, 
  /* EMIOS0_E0UC_24_X_IN_OUT input func */
  {4U, 19U, 24U, 5U}, 
  /* Inout settings for pad PORT5:      {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_5_G_IN_OUT input func */
  {5U, 17U, 5U, 2U}, 
  /* Inout settings for pad PORT6:      {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_6_G_IN_OUT input func */
  {6U, 17U, 6U, 2U}, 
  /* Inout settings for pad PORT7:      {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_7_G_IN_OUT input func */
  {7U, 17U, 7U, 2U}, 
  /* Inout settings for pad PORT8:      {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_8_X_IN_OUT input func */
  {8U, 17U, 8U, 2U}, 
  /* EMIOS0_E0UC_14_H_IN_OUT input func */
  {8U, 18U, 14U, 2U}, 
  /* Inout settings for pad PORT9:      {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_9_H_IN_OUT input func */
  {9U, 17U, 9U, 2U}, 
  /* Inout settings for pad PORT10:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_10_H_IN_OUT input func */
  {10U, 17U, 10U, 2U}, 
  /* IIC_0_SDA0_IN_OUT input func */
  {10U, 18U, 266U, 1U}, 
  /* Inout settings for pad PORT11:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_11_H_IN_OUT input func */
  {11U, 17U, 11U, 2U}, 
  /* IIC_0_SCL0_IN_OUT input func */
  {11U, 18U, 265U, 1U}, 
  /* Inout settings for pad PORT12:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_28_Y_IN_OUT input func */
  {12U, 17U, 28U, 2U}, 
  /* EMIOS0_E0UC_26_Y_IN_OUT input func */
  {12U, 19U, 26U, 4U}, 
  /* Inout settings for pad PORT13:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_29_Y_IN_OUT input func */
  {13U, 18U, 29U, 2U}, 
  /* EMIOS0_E0UC_25_Y_IN_OUT input func */
  {13U, 19U, 25U, 4U}, 
  /* Inout settings for pad PORT14:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* DSPI_0_dSCLK_IN_OUT input func */
  {14U, 17U, 289U, 1U}, 
  /* EMIOS0_E0UC_0_X_IN_OUT input func */
  {14U, 19U, 0U, 3U}, 
  /* EMIOS0_E0UC_23_X_IN_OUT input func */
  {14U, 20U, 23U, 5U}, 
  /* Inout settings for pad PORT15:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* DSPI_0_dSCLK_IN_OUT input func */
  {15U, 18U, 289U, 2U}, 
  /* EMIOS0_E0UC_1_G_IN_OUT input func */
  {15U, 19U, 1U, 3U}, 
  /* EMIOS0_E0UC_21_Y_IN_OUT input func */
  {15U, 20U, 21U, 3U}, 
  /* Inout settings for pad PORT16:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_30_Y_IN_OUT input func */
  {16U, 18U, 30U, 2U}, 
  /* EMIOS0_E0UC_4_G_IN_OUT input func */
  {16U, 20U, 4U, 5U}, 
  /* Inout settings for pad PORT17:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_31_Y_IN_OUT input func */
  {17U, 17U, 31U, 2U}, 
  /* EMIOS0_E0UC_5_G_IN_OUT input func */
  {17U, 18U, 5U, 4U}, 
  /* Inout settings for pad PORT26:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SAI0_SAI0_SYNC_IN_OUT input func */
  {26U, 20U, 490U, 1U}, 
  /* EMIOS0_E0UC_29_Y_IN_OUT input func */
  {26U, 21U, 29U, 4U}, 
  /* Inout settings for pad PORT43:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_1_G_IN_OUT input func */
  {43U, 18U, 1U, 5U}, 
  /* Inout settings for pad PORT61:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_25_Y_IN_OUT input func */
  {61U, 18U, 25U, 2U}, 
  /* ENET0_ENET0_TMR0_IN_OUT input func */
  {61U, 19U, 329U, 1U}, 
  /* Inout settings for pad PORT66:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_18_Y_IN_OUT input func */
  {66U, 17U, 18U, 2U}, 
  /* Inout settings for pad PORT67:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_19_Y_IN_OUT input func */
  {67U, 17U, 19U, 2U}, 
  /* Inout settings for pad PORT72:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_22_X_IN_OUT input func */
  {72U, 18U, 22U, 3U}, 
  /* IIC_2_SDA2_IN_OUT input func */
  {72U, 20U, 270U, 1U}, 
  /* Inout settings for pad PORT73:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_23_X_IN_OUT input func */
  {73U, 17U, 23U, 3U}, 
  /* IIC_2_SCL2_IN_OUT input func */
  {73U, 18U, 269U, 1U}, 
  /* Inout settings for pad PORT77:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_20_Y_IN_OUT input func */
  {77U, 18U, 56U, 2U}, 
  /* Inout settings for pad PORT79:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_22_X_IN_OUT input func */
  {79U, 18U, 58U, 2U}, 
  /* SPI_2_SCLK_2_IN_OUT input func */
  {79U, 19U, 307U, 1U}, 
  /* Inout settings for pad PORT80:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_10_H_IN_OUT input func */
  {80U, 17U, 10U, 3U}, 
  /* SAI0_SAI0_MCLK_IN_OUT input func */
  {80U, 23U, 489U, 1U}, 
  /* Inout settings for pad PORT85:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_22_X_IN_OUT input func */
  {85U, 17U, 22U, 4U}, 
  /* SAI0_SAI0_D0_IN_OUT input func */
  {85U, 20U, 491U, 1U}, 
  /* Inout settings for pad PORT88:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_15_H_IN_OUT input func */
  {88U, 20U, 15U, 3U}, 
  /* Inout settings for pad PORT89:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_1_H_IN_OUT input func */
  {89U, 17U, 37U, 2U}, 
  /* EMIOS0_E0UC_14_H_IN_OUT input func */
  {89U, 19U, 14U, 5U}, 
  /* Inout settings for pad PORT90:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_2_H_IN_OUT input func */
  {90U, 19U, 38U, 2U}, 
  /* EMIOS0_E0UC_19_Y_IN_OUT input func */
  {90U, 20U, 19U, 3U}, 
  /* FCCU_EOUT0_IN_OUT input func */
  {90U, 21U, 65535U, 0U}, 
  /* Inout settings for pad PORT94:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_27_Y_IN_OUT input func */
  {94U, 18U, 63U, 2U}, 
  /* ENET0_MII_RMII_0_MDIO_IN_OUT input func */
  {94U, 20U, 450U, 1U}, 
  /* Inout settings for pad PORT95:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_4_H_IN_OUT input func */
  {95U, 17U, 40U, 2U}, 
  /* Inout settings for pad PORT96:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_23_X_IN_OUT input func */
  {96U, 18U, 59U, 2U}, 
  /* Inout settings for pad PORT97:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_24_X_IN_OUT input func */
  {97U, 17U, 60U, 2U}, 
  /* ENET0_MII_RMII_0_TX_CLK_IN_OUT input func */
  {97U, 18U, 449U, 1U}, 
  /* Inout settings for pad PORT98:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_11_H_IN_OUT input func */
  {98U, 17U, 47U, 2U}, 
  /* Inout settings for pad PORT99:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_12_H_IN_OUT input func */
  {99U, 17U, 48U, 2U}, 
  /* Inout settings for pad PORT102:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_15_H_IN_OUT input func */
  {102U, 17U, 51U, 2U}, 
  /* EMIOS0_E0UC_3_G_IN_OUT input func */
  {102U, 20U, 3U, 6U}, 
  /* Inout settings for pad PORT103:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_16_X_IN_OUT input func */
  {103U, 17U, 52U, 2U}, 
  /* EMIOS1_E1UC_30_Y_IN_OUT input func */
  {103U, 18U, 66U, 3U}, 
  /* Inout settings for pad PORT107:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_25_Y_IN_OUT input func */
  {107U, 17U, 25U, 3U}, 
  /* Inout settings for pad PORT108:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_26_Y_IN_OUT input func */
  {108U, 17U, 26U, 3U}, 
  /* Inout settings for pad PORT109:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_27_Y_IN_OUT input func */
  {109U, 17U, 27U, 3U}, 
  /* SPI_0_SCLK_0_IN_OUT input func */
  {109U, 18U, 301U, 2U}, 
  /* Inout settings for pad PORT110:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_0_X_IN_OUT input func */
  {110U, 17U, 36U, 2U}, 
  /* Inout settings for pad PORT111:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_1_H_IN_OUT input func */
  {111U, 17U, 37U, 3U}, 
  /* Inout settings for pad PORT112:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_2_H_IN_OUT input func */
  {112U, 17U, 38U, 3U}, 
  /* Inout settings for pad PORT113:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_3_H_IN_OUT input func */
  {113U, 17U, 39U, 3U}, 
  /* Inout settings for pad PORT114:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_4_H_IN_OUT input func */
  {114U, 17U, 40U, 3U}, 
  /* DSPI_1_dSCLK_IN_OUT input func */
  {114U, 18U, 292U, 3U}, 
  /* Inout settings for pad PORT122:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* DCI_TMS_IN_OUT input func */
  {122U, 17U, 65535U, 0U}, 
  /* Inout settings for pad PORT124:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* DSPI_3_dSCLK_IN_OUT input func */
  {124U, 17U, 298U, 2U}, 
  /* EMIOS1_E1UC_25_Y_IN_OUT input func */
  {124U, 19U, 61U, 3U}, 
  /* Inout settings for pad PORT128:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_28_Y_IN_OUT input func */
  {128U, 17U, 28U, 3U}, 
  /* IIC_1_SDA1_IN_OUT input func */
  {128U, 19U, 268U, 2U}, 
  /* Inout settings for pad PORT129:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_29_Y_IN_OUT input func */
  {129U, 17U, 29U, 3U}, 
  /* IIC_1_SCL1_IN_OUT input func */
  {129U, 18U, 267U, 2U}, 
  /* Inout settings for pad PORT130:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_30_Y_IN_OUT input func */
  {130U, 17U, 30U, 4U}, 
  /* IIC_2_SDA2_IN_OUT input func */
  {130U, 19U, 270U, 2U}, 
  /* Inout settings for pad PORT131:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_31_Y_IN_OUT input func */
  {131U, 17U, 31U, 4U}, 
  /* IIC_2_SCL2_IN_OUT input func */
  {131U, 18U, 269U, 2U}, 
  /* Inout settings for pad PORT142:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SAI2_SAI2_D0_IN_OUT input func */
  {142U, 17U, 505U, 2U}, 
  /* Inout settings for pad PORT144:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SAI2_SAI2_SYNC_IN_OUT input func */
  {144U, 19U, 504U, 2U}, 
  /* Inout settings for pad PORT145:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SAI2_SAI2_BCLK_IN_OUT input func */
  {145U, 18U, 502U, 1U}, 
  /* Inout settings for pad PORT146:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SAI1_SAI1_D0_IN_OUT input func */
  {146U, 20U, 498U, 1U}, 
  /* Inout settings for pad PORT157:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_15_H_IN_OUT input func */
  {157U, 19U, 51U, 3U}, 
  /* Inout settings for pad PORT158:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_14_H_IN_OUT input func */
  {158U, 22U, 50U, 3U}
[!ENDVAR!]


[!VAR "SIZE_OF_INOUT_SETTINGS_1"!][!//
94[!//
[!ENDVAR!]


[!VAR "INOUT_SETTINGS_2"!]
  /* Inout settings for pad PORT0:      {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_0_X_IN_OUT input func */
  {0U, 17U, 0U, 2U}, 
  /* EMIOS0_E0UC_13_H_IN_OUT input func */
  {0U, 19U, 13U, 2U}, 
  /* Inout settings for pad PORT1:      {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_1_G_IN_OUT input func */
  {1U, 17U, 1U, 2U}, 
  /* Inout settings for pad PORT2:      {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_2_G_IN_OUT input func */
  {2U, 17U, 2U, 2U}, 
  /* Inout settings for pad PORT3:      {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_3_G_IN_OUT input func */
  {3U, 17U, 3U, 2U}, 
  /* Inout settings for pad PORT4:      {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_4_G_IN_OUT input func */
  {4U, 17U, 4U, 2U}, 
  /* EMIOS0_E0UC_24_X_IN_OUT input func */
  {4U, 19U, 24U, 5U}, 
  /* Inout settings for pad PORT5:      {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_5_G_IN_OUT input func */
  {5U, 17U, 5U, 2U}, 
  /* Inout settings for pad PORT6:      {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_6_G_IN_OUT input func */
  {6U, 17U, 6U, 2U}, 
  /* Inout settings for pad PORT7:      {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_7_G_IN_OUT input func */
  {7U, 17U, 7U, 2U}, 
  /* Inout settings for pad PORT8:      {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_8_X_IN_OUT input func */
  {8U, 17U, 8U, 2U}, 
  /* EMIOS0_E0UC_14_H_IN_OUT input func */
  {8U, 18U, 14U, 2U}, 
  /* Inout settings for pad PORT9:      {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_9_H_IN_OUT input func */
  {9U, 17U, 9U, 2U}, 
  /* Inout settings for pad PORT10:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_10_H_IN_OUT input func */
  {10U, 17U, 10U, 2U}, 
  /* IIC_0_SDA0_IN_OUT input func */
  {10U, 18U, 266U, 1U}, 
  /* Inout settings for pad PORT11:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_11_H_IN_OUT input func */
  {11U, 17U, 11U, 2U}, 
  /* IIC_0_SCL0_IN_OUT input func */
  {11U, 18U, 265U, 1U}, 
  /* Inout settings for pad PORT12:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_28_Y_IN_OUT input func */
  {12U, 17U, 28U, 2U}, 
  /* EMIOS0_E0UC_26_Y_IN_OUT input func */
  {12U, 19U, 26U, 4U}, 
  /* Inout settings for pad PORT13:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_29_Y_IN_OUT input func */
  {13U, 18U, 29U, 2U}, 
  /* EMIOS0_E0UC_25_Y_IN_OUT input func */
  {13U, 19U, 25U, 4U}, 
  /* Inout settings for pad PORT14:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* DSPI_0_dSCLK_IN_OUT input func */
  {14U, 17U, 289U, 1U}, 
  /* EMIOS0_E0UC_0_X_IN_OUT input func */
  {14U, 19U, 0U, 3U}, 
  /* EMIOS0_E0UC_23_X_IN_OUT input func */
  {14U, 20U, 23U, 5U}, 
  /* Inout settings for pad PORT15:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* DSPI_0_dSCLK_IN_OUT input func */
  {15U, 18U, 289U, 2U}, 
  /* EMIOS0_E0UC_1_G_IN_OUT input func */
  {15U, 19U, 1U, 3U}, 
  /* EMIOS0_E0UC_21_Y_IN_OUT input func */
  {15U, 20U, 21U, 3U}, 
  /* Inout settings for pad PORT16:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_30_Y_IN_OUT input func */
  {16U, 18U, 30U, 2U}, 
  /* EMIOS0_E0UC_4_G_IN_OUT input func */
  {16U, 20U, 4U, 5U}, 
  /* Inout settings for pad PORT17:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_31_Y_IN_OUT input func */
  {17U, 17U, 31U, 2U}, 
  /* EMIOS0_E0UC_5_G_IN_OUT input func */
  {17U, 18U, 5U, 4U}, 
  /* Inout settings for pad PORT18:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* IIC_0_SDA0_IN_OUT input func */
  {18U, 18U, 266U, 2U}, 
  /* EMIOS0_E0UC_30_Y_IN_OUT input func */
  {18U, 19U, 30U, 3U}, 
  /* Inout settings for pad PORT19:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_31_Y_IN_OUT input func */
  {19U, 17U, 31U, 3U}, 
  /* IIC_0_SCL0_IN_OUT input func */
  {19U, 18U, 265U, 2U}, 
  /* EMIOS0_E0UC_8_X_IN_OUT input func */
  {19U, 19U, 8U, 3U}, 
  /* Inout settings for pad PORT26:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SAI0_SAI0_SYNC_IN_OUT input func */
  {26U, 20U, 490U, 1U}, 
  /* EMIOS0_E0UC_29_Y_IN_OUT input func */
  {26U, 21U, 29U, 4U}, 
  /* Inout settings for pad PORT27:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_3_G_IN_OUT input func */
  {27U, 17U, 3U, 3U}, 
  /* Inout settings for pad PORT28:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_4_G_IN_OUT input func */
  {28U, 17U, 4U, 3U}, 
  /* Inout settings for pad PORT29:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_5_G_IN_OUT input func */
  {29U, 17U, 5U, 3U}, 
  /* Inout settings for pad PORT30:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_6_G_IN_OUT input func */
  {30U, 17U, 6U, 3U}, 
  /* Inout settings for pad PORT31:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_7_G_IN_OUT input func */
  {31U, 17U, 7U, 3U}, 
  /* Inout settings for pad PORT34:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* DSPI_1_dSCLK_IN_OUT input func */
  {34U, 17U, 292U, 1U}, 
  /* Inout settings for pad PORT36:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_31_Y_IN_OUT input func */
  {36U, 17U, 67U, 2U}, 
  /* Inout settings for pad PORT38:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_28_Y_IN_OUT input func */
  {38U, 18U, 64U, 2U}, 
  /* EMIOS0_E0UC_17_Y_IN_OUT input func */
  {38U, 19U, 17U, 3U}, 
  /* Inout settings for pad PORT39:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_29_Y_IN_OUT input func */
  {39U, 17U, 65U, 2U}, 
  /* EMIOS0_E0UC_18_Y_IN_OUT input func */
  {39U, 19U, 18U, 3U}, 
  /* Inout settings for pad PORT40:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_3_G_IN_OUT input func */
  {40U, 18U, 3U, 4U}, 
  /* Inout settings for pad PORT41:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_7_G_IN_OUT input func */
  {41U, 17U, 7U, 4U}, 
  /* Inout settings for pad PORT43:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_1_G_IN_OUT input func */
  {43U, 18U, 1U, 5U}, 
  /* Inout settings for pad PORT44:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_12_H_IN_OUT input func */
  {44U, 17U, 12U, 2U}, 
  /* Inout settings for pad PORT45:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_13_H_IN_OUT input func */
  {45U, 17U, 13U, 3U}, 
  /* Inout settings for pad PORT46:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_14_H_IN_OUT input func */
  {46U, 17U, 14U, 3U}, 
  /* DSPI_2_dSCLK_IN_OUT input func */
  {46U, 18U, 295U, 1U}, 
  /* Inout settings for pad PORT47:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_15_H_IN_OUT input func */
  {47U, 17U, 15U, 2U}, 
  /* Inout settings for pad PORT60:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_24_X_IN_OUT input func */
  {60U, 18U, 24U, 2U}, 
  /* Inout settings for pad PORT61:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_25_Y_IN_OUT input func */
  {61U, 18U, 25U, 2U}, 
  /* ENET0_ENET0_TMR0_IN_OUT input func */
  {61U, 19U, 329U, 1U}, 
  /* Inout settings for pad PORT62:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_26_Y_IN_OUT input func */
  {62U, 18U, 26U, 2U}, 
  /* Inout settings for pad PORT63:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_27_Y_IN_OUT input func */
  {63U, 18U, 27U, 2U}, 
  /* Inout settings for pad PORT64:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_16_X_IN_OUT input func */
  {64U, 17U, 16U, 2U}, 
  /* IIC_1_SCL1_IN_OUT input func */
  {64U, 18U, 267U, 1U}, 
  /* Inout settings for pad PORT65:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_17_Y_IN_OUT input func */
  {65U, 17U, 17U, 2U}, 
  /* IIC_1_SDA1_IN_OUT input func */
  {65U, 19U, 268U, 1U}, 
  /* Inout settings for pad PORT66:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_18_Y_IN_OUT input func */
  {66U, 17U, 18U, 2U}, 
  /* Inout settings for pad PORT67:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_19_Y_IN_OUT input func */
  {67U, 17U, 19U, 2U}, 
  /* Inout settings for pad PORT68:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_20_Y_IN_OUT input func */
  {68U, 17U, 20U, 2U}, 
  /* DSPI_1_dSCLK_IN_OUT input func */
  {68U, 18U, 292U, 2U}, 
  /* Inout settings for pad PORT69:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_21_Y_IN_OUT input func */
  {69U, 17U, 21U, 2U}, 
  /* Inout settings for pad PORT70:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_22_X_IN_OUT input func */
  {70U, 17U, 22U, 2U}, 
  /* Inout settings for pad PORT71:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_23_X_IN_OUT input func */
  {71U, 17U, 23U, 2U}, 
  /* Inout settings for pad PORT72:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_22_X_IN_OUT input func */
  {72U, 18U, 22U, 3U}, 
  /* IIC_2_SDA2_IN_OUT input func */
  {72U, 20U, 270U, 1U}, 
  /* Inout settings for pad PORT73:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_23_X_IN_OUT input func */
  {73U, 17U, 23U, 3U}, 
  /* IIC_2_SCL2_IN_OUT input func */
  {73U, 18U, 269U, 1U}, 
  /* Inout settings for pad PORT74:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_30_Y_IN_OUT input func */
  {74U, 19U, 66U, 2U}, 
  /* IIC_3_SDA3_IN_OUT input func */
  {74U, 20U, 272U, 1U}, 
  /* Inout settings for pad PORT75:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_24_X_IN_OUT input func */
  {75U, 17U, 24U, 3U}, 
  /* IIC_3_SCL3_IN_OUT input func */
  {75U, 20U, 271U, 1U}, 
  /* Inout settings for pad PORT76:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_19_Y_IN_OUT input func */
  {76U, 17U, 55U, 2U}, 
  /* Inout settings for pad PORT77:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_20_Y_IN_OUT input func */
  {77U, 18U, 56U, 2U}, 
  /* Inout settings for pad PORT78:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* DSPI_2_dSCLK_IN_OUT input func */
  {78U, 17U, 295U, 2U}, 
  /* EMIOS1_E1UC_21_Y_IN_OUT input func */
  {78U, 18U, 57U, 2U}, 
  /* Inout settings for pad PORT79:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_22_X_IN_OUT input func */
  {79U, 18U, 58U, 2U}, 
  /* SPI_2_SCLK_2_IN_OUT input func */
  {79U, 19U, 307U, 1U}, 
  /* Inout settings for pad PORT80:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_10_H_IN_OUT input func */
  {80U, 17U, 10U, 3U}, 
  /* SAI0_SAI0_MCLK_IN_OUT input func */
  {80U, 23U, 489U, 1U}, 
  /* Inout settings for pad PORT81:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_11_H_IN_OUT input func */
  {81U, 17U, 11U, 3U}, 
  /* SAI0_SAI0_BCLK_IN_OUT input func */
  {81U, 20U, 488U, 1U}, 
  /* Inout settings for pad PORT82:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_12_H_IN_OUT input func */
  {82U, 17U, 12U, 3U}, 
  /* SAI0_SAI0_D3_IN_OUT input func */
  {82U, 20U, 494U, 1U}, 
  /* Inout settings for pad PORT83:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_13_H_IN_OUT input func */
  {83U, 17U, 13U, 4U}, 
  /* SAI0_SAI0_D2_IN_OUT input func */
  {83U, 20U, 493U, 1U}, 
  /* Inout settings for pad PORT84:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_14_H_IN_OUT input func */
  {84U, 17U, 14U, 4U}, 
  /* SAI0_SAI0_D1_IN_OUT input func */
  {84U, 20U, 492U, 1U}, 
  /* Inout settings for pad PORT85:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_22_X_IN_OUT input func */
  {85U, 17U, 22U, 4U}, 
  /* SAI0_SAI0_D0_IN_OUT input func */
  {85U, 20U, 491U, 1U}, 
  /* Inout settings for pad PORT86:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_23_X_IN_OUT input func */
  {86U, 17U, 23U, 4U}, 
  /* SAI1_SAI1_SYNC_IN_OUT input func */
  {86U, 20U, 497U, 1U}, 
  /* EMIOS0_E0UC_30_Y_IN_OUT input func */
  {86U, 21U, 30U, 5U}, 
  /* Inout settings for pad PORT87:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SPI_0_SCLK_0_IN_OUT input func */
  {87U, 17U, 301U, 1U}, 
  /* SAI1_SAI1_MCLK_IN_OUT input func */
  {87U, 22U, 496U, 1U}, 
  /* Inout settings for pad PORT88:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_15_H_IN_OUT input func */
  {88U, 20U, 15U, 3U}, 
  /* Inout settings for pad PORT89:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_1_H_IN_OUT input func */
  {89U, 17U, 37U, 2U}, 
  /* EMIOS0_E0UC_14_H_IN_OUT input func */
  {89U, 19U, 14U, 5U}, 
  /* Inout settings for pad PORT90:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_2_H_IN_OUT input func */
  {90U, 19U, 38U, 2U}, 
  /* EMIOS0_E0UC_19_Y_IN_OUT input func */
  {90U, 20U, 19U, 3U}, 
  /* FCCU_EOUT0_IN_OUT input func */
  {90U, 21U, 65535U, 0U}, 
  /* Inout settings for pad PORT91:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_3_H_IN_OUT input func */
  {91U, 18U, 39U, 2U}, 
  /* EMIOS0_E0UC_20_Y_IN_OUT input func */
  {91U, 19U, 20U, 3U}, 
  /* Inout settings for pad PORT92:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_25_Y_IN_OUT input func */
  {92U, 17U, 61U, 2U}, 
  /* EMIOS0_E0UC_16_X_IN_OUT input func */
  {92U, 19U, 16U, 3U}, 
  /* FCCU_EOUT1_IN_OUT input func */
  {92U, 20U, 65535U, 0U}, 
  /* Inout settings for pad PORT93:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_26_Y_IN_OUT input func */
  {93U, 17U, 62U, 2U}, 
  /* EMIOS0_E0UC_22_X_IN_OUT input func */
  {93U, 18U, 22U, 5U}, 
  /* Inout settings for pad PORT94:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_27_Y_IN_OUT input func */
  {94U, 18U, 63U, 2U}, 
  /* ENET0_MII_RMII_0_MDIO_IN_OUT input func */
  {94U, 20U, 450U, 1U}, 
  /* Inout settings for pad PORT95:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_4_H_IN_OUT input func */
  {95U, 17U, 40U, 2U}, 
  /* Inout settings for pad PORT96:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_23_X_IN_OUT input func */
  {96U, 18U, 59U, 2U}, 
  /* Inout settings for pad PORT97:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_24_X_IN_OUT input func */
  {97U, 17U, 60U, 2U}, 
  /* ENET0_MII_RMII_0_TX_CLK_IN_OUT input func */
  {97U, 18U, 449U, 1U}, 
  /* Inout settings for pad PORT98:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_11_H_IN_OUT input func */
  {98U, 17U, 47U, 2U}, 
  /* Inout settings for pad PORT99:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_12_H_IN_OUT input func */
  {99U, 17U, 48U, 2U}, 
  /* Inout settings for pad PORT100:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_13_H_IN_OUT input func */
  {100U, 17U, 49U, 2U}, 
  /* DSPI_3_dSCLK_IN_OUT input func */
  {100U, 18U, 298U, 1U}, 
  /* Inout settings for pad PORT101:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_14_H_IN_OUT input func */
  {101U, 17U, 50U, 2U}, 
  /* EMIOS0_E0UC_2_G_IN_OUT input func */
  {101U, 18U, 2U, 4U}, 
  /* Inout settings for pad PORT102:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_15_H_IN_OUT input func */
  {102U, 17U, 51U, 2U}, 
  /* EMIOS0_E0UC_3_G_IN_OUT input func */
  {102U, 20U, 3U, 6U}, 
  /* Inout settings for pad PORT103:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_16_X_IN_OUT input func */
  {103U, 17U, 52U, 2U}, 
  /* EMIOS1_E1UC_30_Y_IN_OUT input func */
  {103U, 18U, 66U, 3U}, 
  /* Inout settings for pad PORT104:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_17_Y_IN_OUT input func */
  {104U, 17U, 53U, 2U}, 
  /* Inout settings for pad PORT105:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_18_Y_IN_OUT input func */
  {105U, 17U, 54U, 2U}, 
  /* DSPI_2_dSCLK_IN_OUT input func */
  {105U, 18U, 295U, 3U}, 
  /* EMIOS0_E0UC_0_X_IN_OUT input func */
  {105U, 19U, 0U, 5U}, 
  /* Inout settings for pad PORT106:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_24_X_IN_OUT input func */
  {106U, 17U, 24U, 4U}, 
  /* EMIOS1_E1UC_31_Y_IN_OUT input func */
  {106U, 18U, 67U, 3U}, 
  /* Inout settings for pad PORT107:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_25_Y_IN_OUT input func */
  {107U, 17U, 25U, 3U}, 
  /* Inout settings for pad PORT108:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_26_Y_IN_OUT input func */
  {108U, 17U, 26U, 3U}, 
  /* Inout settings for pad PORT109:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_27_Y_IN_OUT input func */
  {109U, 17U, 27U, 3U}, 
  /* SPI_0_SCLK_0_IN_OUT input func */
  {109U, 18U, 301U, 2U}, 
  /* Inout settings for pad PORT110:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_0_X_IN_OUT input func */
  {110U, 17U, 36U, 2U}, 
  /* Inout settings for pad PORT111:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_1_H_IN_OUT input func */
  {111U, 17U, 37U, 3U}, 
  /* Inout settings for pad PORT112:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_2_H_IN_OUT input func */
  {112U, 17U, 38U, 3U}, 
  /* Inout settings for pad PORT113:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_3_H_IN_OUT input func */
  {113U, 17U, 39U, 3U}, 
  /* Inout settings for pad PORT114:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_4_H_IN_OUT input func */
  {114U, 17U, 40U, 3U}, 
  /* DSPI_1_dSCLK_IN_OUT input func */
  {114U, 18U, 292U, 3U}, 
  /* Inout settings for pad PORT115:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_5_H_IN_OUT input func */
  {115U, 17U, 41U, 2U}, 
  /* Inout settings for pad PORT116:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_6_H_IN_OUT input func */
  {116U, 17U, 42U, 2U}, 
  /* IIC_3_SCL3_IN_OUT input func */
  {116U, 19U, 271U, 2U}, 
  /* Inout settings for pad PORT117:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_7_H_IN_OUT input func */
  {117U, 17U, 43U, 2U}, 
  /* IIC_3_SDA3_IN_OUT input func */
  {117U, 18U, 272U, 2U}, 
  /* Inout settings for pad PORT118:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_8_X_IN_OUT input func */
  {118U, 17U, 44U, 2U}, 
  /* SPI_3_SCLK_3_IN_OUT input func */
  {118U, 18U, 310U, 1U}, 
  /* Inout settings for pad PORT119:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_9_H_IN_OUT input func */
  {119U, 17U, 45U, 2U}, 
  /* Inout settings for pad PORT120:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_10_H_IN_OUT input func */
  {120U, 17U, 46U, 2U}, 
  /* Inout settings for pad PORT122:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* DCI_TMS_IN_OUT input func */
  {122U, 17U, 65535U, 0U}, 
  /* Inout settings for pad PORT123:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_5_H_IN_OUT input func */
  {123U, 19U, 41U, 3U}, 
  /* Inout settings for pad PORT124:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* DSPI_3_dSCLK_IN_OUT input func */
  {124U, 17U, 298U, 2U}, 
  /* EMIOS1_E1UC_25_Y_IN_OUT input func */
  {124U, 19U, 61U, 3U}, 
  /* Inout settings for pad PORT125:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_26_Y_IN_OUT input func */
  {125U, 19U, 62U, 3U}, 
  /* FCCU_EOUT1_IN_OUT input func */
  {125U, 20U, 65535U, 0U}, 
  /* Inout settings for pad PORT126:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SPI_0_SCLK_0_IN_OUT input func */
  {126U, 17U, 301U, 3U}, 
  /* EMIOS1_E1UC_27_Y_IN_OUT input func */
  {126U, 19U, 63U, 3U}, 
  /* Inout settings for pad PORT127:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_17_Y_IN_OUT input func */
  {127U, 19U, 53U, 3U}, 
  /* FCCU_EOUT0_IN_OUT input func */
  {127U, 20U, 65535U, 0U}, 
  /* Inout settings for pad PORT128:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_28_Y_IN_OUT input func */
  {128U, 17U, 28U, 3U}, 
  /* IIC_1_SDA1_IN_OUT input func */
  {128U, 19U, 268U, 2U}, 
  /* Inout settings for pad PORT129:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_29_Y_IN_OUT input func */
  {129U, 17U, 29U, 3U}, 
  /* IIC_1_SCL1_IN_OUT input func */
  {129U, 18U, 267U, 2U}, 
  /* Inout settings for pad PORT130:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_30_Y_IN_OUT input func */
  {130U, 17U, 30U, 4U}, 
  /* IIC_2_SDA2_IN_OUT input func */
  {130U, 19U, 270U, 2U}, 
  /* Inout settings for pad PORT131:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_31_Y_IN_OUT input func */
  {131U, 17U, 31U, 4U}, 
  /* IIC_2_SCL2_IN_OUT input func */
  {131U, 18U, 269U, 2U}, 
  /* Inout settings for pad PORT132:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_28_Y_IN_OUT input func */
  {132U, 17U, 64U, 3U}, 
  /* Inout settings for pad PORT133:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_29_Y_IN_OUT input func */
  {133U, 17U, 65U, 3U}, 
  /* SPI_0_SCLK_0_IN_OUT input func */
  {133U, 18U, 301U, 4U}, 
  /* Inout settings for pad PORT134:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_30_Y_IN_OUT input func */
  {134U, 17U, 66U, 4U}, 
  /* Inout settings for pad PORT135:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_31_Y_IN_OUT input func */
  {135U, 17U, 67U, 4U}, 
  /* Inout settings for pad PORT139:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* ENET0_ENET0_TMR1_IN_OUT input func */
  {139U, 18U, 330U, 1U}, 
  /* Inout settings for pad PORT142:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SAI2_SAI2_D0_IN_OUT input func */
  {142U, 17U, 505U, 2U}, 
  /* Inout settings for pad PORT143:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SAI2_SAI2_MCLK_IN_OUT input func */
  {143U, 19U, 503U, 2U}, 
  /* Inout settings for pad PORT144:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SAI2_SAI2_SYNC_IN_OUT input func */
  {144U, 19U, 504U, 2U}, 
  /* Inout settings for pad PORT145:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SAI2_SAI2_BCLK_IN_OUT input func */
  {145U, 18U, 502U, 1U}, 
  /* Inout settings for pad PORT146:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SAI1_SAI1_D0_IN_OUT input func */
  {146U, 20U, 498U, 1U}, 
  /* Inout settings for pad PORT147:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SAI1_SAI1_BCLK_IN_OUT input func */
  {147U, 20U, 495U, 1U}, 
  /* Inout settings for pad PORT148:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SPI_1_SCLK_1_IN_OUT input func */
  {148U, 17U, 304U, 1U}, 
  /* EMIOS1_E1UC_18_Y_IN_OUT input func */
  {148U, 18U, 54U, 3U}
[!ENDVAR!]


[!VAR "SIZE_OF_INOUT_SETTINGS_2"!][!//
190[!//
[!ENDVAR!]


[!VAR "INOUT_SETTINGS_3"!]
  /* Inout settings for pad PORT0:      {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_0_X_IN_OUT input func */
  {0U, 17U, 0U, 2U}, 
  /* EMIOS0_E0UC_13_H_IN_OUT input func */
  {0U, 19U, 13U, 2U}, 
  /* Inout settings for pad PORT1:      {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_1_G_IN_OUT input func */
  {1U, 17U, 1U, 2U}, 
  /* Inout settings for pad PORT2:      {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_2_G_IN_OUT input func */
  {2U, 17U, 2U, 2U}, 
  /* Inout settings for pad PORT3:      {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_3_G_IN_OUT input func */
  {3U, 17U, 3U, 2U}, 
  /* Inout settings for pad PORT4:      {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_4_G_IN_OUT input func */
  {4U, 17U, 4U, 2U}, 
  /* EMIOS0_E0UC_24_X_IN_OUT input func */
  {4U, 19U, 24U, 5U}, 
  /* Inout settings for pad PORT5:      {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_5_G_IN_OUT input func */
  {5U, 17U, 5U, 2U}, 
  /* Inout settings for pad PORT6:      {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_6_G_IN_OUT input func */
  {6U, 17U, 6U, 2U}, 
  /* Inout settings for pad PORT7:      {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_7_G_IN_OUT input func */
  {7U, 17U, 7U, 2U}, 
  /* Inout settings for pad PORT8:      {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_8_X_IN_OUT input func */
  {8U, 17U, 8U, 2U}, 
  /* EMIOS0_E0UC_14_H_IN_OUT input func */
  {8U, 18U, 14U, 2U}, 
  /* Inout settings for pad PORT9:      {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_9_H_IN_OUT input func */
  {9U, 17U, 9U, 2U}, 
  /* Inout settings for pad PORT10:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_10_H_IN_OUT input func */
  {10U, 17U, 10U, 2U}, 
  /* IIC_0_SDA0_IN_OUT input func */
  {10U, 18U, 266U, 1U}, 
  /* Inout settings for pad PORT11:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_11_H_IN_OUT input func */
  {11U, 17U, 11U, 2U}, 
  /* IIC_0_SCL0_IN_OUT input func */
  {11U, 18U, 265U, 1U}, 
  /* Inout settings for pad PORT12:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_28_Y_IN_OUT input func */
  {12U, 17U, 28U, 2U}, 
  /* EMIOS0_E0UC_26_Y_IN_OUT input func */
  {12U, 19U, 26U, 4U}, 
  /* Inout settings for pad PORT13:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_29_Y_IN_OUT input func */
  {13U, 18U, 29U, 2U}, 
  /* EMIOS0_E0UC_25_Y_IN_OUT input func */
  {13U, 19U, 25U, 4U}, 
  /* Inout settings for pad PORT14:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* DSPI_0_dSCLK_IN_OUT input func */
  {14U, 17U, 289U, 1U}, 
  /* EMIOS0_E0UC_0_X_IN_OUT input func */
  {14U, 19U, 0U, 3U}, 
  /* EMIOS0_E0UC_23_X_IN_OUT input func */
  {14U, 20U, 23U, 5U}, 
  /* Inout settings for pad PORT15:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* DSPI_0_dSCLK_IN_OUT input func */
  {15U, 18U, 289U, 2U}, 
  /* EMIOS0_E0UC_1_G_IN_OUT input func */
  {15U, 19U, 1U, 3U}, 
  /* EMIOS0_E0UC_21_Y_IN_OUT input func */
  {15U, 20U, 21U, 3U}, 
  /* Inout settings for pad PORT16:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_30_Y_IN_OUT input func */
  {16U, 18U, 30U, 2U}, 
  /* EMIOS0_E0UC_4_G_IN_OUT input func */
  {16U, 20U, 4U, 5U}, 
  /* Inout settings for pad PORT17:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_31_Y_IN_OUT input func */
  {17U, 17U, 31U, 2U}, 
  /* EMIOS0_E0UC_5_G_IN_OUT input func */
  {17U, 18U, 5U, 4U}, 
  /* Inout settings for pad PORT18:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* IIC_0_SDA0_IN_OUT input func */
  {18U, 18U, 266U, 2U}, 
  /* EMIOS0_E0UC_30_Y_IN_OUT input func */
  {18U, 19U, 30U, 3U}, 
  /* Inout settings for pad PORT19:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_31_Y_IN_OUT input func */
  {19U, 17U, 31U, 3U}, 
  /* IIC_0_SCL0_IN_OUT input func */
  {19U, 18U, 265U, 2U}, 
  /* EMIOS0_E0UC_8_X_IN_OUT input func */
  {19U, 19U, 8U, 3U}, 
  /* Inout settings for pad PORT26:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SAI0_SAI0_SYNC_IN_OUT input func */
  {26U, 20U, 490U, 1U}, 
  /* EMIOS0_E0UC_29_Y_IN_OUT input func */
  {26U, 21U, 29U, 4U}, 
  /* Inout settings for pad PORT27:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_3_G_IN_OUT input func */
  {27U, 17U, 3U, 3U}, 
  /* Inout settings for pad PORT28:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_4_G_IN_OUT input func */
  {28U, 17U, 4U, 3U}, 
  /* Inout settings for pad PORT29:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_5_G_IN_OUT input func */
  {29U, 17U, 5U, 3U}, 
  /* Inout settings for pad PORT30:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_6_G_IN_OUT input func */
  {30U, 17U, 6U, 3U}, 
  /* Inout settings for pad PORT31:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_7_G_IN_OUT input func */
  {31U, 17U, 7U, 3U}, 
  /* Inout settings for pad PORT34:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* DSPI_1_dSCLK_IN_OUT input func */
  {34U, 17U, 292U, 1U}, 
  /* Inout settings for pad PORT36:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_31_Y_IN_OUT input func */
  {36U, 17U, 67U, 2U}, 
  /* Inout settings for pad PORT38:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_28_Y_IN_OUT input func */
  {38U, 18U, 64U, 2U}, 
  /* EMIOS0_E0UC_17_Y_IN_OUT input func */
  {38U, 19U, 17U, 3U}, 
  /* Inout settings for pad PORT39:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_29_Y_IN_OUT input func */
  {39U, 17U, 65U, 2U}, 
  /* EMIOS0_E0UC_18_Y_IN_OUT input func */
  {39U, 19U, 18U, 3U}, 
  /* Inout settings for pad PORT40:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_3_G_IN_OUT input func */
  {40U, 18U, 3U, 4U}, 
  /* Inout settings for pad PORT41:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_7_G_IN_OUT input func */
  {41U, 17U, 7U, 4U}, 
  /* Inout settings for pad PORT43:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_1_G_IN_OUT input func */
  {43U, 18U, 1U, 5U}, 
  /* Inout settings for pad PORT44:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_12_H_IN_OUT input func */
  {44U, 17U, 12U, 2U}, 
  /* Inout settings for pad PORT45:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_13_H_IN_OUT input func */
  {45U, 17U, 13U, 3U}, 
  /* Inout settings for pad PORT46:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_14_H_IN_OUT input func */
  {46U, 17U, 14U, 3U}, 
  /* DSPI_2_dSCLK_IN_OUT input func */
  {46U, 18U, 295U, 1U}, 
  /* Inout settings for pad PORT47:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_15_H_IN_OUT input func */
  {47U, 17U, 15U, 2U}, 
  /* Inout settings for pad PORT60:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_24_X_IN_OUT input func */
  {60U, 18U, 24U, 2U}, 
  /* Inout settings for pad PORT61:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_25_Y_IN_OUT input func */
  {61U, 18U, 25U, 2U}, 
  /* ENET0_ENET0_TMR0_IN_OUT input func */
  {61U, 19U, 329U, 1U}, 
  /* Inout settings for pad PORT62:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_26_Y_IN_OUT input func */
  {62U, 18U, 26U, 2U}, 
  /* Inout settings for pad PORT63:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_27_Y_IN_OUT input func */
  {63U, 18U, 27U, 2U}, 
  /* Inout settings for pad PORT64:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_16_X_IN_OUT input func */
  {64U, 17U, 16U, 2U}, 
  /* IIC_1_SCL1_IN_OUT input func */
  {64U, 18U, 267U, 1U}, 
  /* Inout settings for pad PORT65:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_17_Y_IN_OUT input func */
  {65U, 17U, 17U, 2U}, 
  /* IIC_1_SDA1_IN_OUT input func */
  {65U, 19U, 268U, 1U}, 
  /* Inout settings for pad PORT66:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_18_Y_IN_OUT input func */
  {66U, 17U, 18U, 2U}, 
  /* Inout settings for pad PORT67:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_19_Y_IN_OUT input func */
  {67U, 17U, 19U, 2U}, 
  /* Inout settings for pad PORT68:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_20_Y_IN_OUT input func */
  {68U, 17U, 20U, 2U}, 
  /* DSPI_1_dSCLK_IN_OUT input func */
  {68U, 18U, 292U, 2U}, 
  /* Inout settings for pad PORT69:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_21_Y_IN_OUT input func */
  {69U, 17U, 21U, 2U}, 
  /* Inout settings for pad PORT70:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_22_X_IN_OUT input func */
  {70U, 17U, 22U, 2U}, 
  /* Inout settings for pad PORT71:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_23_X_IN_OUT input func */
  {71U, 17U, 23U, 2U}, 
  /* Inout settings for pad PORT72:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_22_X_IN_OUT input func */
  {72U, 18U, 22U, 3U}, 
  /* IIC_2_SDA2_IN_OUT input func */
  {72U, 20U, 270U, 1U}, 
  /* Inout settings for pad PORT73:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_23_X_IN_OUT input func */
  {73U, 17U, 23U, 3U}, 
  /* IIC_2_SCL2_IN_OUT input func */
  {73U, 18U, 269U, 1U}, 
  /* Inout settings for pad PORT74:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_30_Y_IN_OUT input func */
  {74U, 19U, 66U, 2U}, 
  /* IIC_3_SDA3_IN_OUT input func */
  {74U, 20U, 272U, 1U}, 
  /* Inout settings for pad PORT75:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_24_X_IN_OUT input func */
  {75U, 17U, 24U, 3U}, 
  /* IIC_3_SCL3_IN_OUT input func */
  {75U, 20U, 271U, 1U}, 
  /* Inout settings for pad PORT76:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_19_Y_IN_OUT input func */
  {76U, 17U, 55U, 2U}, 
  /* Inout settings for pad PORT77:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_20_Y_IN_OUT input func */
  {77U, 18U, 56U, 2U}, 
  /* Inout settings for pad PORT78:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* DSPI_2_dSCLK_IN_OUT input func */
  {78U, 17U, 295U, 2U}, 
  /* EMIOS1_E1UC_21_Y_IN_OUT input func */
  {78U, 18U, 57U, 2U}, 
  /* Inout settings for pad PORT79:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_22_X_IN_OUT input func */
  {79U, 18U, 58U, 2U}, 
  /* SPI_2_SCLK_2_IN_OUT input func */
  {79U, 19U, 307U, 1U}, 
  /* Inout settings for pad PORT80:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_10_H_IN_OUT input func */
  {80U, 17U, 10U, 3U}, 
  /* SAI0_SAI0_MCLK_IN_OUT input func */
  {80U, 23U, 489U, 1U}, 
  /* Inout settings for pad PORT81:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_11_H_IN_OUT input func */
  {81U, 17U, 11U, 3U}, 
  /* SAI0_SAI0_BCLK_IN_OUT input func */
  {81U, 20U, 488U, 1U}, 
  /* Inout settings for pad PORT82:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_12_H_IN_OUT input func */
  {82U, 17U, 12U, 3U}, 
  /* SAI0_SAI0_D3_IN_OUT input func */
  {82U, 20U, 494U, 1U}, 
  /* Inout settings for pad PORT83:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_13_H_IN_OUT input func */
  {83U, 17U, 13U, 4U}, 
  /* SAI0_SAI0_D2_IN_OUT input func */
  {83U, 20U, 493U, 1U}, 
  /* Inout settings for pad PORT84:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_14_H_IN_OUT input func */
  {84U, 17U, 14U, 4U}, 
  /* SAI0_SAI0_D1_IN_OUT input func */
  {84U, 20U, 492U, 1U}, 
  /* Inout settings for pad PORT85:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_22_X_IN_OUT input func */
  {85U, 17U, 22U, 4U}, 
  /* SAI0_SAI0_D0_IN_OUT input func */
  {85U, 20U, 491U, 1U}, 
  /* Inout settings for pad PORT86:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_23_X_IN_OUT input func */
  {86U, 17U, 23U, 4U}, 
  /* SAI1_SAI1_SYNC_IN_OUT input func */
  {86U, 20U, 497U, 1U}, 
  /* EMIOS0_E0UC_30_Y_IN_OUT input func */
  {86U, 21U, 30U, 5U}, 
  /* Inout settings for pad PORT87:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SPI_0_SCLK_0_IN_OUT input func */
  {87U, 17U, 301U, 1U}, 
  /* SAI1_SAI1_MCLK_IN_OUT input func */
  {87U, 22U, 496U, 1U}, 
  /* Inout settings for pad PORT88:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_15_H_IN_OUT input func */
  {88U, 20U, 15U, 3U}, 
  /* Inout settings for pad PORT89:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_1_H_IN_OUT input func */
  {89U, 17U, 37U, 2U}, 
  /* EMIOS0_E0UC_14_H_IN_OUT input func */
  {89U, 19U, 14U, 5U}, 
  /* Inout settings for pad PORT90:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_2_H_IN_OUT input func */
  {90U, 19U, 38U, 2U}, 
  /* EMIOS0_E0UC_19_Y_IN_OUT input func */
  {90U, 20U, 19U, 3U}, 
  /* FCCU_EOUT0_IN_OUT input func */
  {90U, 21U, 65535U, 0U}, 
  /* Inout settings for pad PORT91:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_3_H_IN_OUT input func */
  {91U, 18U, 39U, 2U}, 
  /* EMIOS0_E0UC_20_Y_IN_OUT input func */
  {91U, 19U, 20U, 3U}, 
  /* Inout settings for pad PORT92:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_25_Y_IN_OUT input func */
  {92U, 17U, 61U, 2U}, 
  /* EMIOS0_E0UC_16_X_IN_OUT input func */
  {92U, 19U, 16U, 3U}, 
  /* FCCU_EOUT1_IN_OUT input func */
  {92U, 20U, 65535U, 0U}, 
  /* Inout settings for pad PORT93:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_26_Y_IN_OUT input func */
  {93U, 17U, 62U, 2U}, 
  /* EMIOS0_E0UC_22_X_IN_OUT input func */
  {93U, 18U, 22U, 5U}, 
  /* Inout settings for pad PORT94:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_27_Y_IN_OUT input func */
  {94U, 18U, 63U, 2U}, 
  /* ENET0_MII_RMII_0_MDIO_IN_OUT input func */
  {94U, 20U, 450U, 1U}, 
  /* Inout settings for pad PORT95:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_4_H_IN_OUT input func */
  {95U, 17U, 40U, 2U}, 
  /* Inout settings for pad PORT96:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_23_X_IN_OUT input func */
  {96U, 18U, 59U, 2U}, 
  /* Inout settings for pad PORT97:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_24_X_IN_OUT input func */
  {97U, 17U, 60U, 2U}, 
  /* ENET0_MII_RMII_0_TX_CLK_IN_OUT input func */
  {97U, 18U, 449U, 1U}, 
  /* Inout settings for pad PORT98:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_11_H_IN_OUT input func */
  {98U, 17U, 47U, 2U}, 
  /* Inout settings for pad PORT99:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_12_H_IN_OUT input func */
  {99U, 17U, 48U, 2U}, 
  /* Inout settings for pad PORT100:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_13_H_IN_OUT input func */
  {100U, 17U, 49U, 2U}, 
  /* DSPI_3_dSCLK_IN_OUT input func */
  {100U, 18U, 298U, 1U}, 
  /* Inout settings for pad PORT101:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_14_H_IN_OUT input func */
  {101U, 17U, 50U, 2U}, 
  /* EMIOS0_E0UC_2_G_IN_OUT input func */
  {101U, 18U, 2U, 4U}, 
  /* Inout settings for pad PORT102:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_15_H_IN_OUT input func */
  {102U, 17U, 51U, 2U}, 
  /* EMIOS0_E0UC_3_G_IN_OUT input func */
  {102U, 20U, 3U, 6U}, 
  /* Inout settings for pad PORT103:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_16_X_IN_OUT input func */
  {103U, 17U, 52U, 2U}, 
  /* EMIOS1_E1UC_30_Y_IN_OUT input func */
  {103U, 18U, 66U, 3U}, 
  /* Inout settings for pad PORT104:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_17_Y_IN_OUT input func */
  {104U, 17U, 53U, 2U}, 
  /* Inout settings for pad PORT105:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_18_Y_IN_OUT input func */
  {105U, 17U, 54U, 2U}, 
  /* DSPI_2_dSCLK_IN_OUT input func */
  {105U, 18U, 295U, 3U}, 
  /* EMIOS0_E0UC_0_X_IN_OUT input func */
  {105U, 19U, 0U, 5U}, 
  /* Inout settings for pad PORT106:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_24_X_IN_OUT input func */
  {106U, 17U, 24U, 4U}, 
  /* EMIOS1_E1UC_31_Y_IN_OUT input func */
  {106U, 18U, 67U, 3U}, 
  /* Inout settings for pad PORT107:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_25_Y_IN_OUT input func */
  {107U, 17U, 25U, 3U}, 
  /* Inout settings for pad PORT108:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_26_Y_IN_OUT input func */
  {108U, 17U, 26U, 3U}, 
  /* Inout settings for pad PORT109:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_27_Y_IN_OUT input func */
  {109U, 17U, 27U, 3U}, 
  /* SPI_0_SCLK_0_IN_OUT input func */
  {109U, 18U, 301U, 2U}, 
  /* Inout settings for pad PORT110:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_0_X_IN_OUT input func */
  {110U, 17U, 36U, 2U}, 
  /* Inout settings for pad PORT111:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_1_H_IN_OUT input func */
  {111U, 17U, 37U, 3U}, 
  /* Inout settings for pad PORT112:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_2_H_IN_OUT input func */
  {112U, 17U, 38U, 3U}, 
  /* Inout settings for pad PORT113:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_3_H_IN_OUT input func */
  {113U, 17U, 39U, 3U}, 
  /* Inout settings for pad PORT114:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_4_H_IN_OUT input func */
  {114U, 17U, 40U, 3U}, 
  /* DSPI_1_dSCLK_IN_OUT input func */
  {114U, 18U, 292U, 3U}, 
  /* Inout settings for pad PORT115:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_5_H_IN_OUT input func */
  {115U, 17U, 41U, 2U}, 
  /* Inout settings for pad PORT116:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_6_H_IN_OUT input func */
  {116U, 17U, 42U, 2U}, 
  /* IIC_3_SCL3_IN_OUT input func */
  {116U, 19U, 271U, 2U}, 
  /* Inout settings for pad PORT117:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_7_H_IN_OUT input func */
  {117U, 17U, 43U, 2U}, 
  /* IIC_3_SDA3_IN_OUT input func */
  {117U, 18U, 272U, 2U}, 
  /* Inout settings for pad PORT118:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_8_X_IN_OUT input func */
  {118U, 17U, 44U, 2U}, 
  /* SPI_3_SCLK_3_IN_OUT input func */
  {118U, 18U, 310U, 1U}, 
  /* Inout settings for pad PORT119:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_9_H_IN_OUT input func */
  {119U, 17U, 45U, 2U}, 
  /* Inout settings for pad PORT120:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_10_H_IN_OUT input func */
  {120U, 17U, 46U, 2U}, 
  /* Inout settings for pad PORT122:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* DCI_TMS_IN_OUT input func */
  {122U, 17U, 65535U, 0U}, 
  /* Inout settings for pad PORT123:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_5_H_IN_OUT input func */
  {123U, 19U, 41U, 3U}, 
  /* Inout settings for pad PORT124:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* DSPI_3_dSCLK_IN_OUT input func */
  {124U, 17U, 298U, 2U}, 
  /* EMIOS1_E1UC_25_Y_IN_OUT input func */
  {124U, 19U, 61U, 3U}, 
  /* Inout settings for pad PORT125:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_26_Y_IN_OUT input func */
  {125U, 19U, 62U, 3U}, 
  /* FCCU_EOUT1_IN_OUT input func */
  {125U, 20U, 65535U, 0U}, 
  /* Inout settings for pad PORT126:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SPI_0_SCLK_0_IN_OUT input func */
  {126U, 17U, 301U, 3U}, 
  /* EMIOS1_E1UC_27_Y_IN_OUT input func */
  {126U, 19U, 63U, 3U}, 
  /* Inout settings for pad PORT127:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_17_Y_IN_OUT input func */
  {127U, 19U, 53U, 3U}, 
  /* FCCU_EOUT0_IN_OUT input func */
  {127U, 20U, 65535U, 0U}, 
  /* Inout settings for pad PORT128:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_28_Y_IN_OUT input func */
  {128U, 17U, 28U, 3U}, 
  /* IIC_1_SDA1_IN_OUT input func */
  {128U, 19U, 268U, 2U}, 
  /* Inout settings for pad PORT129:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_29_Y_IN_OUT input func */
  {129U, 17U, 29U, 3U}, 
  /* IIC_1_SCL1_IN_OUT input func */
  {129U, 18U, 267U, 2U}, 
  /* Inout settings for pad PORT130:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_30_Y_IN_OUT input func */
  {130U, 17U, 30U, 4U}, 
  /* IIC_2_SDA2_IN_OUT input func */
  {130U, 19U, 270U, 2U}, 
  /* Inout settings for pad PORT131:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_31_Y_IN_OUT input func */
  {131U, 17U, 31U, 4U}, 
  /* IIC_2_SCL2_IN_OUT input func */
  {131U, 18U, 269U, 2U}, 
  /* Inout settings for pad PORT132:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_28_Y_IN_OUT input func */
  {132U, 17U, 64U, 3U}, 
  /* Inout settings for pad PORT133:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_29_Y_IN_OUT input func */
  {133U, 17U, 65U, 3U}, 
  /* SPI_0_SCLK_0_IN_OUT input func */
  {133U, 18U, 301U, 4U}, 
  /* Inout settings for pad PORT134:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_30_Y_IN_OUT input func */
  {134U, 17U, 66U, 4U}, 
  /* Inout settings for pad PORT135:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_31_Y_IN_OUT input func */
  {135U, 17U, 67U, 4U}, 
  /* Inout settings for pad PORT139:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* ENET0_ENET0_TMR1_IN_OUT input func */
  {139U, 18U, 330U, 1U}, 
  /* Inout settings for pad PORT142:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SAI2_SAI2_D0_IN_OUT input func */
  {142U, 17U, 505U, 2U}, 
  /* Inout settings for pad PORT143:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SAI2_SAI2_MCLK_IN_OUT input func */
  {143U, 19U, 503U, 2U}, 
  /* Inout settings for pad PORT144:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SAI2_SAI2_SYNC_IN_OUT input func */
  {144U, 19U, 504U, 2U}, 
  /* Inout settings for pad PORT145:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SAI2_SAI2_BCLK_IN_OUT input func */
  {145U, 18U, 502U, 1U}, 
  /* Inout settings for pad PORT146:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SAI1_SAI1_D0_IN_OUT input func */
  {146U, 20U, 498U, 1U}, 
  /* Inout settings for pad PORT147:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SAI1_SAI1_BCLK_IN_OUT input func */
  {147U, 20U, 495U, 1U}, 
  /* Inout settings for pad PORT148:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SPI_1_SCLK_1_IN_OUT input func */
  {148U, 17U, 304U, 1U}, 
  /* EMIOS1_E1UC_18_Y_IN_OUT input func */
  {148U, 18U, 54U, 3U}, 
  /* Inout settings for pad PORT149:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SAI2_SAI2_D0_IN_OUT input func */
  {149U, 18U, 505U, 1U}, 
  /* Inout settings for pad PORT150:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SAI2_SAI2_BCLK_IN_OUT input func */
  {150U, 18U, 502U, 2U}, 
  /* Inout settings for pad PORT151:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SAI2_SAI2_MCLK_IN_OUT input func */
  {151U, 19U, 503U, 1U}, 
  /* Inout settings for pad PORT152:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SAI2_SAI2_SYNC_IN_OUT input func */
  {152U, 18U, 504U, 1U}, 
  /* Inout settings for pad PORT153:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_17_Y_IN_OUT input func */
  {153U, 19U, 53U, 4U}, 
  /* Inout settings for pad PORT154:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_16_X_IN_OUT input func */
  {154U, 18U, 52U, 3U}, 
  /* Inout settings for pad PORT155:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_11_H_IN_OUT input func */
  {155U, 18U, 47U, 3U}, 
  /* Inout settings for pad PORT156:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_10_H_IN_OUT input func */
  {156U, 17U, 46U, 3U}, 
  /* Inout settings for pad PORT157:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_15_H_IN_OUT input func */
  {157U, 19U, 51U, 3U}, 
  /* Inout settings for pad PORT158:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_14_H_IN_OUT input func */
  {158U, 22U, 50U, 3U}, 
  /* Inout settings for pad PORT159:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_13_H_IN_OUT input func */
  {159U, 18U, 49U, 3U}, 
  /* Inout settings for pad PORT160:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_12_H_IN_OUT input func */
  {160U, 20U, 48U, 3U}, 
  /* Inout settings for pad PORT161:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_6_G_IN_OUT input func */
  {161U, 18U, 6U, 4U}, 
  /* EMIOS1_E1UC_1_H_IN_OUT input func */
  {161U, 19U, 37U, 4U}, 
  /* Inout settings for pad PORT162:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_2_H_IN_OUT input func */
  {162U, 19U, 38U, 4U}, 
  /* Inout settings for pad PORT163:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_0_X_IN_OUT input func */
  {163U, 17U, 36U, 3U}, 
  /* EMIOS1_E1UC_3_H_IN_OUT input func */
  {163U, 19U, 39U, 4U}, 
  /* Inout settings for pad PORT164:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_1_H_IN_OUT input func */
  {164U, 19U, 37U, 5U}, 
  /* EMIOS0_E0UC_9_H_IN_OUT input func */
  {164U, 20U, 9U, 3U}, 
  /* Inout settings for pad PORT165:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_10_H_IN_OUT input func */
  {165U, 17U, 10U, 4U}, 
  /* EMIOS1_E1UC_4_H_IN_OUT input func */
  {165U, 18U, 40U, 4U}, 
  /* Inout settings for pad PORT166:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_11_H_IN_OUT input func */
  {166U, 19U, 11U, 4U}, 
  /* EMIOS1_E1UC_5_H_IN_OUT input func */
  {166U, 20U, 41U, 4U}, 
  /* Inout settings for pad PORT167:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_12_H_IN_OUT input func */
  {167U, 17U, 12U, 4U}, 
  /* EMIOS1_E1UC_6_H_IN_OUT input func */
  {167U, 18U, 42U, 3U}, 
  /* Inout settings for pad PORT168:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_13_H_IN_OUT input func */
  {168U, 19U, 13U, 5U}, 
  /* EMIOS1_E1UC_7_H_IN_OUT input func */
  {168U, 20U, 43U, 3U}, 
  /* Inout settings for pad PORT169:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_29_Y_IN_OUT input func */
  {169U, 17U, 65U, 4U}, 
  /* Inout settings for pad PORT170:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_30_Y_IN_OUT input func */
  {170U, 18U, 66U, 5U}, 
  /* Inout settings for pad PORT171:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SPI_0_SCLK_0_IN_OUT input func */
  {171U, 17U, 301U, 5U}, 
  /* EMIOS1_E1UC_31_Y_IN_OUT input func */
  {171U, 18U, 67U, 5U}, 
  /* Inout settings for pad PORT172:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_0_X_IN_OUT input func */
  {172U, 18U, 0U, 4U}, 
  /* Inout settings for pad PORT173:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SPI_1_SCLK_1_IN_OUT input func */
  {173U, 19U, 304U, 2U}, 
  /* EMIOS0_E0UC_1_G_IN_OUT input func */
  {173U, 20U, 1U, 4U}, 
  /* Inout settings for pad PORT174:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_2_G_IN_OUT input func */
  {174U, 20U, 2U, 3U}, 
  /* Inout settings for pad PORT175:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_3_G_IN_OUT input func */
  {175U, 18U, 3U, 5U}, 
  /* Inout settings for pad PORT176:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_4_G_IN_OUT input func */
  {176U, 20U, 4U, 4U}, 
  /* Inout settings for pad PORT177:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SAI0_SAI0_D0_IN_OUT input func */
  {177U, 17U, 491U, 2U}, 
  /* Inout settings for pad PORT195:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SAI0_SAI0_D1_IN_OUT input func */
  {195U, 17U, 492U, 3U}, 
  /* ENET0_ENET0_TMR2_IN_OUT input func */
  {195U, 18U, 331U, 1U}, 
  /* Inout settings for pad PORT196:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SAI0_SAI0_D2_IN_OUT input func */
  {196U, 17U, 493U, 3U}, 
  /* Inout settings for pad PORT197:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SAI0_SAI0_D3_IN_OUT input func */
  {197U, 17U, 494U, 3U}, 
  /* Inout settings for pad PORT206:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SAI0_SAI0_MCLK_IN_OUT input func */
  {206U, 17U, 489U, 3U}, 
  /* DCI_TMS_ALT_IN_OUT input func */
  {206U, 18U, 65535U, 0U}, 
  /* Inout settings for pad PORT224:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* IIC_0_SDA0_IN_OUT input func */
  {224U, 18U, 266U, 3U}, 
  /* Inout settings for pad PORT225:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* IIC_0_SCL0_IN_OUT input func */
  {225U, 18U, 265U, 3U}, 
  /* Inout settings for pad PORT252:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_24_X_IN_OUT input func */
  {252U, 19U, 60U, 3U}, 
  /* Inout settings for pad PORT253:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_23_X_IN_OUT input func */
  {253U, 18U, 59U, 3U}, 
  /* Inout settings for pad PORT254:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SPI_2_SCLK_2_IN_OUT input func */
  {254U, 17U, 307U, 2U}, 
  /* EMIOS1_E1UC_22_X_IN_OUT input func */
  {254U, 18U, 58U, 3U}, 
  /* Inout settings for pad PORT255:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_21_Y_IN_OUT input func */
  {255U, 17U, 57U, 3U}, 
  /* Inout settings for pad PORT258:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* DSPI_0_dSCLK_IN_OUT input func */
  {258U, 17U, 289U, 3U}, 
  /* Inout settings for pad PORT260:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_28_Y_IN_OUT input func */
  {260U, 18U, 64U, 4U}, 
  /* Inout settings for pad PORT261:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_27_Y_IN_OUT input func */
  {261U, 19U, 63U, 4U}, 
  /* Inout settings for pad PORT262:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_26_Y_IN_OUT input func */
  {262U, 19U, 62U, 4U}, 
  /* Inout settings for pad PORT263:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_25_Y_IN_OUT input func */
  {263U, 19U, 61U, 4U}
[!ENDVAR!]


[!VAR "SIZE_OF_INOUT_SETTINGS_3"!][!//
246[!//
[!ENDVAR!]


[!VAR "INOUT_SETTINGS_4"!]
  /* Inout settings for pad PORT0:      {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_0_X_IN_OUT input func */
  {0U, 17U, 0U, 2U}, 
  /* EMIOS0_E0UC_13_H_IN_OUT input func */
  {0U, 19U, 13U, 2U}, 
  /* Inout settings for pad PORT1:      {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_1_G_IN_OUT input func */
  {1U, 17U, 1U, 2U}, 
  /* Inout settings for pad PORT2:      {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_2_G_IN_OUT input func */
  {2U, 17U, 2U, 2U}, 
  /* Inout settings for pad PORT3:      {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_3_G_IN_OUT input func */
  {3U, 17U, 3U, 2U}, 
  /* Inout settings for pad PORT4:      {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_4_G_IN_OUT input func */
  {4U, 17U, 4U, 2U}, 
  /* EMIOS0_E0UC_24_X_IN_OUT input func */
  {4U, 19U, 24U, 5U}, 
  /* Inout settings for pad PORT5:      {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_5_G_IN_OUT input func */
  {5U, 17U, 5U, 2U}, 
  /* Inout settings for pad PORT6:      {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_6_G_IN_OUT input func */
  {6U, 17U, 6U, 2U}, 
  /* Inout settings for pad PORT7:      {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_7_G_IN_OUT input func */
  {7U, 17U, 7U, 2U}, 
  /* Inout settings for pad PORT8:      {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_8_X_IN_OUT input func */
  {8U, 17U, 8U, 2U}, 
  /* EMIOS0_E0UC_14_H_IN_OUT input func */
  {8U, 18U, 14U, 2U}, 
  /* Inout settings for pad PORT9:      {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_9_H_IN_OUT input func */
  {9U, 17U, 9U, 2U}, 
  /* Inout settings for pad PORT10:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_10_H_IN_OUT input func */
  {10U, 17U, 10U, 2U}, 
  /* IIC_0_SDA0_IN_OUT input func */
  {10U, 18U, 266U, 1U}, 
  /* Inout settings for pad PORT11:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_11_H_IN_OUT input func */
  {11U, 17U, 11U, 2U}, 
  /* IIC_0_SCL0_IN_OUT input func */
  {11U, 18U, 265U, 1U}, 
  /* Inout settings for pad PORT12:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_28_Y_IN_OUT input func */
  {12U, 17U, 28U, 2U}, 
  /* EMIOS0_E0UC_26_Y_IN_OUT input func */
  {12U, 19U, 26U, 4U}, 
  /* Inout settings for pad PORT13:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_29_Y_IN_OUT input func */
  {13U, 18U, 29U, 2U}, 
  /* EMIOS0_E0UC_25_Y_IN_OUT input func */
  {13U, 19U, 25U, 4U}, 
  /* Inout settings for pad PORT14:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* DSPI_0_dSCLK_IN_OUT input func */
  {14U, 17U, 289U, 1U}, 
  /* EMIOS0_E0UC_0_X_IN_OUT input func */
  {14U, 19U, 0U, 3U}, 
  /* EMIOS0_E0UC_23_X_IN_OUT input func */
  {14U, 20U, 23U, 5U}, 
  /* Inout settings for pad PORT15:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* DSPI_0_dSCLK_IN_OUT input func */
  {15U, 18U, 289U, 2U}, 
  /* EMIOS0_E0UC_1_G_IN_OUT input func */
  {15U, 19U, 1U, 3U}, 
  /* EMIOS0_E0UC_21_Y_IN_OUT input func */
  {15U, 20U, 21U, 3U}, 
  /* Inout settings for pad PORT16:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_30_Y_IN_OUT input func */
  {16U, 18U, 30U, 2U}, 
  /* EMIOS0_E0UC_4_G_IN_OUT input func */
  {16U, 20U, 4U, 5U}, 
  /* Inout settings for pad PORT17:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_31_Y_IN_OUT input func */
  {17U, 17U, 31U, 2U}, 
  /* EMIOS0_E0UC_5_G_IN_OUT input func */
  {17U, 18U, 5U, 4U}, 
  /* Inout settings for pad PORT18:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* IIC_0_SDA0_IN_OUT input func */
  {18U, 18U, 266U, 2U}, 
  /* EMIOS0_E0UC_30_Y_IN_OUT input func */
  {18U, 19U, 30U, 3U}, 
  /* Inout settings for pad PORT19:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_31_Y_IN_OUT input func */
  {19U, 17U, 31U, 3U}, 
  /* IIC_0_SCL0_IN_OUT input func */
  {19U, 18U, 265U, 2U}, 
  /* EMIOS0_E0UC_8_X_IN_OUT input func */
  {19U, 19U, 8U, 3U}, 
  /* Inout settings for pad PORT26:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SAI0_SAI0_SYNC_IN_OUT input func */
  {26U, 20U, 490U, 1U}, 
  /* EMIOS0_E0UC_29_Y_IN_OUT input func */
  {26U, 21U, 29U, 4U}, 
  /* Inout settings for pad PORT27:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_3_G_IN_OUT input func */
  {27U, 17U, 3U, 3U}, 
  /* Inout settings for pad PORT28:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_4_G_IN_OUT input func */
  {28U, 17U, 4U, 3U}, 
  /* Inout settings for pad PORT29:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_5_G_IN_OUT input func */
  {29U, 17U, 5U, 3U}, 
  /* Inout settings for pad PORT30:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_6_G_IN_OUT input func */
  {30U, 17U, 6U, 3U}, 
  /* Inout settings for pad PORT31:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_7_G_IN_OUT input func */
  {31U, 17U, 7U, 3U}, 
  /* Inout settings for pad PORT34:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* DSPI_1_dSCLK_IN_OUT input func */
  {34U, 17U, 292U, 1U}, 
  /* Inout settings for pad PORT36:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_31_Y_IN_OUT input func */
  {36U, 17U, 67U, 2U}, 
  /* Inout settings for pad PORT38:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_28_Y_IN_OUT input func */
  {38U, 18U, 64U, 2U}, 
  /* EMIOS0_E0UC_17_Y_IN_OUT input func */
  {38U, 19U, 17U, 3U}, 
  /* Inout settings for pad PORT39:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_29_Y_IN_OUT input func */
  {39U, 17U, 65U, 2U}, 
  /* EMIOS0_E0UC_18_Y_IN_OUT input func */
  {39U, 19U, 18U, 3U}, 
  /* Inout settings for pad PORT40:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_3_G_IN_OUT input func */
  {40U, 18U, 3U, 4U}, 
  /* Inout settings for pad PORT41:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_7_G_IN_OUT input func */
  {41U, 17U, 7U, 4U}, 
  /* Inout settings for pad PORT43:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_1_G_IN_OUT input func */
  {43U, 18U, 1U, 5U}, 
  /* Inout settings for pad PORT44:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_12_H_IN_OUT input func */
  {44U, 17U, 12U, 2U}, 
  /* Inout settings for pad PORT45:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_13_H_IN_OUT input func */
  {45U, 17U, 13U, 3U}, 
  /* Inout settings for pad PORT46:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_14_H_IN_OUT input func */
  {46U, 17U, 14U, 3U}, 
  /* DSPI_2_dSCLK_IN_OUT input func */
  {46U, 18U, 295U, 1U}, 
  /* Inout settings for pad PORT47:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_15_H_IN_OUT input func */
  {47U, 17U, 15U, 2U}, 
  /* Inout settings for pad PORT60:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_24_X_IN_OUT input func */
  {60U, 18U, 24U, 2U}, 
  /* Inout settings for pad PORT61:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_25_Y_IN_OUT input func */
  {61U, 18U, 25U, 2U}, 
  /* ENET0_ENET0_TMR0_IN_OUT input func */
  {61U, 19U, 329U, 1U}, 
  /* Inout settings for pad PORT62:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_26_Y_IN_OUT input func */
  {62U, 18U, 26U, 2U}, 
  /* Inout settings for pad PORT63:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_27_Y_IN_OUT input func */
  {63U, 18U, 27U, 2U}, 
  /* Inout settings for pad PORT64:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_16_X_IN_OUT input func */
  {64U, 17U, 16U, 2U}, 
  /* IIC_1_SCL1_IN_OUT input func */
  {64U, 18U, 267U, 1U}, 
  /* Inout settings for pad PORT65:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_17_Y_IN_OUT input func */
  {65U, 17U, 17U, 2U}, 
  /* IIC_1_SDA1_IN_OUT input func */
  {65U, 19U, 268U, 1U}, 
  /* Inout settings for pad PORT66:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_18_Y_IN_OUT input func */
  {66U, 17U, 18U, 2U}, 
  /* Inout settings for pad PORT67:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_19_Y_IN_OUT input func */
  {67U, 17U, 19U, 2U}, 
  /* Inout settings for pad PORT68:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_20_Y_IN_OUT input func */
  {68U, 17U, 20U, 2U}, 
  /* DSPI_1_dSCLK_IN_OUT input func */
  {68U, 18U, 292U, 2U}, 
  /* Inout settings for pad PORT69:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_21_Y_IN_OUT input func */
  {69U, 17U, 21U, 2U}, 
  /* Inout settings for pad PORT70:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_22_X_IN_OUT input func */
  {70U, 17U, 22U, 2U}, 
  /* Inout settings for pad PORT71:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_23_X_IN_OUT input func */
  {71U, 17U, 23U, 2U}, 
  /* Inout settings for pad PORT72:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_22_X_IN_OUT input func */
  {72U, 18U, 22U, 3U}, 
  /* IIC_2_SDA2_IN_OUT input func */
  {72U, 20U, 270U, 1U}, 
  /* Inout settings for pad PORT73:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_23_X_IN_OUT input func */
  {73U, 17U, 23U, 3U}, 
  /* IIC_2_SCL2_IN_OUT input func */
  {73U, 18U, 269U, 1U}, 
  /* Inout settings for pad PORT74:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_30_Y_IN_OUT input func */
  {74U, 19U, 66U, 2U}, 
  /* IIC_3_SDA3_IN_OUT input func */
  {74U, 20U, 272U, 1U}, 
  /* Inout settings for pad PORT75:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_24_X_IN_OUT input func */
  {75U, 17U, 24U, 3U}, 
  /* IIC_3_SCL3_IN_OUT input func */
  {75U, 20U, 271U, 1U}, 
  /* Inout settings for pad PORT76:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_19_Y_IN_OUT input func */
  {76U, 17U, 55U, 2U}, 
  /* Inout settings for pad PORT77:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_20_Y_IN_OUT input func */
  {77U, 18U, 56U, 2U}, 
  /* Inout settings for pad PORT78:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* DSPI_2_dSCLK_IN_OUT input func */
  {78U, 17U, 295U, 2U}, 
  /* EMIOS1_E1UC_21_Y_IN_OUT input func */
  {78U, 18U, 57U, 2U}, 
  /* Inout settings for pad PORT79:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_22_X_IN_OUT input func */
  {79U, 18U, 58U, 2U}, 
  /* SPI_2_SCLK_2_IN_OUT input func */
  {79U, 19U, 307U, 1U}, 
  /* Inout settings for pad PORT80:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_10_H_IN_OUT input func */
  {80U, 17U, 10U, 3U}, 
  /* SAI0_SAI0_MCLK_IN_OUT input func */
  {80U, 23U, 489U, 1U}, 
  /* Inout settings for pad PORT81:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_11_H_IN_OUT input func */
  {81U, 17U, 11U, 3U}, 
  /* SAI0_SAI0_BCLK_IN_OUT input func */
  {81U, 20U, 488U, 1U}, 
  /* Inout settings for pad PORT82:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_12_H_IN_OUT input func */
  {82U, 17U, 12U, 3U}, 
  /* SAI0_SAI0_D3_IN_OUT input func */
  {82U, 20U, 494U, 1U}, 
  /* Inout settings for pad PORT83:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_13_H_IN_OUT input func */
  {83U, 17U, 13U, 4U}, 
  /* SAI0_SAI0_D2_IN_OUT input func */
  {83U, 20U, 493U, 1U}, 
  /* Inout settings for pad PORT84:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_14_H_IN_OUT input func */
  {84U, 17U, 14U, 4U}, 
  /* SAI0_SAI0_D1_IN_OUT input func */
  {84U, 20U, 492U, 1U}, 
  /* Inout settings for pad PORT85:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_22_X_IN_OUT input func */
  {85U, 17U, 22U, 4U}, 
  /* SAI0_SAI0_D0_IN_OUT input func */
  {85U, 20U, 491U, 1U}, 
  /* Inout settings for pad PORT86:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_23_X_IN_OUT input func */
  {86U, 17U, 23U, 4U}, 
  /* SAI1_SAI1_SYNC_IN_OUT input func */
  {86U, 20U, 497U, 1U}, 
  /* EMIOS0_E0UC_30_Y_IN_OUT input func */
  {86U, 21U, 30U, 5U}, 
  /* Inout settings for pad PORT87:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SPI_0_SCLK_0_IN_OUT input func */
  {87U, 17U, 301U, 1U}, 
  /* SAI1_SAI1_MCLK_IN_OUT input func */
  {87U, 22U, 496U, 1U}, 
  /* Inout settings for pad PORT88:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_15_H_IN_OUT input func */
  {88U, 20U, 15U, 3U}, 
  /* Inout settings for pad PORT89:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_1_H_IN_OUT input func */
  {89U, 17U, 37U, 2U}, 
  /* EMIOS0_E0UC_14_H_IN_OUT input func */
  {89U, 19U, 14U, 5U}, 
  /* Inout settings for pad PORT90:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_2_H_IN_OUT input func */
  {90U, 19U, 38U, 2U}, 
  /* EMIOS0_E0UC_19_Y_IN_OUT input func */
  {90U, 20U, 19U, 3U}, 
  /* FCCU_EOUT0_IN_OUT input func */
  {90U, 21U, 65535U, 0U}, 
  /* Inout settings for pad PORT91:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_3_H_IN_OUT input func */
  {91U, 18U, 39U, 2U}, 
  /* EMIOS0_E0UC_20_Y_IN_OUT input func */
  {91U, 19U, 20U, 3U}, 
  /* Inout settings for pad PORT92:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_25_Y_IN_OUT input func */
  {92U, 17U, 61U, 2U}, 
  /* EMIOS0_E0UC_16_X_IN_OUT input func */
  {92U, 19U, 16U, 3U}, 
  /* FCCU_EOUT1_IN_OUT input func */
  {92U, 20U, 65535U, 0U}, 
  /* Inout settings for pad PORT93:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_26_Y_IN_OUT input func */
  {93U, 17U, 62U, 2U}, 
  /* EMIOS0_E0UC_22_X_IN_OUT input func */
  {93U, 18U, 22U, 5U}, 
  /* Inout settings for pad PORT94:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_27_Y_IN_OUT input func */
  {94U, 18U, 63U, 2U}, 
  /* ENET0_MII_RMII_0_MDIO_IN_OUT input func */
  {94U, 20U, 450U, 1U}, 
  /* Inout settings for pad PORT95:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_4_H_IN_OUT input func */
  {95U, 17U, 40U, 2U}, 
  /* Inout settings for pad PORT96:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_23_X_IN_OUT input func */
  {96U, 18U, 59U, 2U}, 
  /* Inout settings for pad PORT97:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_24_X_IN_OUT input func */
  {97U, 17U, 60U, 2U}, 
  /* ENET0_MII_RMII_0_TX_CLK_IN_OUT input func */
  {97U, 18U, 449U, 1U}, 
  /* Inout settings for pad PORT98:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_11_H_IN_OUT input func */
  {98U, 17U, 47U, 2U}, 
  /* Inout settings for pad PORT99:     {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_12_H_IN_OUT input func */
  {99U, 17U, 48U, 2U}, 
  /* Inout settings for pad PORT100:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_13_H_IN_OUT input func */
  {100U, 17U, 49U, 2U}, 
  /* DSPI_3_dSCLK_IN_OUT input func */
  {100U, 18U, 298U, 1U}, 
  /* Inout settings for pad PORT101:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_14_H_IN_OUT input func */
  {101U, 17U, 50U, 2U}, 
  /* EMIOS0_E0UC_2_G_IN_OUT input func */
  {101U, 18U, 2U, 4U}, 
  /* Inout settings for pad PORT102:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_15_H_IN_OUT input func */
  {102U, 17U, 51U, 2U}, 
  /* EMIOS0_E0UC_3_G_IN_OUT input func */
  {102U, 20U, 3U, 6U}, 
  /* Inout settings for pad PORT103:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_16_X_IN_OUT input func */
  {103U, 17U, 52U, 2U}, 
  /* EMIOS1_E1UC_30_Y_IN_OUT input func */
  {103U, 18U, 66U, 3U}, 
  /* Inout settings for pad PORT104:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_17_Y_IN_OUT input func */
  {104U, 17U, 53U, 2U}, 
  /* Inout settings for pad PORT105:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_18_Y_IN_OUT input func */
  {105U, 17U, 54U, 2U}, 
  /* DSPI_2_dSCLK_IN_OUT input func */
  {105U, 18U, 295U, 3U}, 
  /* EMIOS0_E0UC_0_X_IN_OUT input func */
  {105U, 19U, 0U, 5U}, 
  /* Inout settings for pad PORT106:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_24_X_IN_OUT input func */
  {106U, 17U, 24U, 4U}, 
  /* EMIOS1_E1UC_31_Y_IN_OUT input func */
  {106U, 18U, 67U, 3U}, 
  /* Inout settings for pad PORT107:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_25_Y_IN_OUT input func */
  {107U, 17U, 25U, 3U}, 
  /* Inout settings for pad PORT108:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_26_Y_IN_OUT input func */
  {108U, 17U, 26U, 3U}, 
  /* Inout settings for pad PORT109:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_27_Y_IN_OUT input func */
  {109U, 17U, 27U, 3U}, 
  /* SPI_0_SCLK_0_IN_OUT input func */
  {109U, 18U, 301U, 2U}, 
  /* Inout settings for pad PORT110:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_0_X_IN_OUT input func */
  {110U, 17U, 36U, 2U}, 
  /* Inout settings for pad PORT111:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_1_H_IN_OUT input func */
  {111U, 17U, 37U, 3U}, 
  /* Inout settings for pad PORT112:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_2_H_IN_OUT input func */
  {112U, 17U, 38U, 3U}, 
  /* Inout settings for pad PORT113:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_3_H_IN_OUT input func */
  {113U, 17U, 39U, 3U}, 
  /* Inout settings for pad PORT114:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_4_H_IN_OUT input func */
  {114U, 17U, 40U, 3U}, 
  /* DSPI_1_dSCLK_IN_OUT input func */
  {114U, 18U, 292U, 3U}, 
  /* Inout settings for pad PORT115:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_5_H_IN_OUT input func */
  {115U, 17U, 41U, 2U}, 
  /* Inout settings for pad PORT116:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_6_H_IN_OUT input func */
  {116U, 17U, 42U, 2U}, 
  /* IIC_3_SCL3_IN_OUT input func */
  {116U, 19U, 271U, 2U}, 
  /* Inout settings for pad PORT117:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_7_H_IN_OUT input func */
  {117U, 17U, 43U, 2U}, 
  /* IIC_3_SDA3_IN_OUT input func */
  {117U, 18U, 272U, 2U}, 
  /* Inout settings for pad PORT118:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_8_X_IN_OUT input func */
  {118U, 17U, 44U, 2U}, 
  /* SPI_3_SCLK_3_IN_OUT input func */
  {118U, 18U, 310U, 1U}, 
  /* Inout settings for pad PORT119:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_9_H_IN_OUT input func */
  {119U, 17U, 45U, 2U}, 
  /* Inout settings for pad PORT120:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_10_H_IN_OUT input func */
  {120U, 17U, 46U, 2U}, 
  /* Inout settings for pad PORT122:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* DCI_TMS_IN_OUT input func */
  {122U, 17U, 65535U, 0U}, 
  /* Inout settings for pad PORT123:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_5_H_IN_OUT input func */
  {123U, 19U, 41U, 3U}, 
  /* Inout settings for pad PORT124:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* DSPI_3_dSCLK_IN_OUT input func */
  {124U, 17U, 298U, 2U}, 
  /* EMIOS1_E1UC_25_Y_IN_OUT input func */
  {124U, 19U, 61U, 3U}, 
  /* Inout settings for pad PORT125:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_26_Y_IN_OUT input func */
  {125U, 19U, 62U, 3U}, 
  /* FCCU_EOUT1_IN_OUT input func */
  {125U, 20U, 65535U, 0U}, 
  /* Inout settings for pad PORT126:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SPI_0_SCLK_0_IN_OUT input func */
  {126U, 17U, 301U, 3U}, 
  /* EMIOS1_E1UC_27_Y_IN_OUT input func */
  {126U, 19U, 63U, 3U}, 
  /* Inout settings for pad PORT127:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_17_Y_IN_OUT input func */
  {127U, 19U, 53U, 3U}, 
  /* FCCU_EOUT0_IN_OUT input func */
  {127U, 20U, 65535U, 0U}, 
  /* Inout settings for pad PORT128:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_28_Y_IN_OUT input func */
  {128U, 17U, 28U, 3U}, 
  /* IIC_1_SDA1_IN_OUT input func */
  {128U, 19U, 268U, 2U}, 
  /* Inout settings for pad PORT129:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_29_Y_IN_OUT input func */
  {129U, 17U, 29U, 3U}, 
  /* IIC_1_SCL1_IN_OUT input func */
  {129U, 18U, 267U, 2U}, 
  /* Inout settings for pad PORT130:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_30_Y_IN_OUT input func */
  {130U, 17U, 30U, 4U}, 
  /* IIC_2_SDA2_IN_OUT input func */
  {130U, 19U, 270U, 2U}, 
  /* Inout settings for pad PORT131:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_31_Y_IN_OUT input func */
  {131U, 17U, 31U, 4U}, 
  /* IIC_2_SCL2_IN_OUT input func */
  {131U, 18U, 269U, 2U}, 
  /* Inout settings for pad PORT132:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_28_Y_IN_OUT input func */
  {132U, 17U, 64U, 3U}, 
  /* Inout settings for pad PORT133:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_29_Y_IN_OUT input func */
  {133U, 17U, 65U, 3U}, 
  /* SPI_0_SCLK_0_IN_OUT input func */
  {133U, 18U, 301U, 4U}, 
  /* Inout settings for pad PORT134:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_30_Y_IN_OUT input func */
  {134U, 17U, 66U, 4U}, 
  /* Inout settings for pad PORT135:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_31_Y_IN_OUT input func */
  {135U, 17U, 67U, 4U}, 
  /* Inout settings for pad PORT139:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* ENET0_ENET0_TMR1_IN_OUT input func */
  {139U, 18U, 330U, 1U}, 
  /* Inout settings for pad PORT142:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SAI2_SAI2_D0_IN_OUT input func */
  {142U, 17U, 505U, 2U}, 
  /* Inout settings for pad PORT143:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SAI2_SAI2_MCLK_IN_OUT input func */
  {143U, 19U, 503U, 2U}, 
  /* Inout settings for pad PORT144:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SAI2_SAI2_SYNC_IN_OUT input func */
  {144U, 19U, 504U, 2U}, 
  /* Inout settings for pad PORT145:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SAI2_SAI2_BCLK_IN_OUT input func */
  {145U, 18U, 502U, 1U}, 
  /* Inout settings for pad PORT146:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SAI1_SAI1_D0_IN_OUT input func */
  {146U, 20U, 498U, 1U}, 
  /* Inout settings for pad PORT147:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SAI1_SAI1_BCLK_IN_OUT input func */
  {147U, 20U, 495U, 1U}, 
  /* Inout settings for pad PORT148:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SPI_1_SCLK_1_IN_OUT input func */
  {148U, 17U, 304U, 1U}, 
  /* EMIOS1_E1UC_18_Y_IN_OUT input func */
  {148U, 18U, 54U, 3U}, 
  /* Inout settings for pad PORT149:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SAI2_SAI2_D0_IN_OUT input func */
  {149U, 18U, 505U, 1U}, 
  /* Inout settings for pad PORT150:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SAI2_SAI2_BCLK_IN_OUT input func */
  {150U, 18U, 502U, 2U}, 
  /* Inout settings for pad PORT151:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SAI2_SAI2_MCLK_IN_OUT input func */
  {151U, 19U, 503U, 1U}, 
  /* Inout settings for pad PORT152:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SAI2_SAI2_SYNC_IN_OUT input func */
  {152U, 18U, 504U, 1U}, 
  /* Inout settings for pad PORT153:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_17_Y_IN_OUT input func */
  {153U, 19U, 53U, 4U}, 
  /* Inout settings for pad PORT154:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_16_X_IN_OUT input func */
  {154U, 18U, 52U, 3U}, 
  /* Inout settings for pad PORT155:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_11_H_IN_OUT input func */
  {155U, 18U, 47U, 3U}, 
  /* Inout settings for pad PORT156:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_10_H_IN_OUT input func */
  {156U, 17U, 46U, 3U}, 
  /* Inout settings for pad PORT157:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_15_H_IN_OUT input func */
  {157U, 19U, 51U, 3U}, 
  /* Inout settings for pad PORT158:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_14_H_IN_OUT input func */
  {158U, 22U, 50U, 3U}, 
  /* Inout settings for pad PORT159:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_13_H_IN_OUT input func */
  {159U, 18U, 49U, 3U}, 
  /* Inout settings for pad PORT160:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_12_H_IN_OUT input func */
  {160U, 20U, 48U, 3U}, 
  /* Inout settings for pad PORT161:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_6_G_IN_OUT input func */
  {161U, 18U, 6U, 4U}, 
  /* EMIOS1_E1UC_1_H_IN_OUT input func */
  {161U, 19U, 37U, 4U}, 
  /* Inout settings for pad PORT162:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_2_H_IN_OUT input func */
  {162U, 19U, 38U, 4U}, 
  /* Inout settings for pad PORT163:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_0_X_IN_OUT input func */
  {163U, 17U, 36U, 3U}, 
  /* EMIOS1_E1UC_3_H_IN_OUT input func */
  {163U, 19U, 39U, 4U}, 
  /* Inout settings for pad PORT164:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_1_H_IN_OUT input func */
  {164U, 19U, 37U, 5U}, 
  /* EMIOS0_E0UC_9_H_IN_OUT input func */
  {164U, 20U, 9U, 3U}, 
  /* Inout settings for pad PORT165:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_10_H_IN_OUT input func */
  {165U, 17U, 10U, 4U}, 
  /* EMIOS1_E1UC_4_H_IN_OUT input func */
  {165U, 18U, 40U, 4U}, 
  /* Inout settings for pad PORT166:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_11_H_IN_OUT input func */
  {166U, 19U, 11U, 4U}, 
  /* EMIOS1_E1UC_5_H_IN_OUT input func */
  {166U, 20U, 41U, 4U}, 
  /* Inout settings for pad PORT167:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_12_H_IN_OUT input func */
  {167U, 17U, 12U, 4U}, 
  /* EMIOS1_E1UC_6_H_IN_OUT input func */
  {167U, 18U, 42U, 3U}, 
  /* Inout settings for pad PORT168:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_13_H_IN_OUT input func */
  {168U, 19U, 13U, 5U}, 
  /* EMIOS1_E1UC_7_H_IN_OUT input func */
  {168U, 20U, 43U, 3U}, 
  /* Inout settings for pad PORT169:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_29_Y_IN_OUT input func */
  {169U, 17U, 65U, 4U}, 
  /* Inout settings for pad PORT170:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_30_Y_IN_OUT input func */
  {170U, 18U, 66U, 5U}, 
  /* Inout settings for pad PORT171:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SPI_0_SCLK_0_IN_OUT input func */
  {171U, 17U, 301U, 5U}, 
  /* EMIOS1_E1UC_31_Y_IN_OUT input func */
  {171U, 18U, 67U, 5U}, 
  /* Inout settings for pad PORT172:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_0_X_IN_OUT input func */
  {172U, 18U, 0U, 4U}, 
  /* Inout settings for pad PORT173:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SPI_1_SCLK_1_IN_OUT input func */
  {173U, 19U, 304U, 2U}, 
  /* EMIOS0_E0UC_1_G_IN_OUT input func */
  {173U, 20U, 1U, 4U}, 
  /* Inout settings for pad PORT174:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_2_G_IN_OUT input func */
  {174U, 20U, 2U, 3U}, 
  /* Inout settings for pad PORT175:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_3_G_IN_OUT input func */
  {175U, 18U, 3U, 5U}, 
  /* Inout settings for pad PORT176:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_4_G_IN_OUT input func */
  {176U, 20U, 4U, 4U}, 
  /* Inout settings for pad PORT177:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SAI0_SAI0_D0_IN_OUT input func */
  {177U, 17U, 491U, 2U}, 
  /* Inout settings for pad PORT195:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SAI0_SAI0_D1_IN_OUT input func */
  {195U, 17U, 492U, 3U}, 
  /* ENET0_ENET0_TMR2_IN_OUT input func */
  {195U, 18U, 331U, 1U}, 
  /* Inout settings for pad PORT196:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SAI0_SAI0_D2_IN_OUT input func */
  {196U, 17U, 493U, 3U}, 
  /* Inout settings for pad PORT197:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SAI0_SAI0_D3_IN_OUT input func */
  {197U, 17U, 494U, 3U}, 
  /* Inout settings for pad PORT206:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SAI0_SAI0_MCLK_IN_OUT input func */
  {206U, 17U, 489U, 3U}, 
  /* DCI_TMS_ALT_IN_OUT input func */
  {206U, 18U, 65535U, 0U}, 
  /* Inout settings for pad PORT224:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* IIC_0_SDA0_IN_OUT input func */
  {224U, 18U, 266U, 3U}, 
  /* Inout settings for pad PORT225:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* IIC_0_SCL0_IN_OUT input func */
  {225U, 18U, 265U, 3U}, 
  /* Inout settings for pad PORT252:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_24_X_IN_OUT input func */
  {252U, 19U, 60U, 3U}, 
  /* Inout settings for pad PORT253:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_23_X_IN_OUT input func */
  {253U, 18U, 59U, 3U}, 
  /* Inout settings for pad PORT254:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* SPI_2_SCLK_2_IN_OUT input func */
  {254U, 17U, 307U, 2U}, 
  /* EMIOS1_E1UC_22_X_IN_OUT input func */
  {254U, 18U, 58U, 3U}, 
  /* Inout settings for pad PORT255:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_21_Y_IN_OUT input func */
  {255U, 17U, 57U, 3U}, 
  /* Inout settings for pad PORT258:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* DSPI_0_dSCLK_IN_OUT input func */
  {258U, 17U, 289U, 3U}, 
  /* Inout settings for pad PORT260:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_28_Y_IN_OUT input func */
  {260U, 18U, 64U, 4U}, 
  /* Inout settings for pad PORT261:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_27_Y_IN_OUT input func */
  {261U, 19U, 63U, 4U}, 
  /* Inout settings for pad PORT262:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_26_Y_IN_OUT input func */
  {262U, 19U, 62U, 4U}, 
  /* Inout settings for pad PORT263:    {MSCR, MODE, INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_25_Y_IN_OUT input func */
  {263U, 19U, 61U, 4U}
[!ENDVAR!]


[!VAR "SIZE_OF_INOUT_SETTINGS_4"!][!//
246[!//
[!ENDVAR!]


[!VAR "INOUT_SETTINGS_"!]

[!ENDVAR!]


[!VAR "SIZE_OF_INOUT_SETTINGS_"!][!//
0[!//
[!ENDVAR!]


[!VAR "INPUT_INMUX_1"!]
  /* INMUX settings for pad not available:  */
  { NO_INPUTMUX_U16, 0U},
  /* INMUX settings for pad PORT0:      {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_0_X_IN input func */
  {0U, 2U}, 
  /* EMIOS0_E0UC_13_H_IN input func */
  {13U, 2U}, 
  /* FlexCAN_1_RX input func */
  {189U, 1U}, 
  /* INMUX settings for pad PORT1:      {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_1_G_IN input func */
  {1U, 2U}, 
  /* FlexCAN_3_RX input func */
  {191U, 1U}, 
  /* INMUX settings for pad PORT2:      {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_2_G_IN input func */
  {2U, 2U}, 
  /* INMUX settings for pad PORT3:      {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_3_G_IN input func */
  {3U, 2U}, 
  /* SIUL2_EIRQ0 input func */
  {144U, 1U}, 
  /* ENET0_MII_0_RX_CLK input func */
  {448U, 1U}, 
  /* INMUX settings for pad PORT4:      {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_4_G_IN input func */
  {4U, 2U}, 
  /* LIN_5_LIN5RX input func */
  {205U, 1U}, 
  /* DSPI_1_dSS input func */
  {293U, 1U}, 
  /* EMIOS0_E0UC_24_X_IN input func */
  {24U, 5U}, 
  /* INMUX settings for pad PORT5:      {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_5_G_IN input func */
  {5U, 2U}, 
  /* INMUX settings for pad PORT6:      {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_6_G_IN input func */
  {6U, 2U}, 
  /* SIUL2_EIRQ1 input func */
  {145U, 1U}, 
  /* LIN_4_LIN4RX input func */
  {204U, 1U}, 
  /* INMUX settings for pad PORT7:      {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_7_G_IN input func */
  {7U, 2U}, 
  /* SIUL2_EIRQ2 input func */
  {146U, 1U}, 
  /* ENET0_MII_0_RXD_2 input func */
  {453U, 1U}, 
  /* INMUX settings for pad PORT8:      {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_8_X_IN input func */
  {8U, 2U}, 
  /* EMIOS0_E0UC_14_H_IN input func */
  {14U, 2U}, 
  /* SIUL2_EIRQ3 input func */
  {147U, 1U}, 
  /* LIN_3_LIN3RX input func */
  {203U, 1U}, 
  /* ENET0_MII_RMII_0_RXD_1 input func */
  {452U, 1U}, 
  /* INMUX settings for pad PORT9:      {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_9_H_IN input func */
  {9U, 2U}, 
  /* ENET0_MII_RMII_0_RXD_0 input func */
  {451U, 1U}, 
  /* INMUX settings for pad PORT10:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_10_H_IN input func */
  {10U, 2U}, 
  /* IIC_0_SDA0_IN input func */
  {266U, 1U}, 
  /* DSPI_1_dSIN input func */
  {291U, 1U}, 
  /* ENET0_MII_0_COL input func */
  {456U, 1U}, 
  /* INMUX settings for pad PORT11:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_11_H_IN input func */
  {11U, 2U}, 
  /* SIUL2_EIRQ16 input func */
  {160U, 1U}, 
  /* LIN_2_LIN2RX input func */
  {202U, 1U}, 
  /* IIC_0_SCL0_IN input func */
  {265U, 1U}, 
  /* ENET0_MII_RMII_0_RX_ER input func */
  {455U, 1U}, 
  /* INMUX settings for pad PORT12:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_28_Y_IN input func */
  {28U, 2U}, 
  /* SIUL2_EIRQ17 input func */
  {161U, 1U}, 
  /* DSPI_0_dSIN input func */
  {288U, 1U}, 
  /* EMIOS0_E0UC_26_Y_IN input func */
  {26U, 4U}, 
  /* GLITCH_FILTER0_INP input func */
  {506U, 1U}, 
  /* INMUX settings for pad PORT13:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_29_Y_IN input func */
  {29U, 2U}, 
  /* EMIOS0_E0UC_25_Y_IN input func */
  {25U, 4U}, 
  /* GLITCH_FILTER0_INP input func */
  {506U, 3U}, 
  /* INMUX settings for pad PORT14:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_0_X_IN input func */
  {0U, 3U}, 
  /* SIUL2_EIRQ4 input func */
  {148U, 1U}, 
  /* DSPI_0_dSCLK_IN input func */
  {289U, 1U}, 
  /* DSPI_0_dSS input func */
  {290U, 1U}, 
  /* EMIOS0_E0UC_23_X_IN input func */
  {23U, 5U}, 
  /* INMUX settings for pad PORT15:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_1_G_IN input func */
  {1U, 3U}, 
  /* FlexCAN_0_RX input func */
  {188U, 1U}, 
  /* DSPI_0_dSCLK_IN input func */
  {289U, 2U}, 
  /* DSPI_0_dSS input func */
  {290U, 2U}, 
  /* EMIOS0_E0UC_21_Y_IN input func */
  {21U, 3U}, 
  /* INMUX settings for pad PORT16:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_30_Y_IN input func */
  {30U, 2U}, 
  /* EMIOS0_E0UC_4_G_IN input func */
  {4U, 5U}, 
  /* GLITCH_FILTER1_INP input func */
  {507U, 1U}, 
  /* INMUX settings for pad PORT17:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_31_Y_IN input func */
  {31U, 2U}, 
  /* FlexCAN_0_RX input func */
  {188U, 2U}, 
  /* LIN_0_LIN0RX input func */
  {200U, 1U}, 
  /* EMIOS0_E0UC_5_G_IN input func */
  {5U, 4U}, 
  /* GLITCH_FILTER1_INP input func */
  {507U, 4U}, 
  /* INMUX settings for pad PORT26:     {INMUX reg, PADSEL val} */
  /* FlexCAN_6_RX input func */
  {194U, 1U}, 
  /* SAI0_SAI0_SYNC_IN input func */
  {490U, 1U}, 
  /* EMIOS0_E0UC_29_Y_IN input func */
  {29U, 4U}, 
  /* INMUX settings for pad PORT37:     {INMUX reg, PADSEL val} */
  /* SIUL2_EIRQ7 input func */
  {151U, 1U}, 
  /* INMUX settings for pad PORT43:     {INMUX reg, PADSEL val} */
  /* FlexCAN_1_RX input func */
  {189U, 3U}, 
  /* FlexCAN_4_RX input func */
  {192U, 2U}, 
  /* EMIOS0_E0UC_1_G_IN input func */
  {1U, 5U}, 
  /* INMUX settings for pad PORT61:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_25_Y_IN input func */
  {25U, 2U}, 
  /* DSPI_1_dSS input func */
  {293U, 3U}, 
  /* ENET0_ENET0_TMR0_IN input func */
  {329U, 1U}, 
  /* INMUX settings for pad PORT66:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_18_Y_IN input func */
  {18U, 2U}, 
  /* SIUL2_EIRQ21 input func */
  {165U, 1U}, 
  /* DSPI_1_dSIN input func */
  {291U, 3U}, 
  /* INMUX settings for pad PORT67:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_19_Y_IN input func */
  {19U, 2U}, 
  /* FlexRay_FR_A_RX input func */
  {224U, 1U}, 
  /* INMUX settings for pad PORT72:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_22_X_IN input func */
  {22U, 3U}, 
  /* IIC_2_SDA2_IN input func */
  {270U, 1U}, 
  /* INMUX settings for pad PORT73:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_23_X_IN input func */
  {23U, 3U}, 
  /* FlexCAN_2_RX input func */
  {190U, 1U}, 
  /* FlexCAN_3_RX input func */
  {191U, 3U}, 
  /* IIC_2_SCL2_IN input func */
  {269U, 1U}, 
  /* INMUX settings for pad PORT77:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_20_Y_IN input func */
  {56U, 2U}, 
  /* ENET0_MII_0_RXD_3 input func */
  {454U, 1U}, 
  /* INMUX settings for pad PORT79:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_22_X_IN input func */
  {58U, 2U}, 
  /* DSPI_2_dSS input func */
  {296U, 2U}, 
  /* SPI_2_SCLK_2_IN input func */
  {307U, 1U}, 
  /* INMUX settings for pad PORT80:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_10_H_IN input func */
  {10U, 3U}, 
  /* SAI0_SAI0_MCLK_IN input func */
  {489U, 1U}, 
  /* INMUX settings for pad PORT85:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_22_X_IN input func */
  {22U, 4U}, 
  /* SAI0_SAI0_D0_IN input func */
  {491U, 1U}, 
  /* GLITCH_FILTER3_INP input func */
  {509U, 9U}, 
  /* INMUX settings for pad PORT88:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_15_H_IN input func */
  {15U, 3U}, 
  /* INMUX settings for pad PORT89:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_1_H_IN input func */
  {37U, 2U}, 
  /* FlexCAN_2_RX input func */
  {190U, 2U}, 
  /* FlexCAN_3_RX input func */
  {191U, 4U}, 
  /* EMIOS0_E0UC_14_H_IN input func */
  {14U, 5U}, 
  /* INMUX settings for pad PORT90:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_2_H_IN input func */
  {38U, 2U}, 
  /* EMIOS0_E0UC_19_Y_IN input func */
  {19U, 3U}, 
  /* INMUX settings for pad PORT94:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_27_Y_IN input func */
  {63U, 2U}, 
  /* ENET0_MII_RMII_0_MDIO_IN input func */
  {450U, 1U}, 
  /* INMUX settings for pad PORT95:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_4_H_IN input func */
  {40U, 2U}, 
  /* SIUL2_EIRQ13 input func */
  {157U, 1U}, 
  /* FlexCAN_1_RX input func */
  {189U, 4U}, 
  /* FlexCAN_4_RX input func */
  {192U, 3U}, 
  /* ENET0_MII_RMII_0_RX_DV input func */
  {457U, 1U}, 
  /* INMUX settings for pad PORT96:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_23_X_IN input func */
  {59U, 2U}, 
  /* INMUX settings for pad PORT97:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_24_X_IN input func */
  {60U, 2U}, 
  /* SIUL2_EIRQ14 input func */
  {158U, 1U}, 
  /* FlexCAN_5_RX input func */
  {193U, 2U}, 
  /* ENET0_MII_RMII_0_TX_CLK_IN input func */
  {449U, 1U}, 
  /* INMUX settings for pad PORT98:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_11_H_IN input func */
  {47U, 2U}, 
  /* INMUX settings for pad PORT99:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_12_H_IN input func */
  {48U, 2U}, 
  /* FlexCAN_7_RX input func */
  {195U, 1U}, 
  /* DSPI_3_dSS input func */
  {299U, 1U}, 
  /* INMUX settings for pad PORT102:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_15_H_IN input func */
  {51U, 2U}, 
  /* EMIOS0_E0UC_3_G_IN input func */
  {3U, 6U}, 
  /* INMUX settings for pad PORT103:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_16_X_IN input func */
  {52U, 2U}, 
  /* EMIOS1_E1UC_30_Y_IN input func */
  {66U, 3U}, 
  /* LIN_6_LIN6RX input func */
  {206U, 1U}, 
  /* GLITCH_FILTER3_INP input func */
  {509U, 2U}, 
  /* INMUX settings for pad PORT107:    {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_25_Y_IN input func */
  {25U, 3U}, 
  /* SPI_0_SS_0 input func */
  {302U, 1U}, 
  /* SPI_2_SS_2 input func */
  {308U, 1U}, 
  /* INMUX settings for pad PORT108:    {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_26_Y_IN input func */
  {26U, 3U}, 
  /* INMUX settings for pad PORT109:    {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_27_Y_IN input func */
  {27U, 3U}, 
  /* SPI_0_SCLK_0_IN input func */
  {301U, 2U}, 
  /* INMUX settings for pad PORT110:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_0_X_IN input func */
  {36U, 2U}, 
  /* SPI_2_SIN_2 input func */
  {306U, 1U}, 
  /* INMUX settings for pad PORT111:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_1_H_IN input func */
  {37U, 3U}, 
  /* LIN_8_LIN8RX input func */
  {208U, 1U}, 
  /* INMUX settings for pad PORT112:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_2_H_IN input func */
  {38U, 3U}, 
  /* DSPI_1_dSIN input func */
  {291U, 4U}, 
  /* INMUX settings for pad PORT113:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_3_H_IN input func */
  {39U, 3U}, 
  /* INMUX settings for pad PORT114:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_4_H_IN input func */
  {40U, 3U}, 
  /* DSPI_1_dSCLK_IN input func */
  {292U, 3U}, 
  /* INMUX settings for pad PORT124:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_25_Y_IN input func */
  {61U, 3U}, 
  /* DSPI_3_dSCLK_IN input func */
  {298U, 2U}, 
  /* INMUX settings for pad PORT128:    {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_28_Y_IN input func */
  {28U, 3U}, 
  /* IIC_1_SDA1_IN input func */
  {268U, 2U}, 
  /* GLITCH_FILTER0_INP input func */
  {506U, 2U}, 
  /* INMUX settings for pad PORT129:    {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_29_Y_IN input func */
  {29U, 3U}, 
  /* LIN_8_LIN8RX input func */
  {208U, 2U}, 
  /* IIC_1_SCL1_IN input func */
  {267U, 2U}, 
  /* GLITCH_FILTER0_INP input func */
  {506U, 4U}, 
  /* INMUX settings for pad PORT130:    {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_30_Y_IN input func */
  {30U, 4U}, 
  /* IIC_2_SDA2_IN input func */
  {270U, 2U}, 
  /* GLITCH_FILTER1_INP input func */
  {507U, 3U}, 
  /* INMUX settings for pad PORT131:    {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_31_Y_IN input func */
  {31U, 4U}, 
  /* LIN_9_LIN9RX input func */
  {209U, 1U}, 
  /* IIC_2_SCL2_IN input func */
  {269U, 2U}, 
  /* GLITCH_FILTER1_INP input func */
  {507U, 6U}, 
  /* INMUX settings for pad PORT142:    {INMUX reg, PADSEL val} */
  /* SPI_0_SIN_0 input func */
  {300U, 2U}, 
  /* SAI2_SAI2_D0_IN input func */
  {505U, 2U}, 
  /* INMUX settings for pad PORT144:    {INMUX reg, PADSEL val} */
  /* SAI2_SAI2_SYNC_IN input func */
  {504U, 2U}, 
  /* INMUX settings for pad PORT145:    {INMUX reg, PADSEL val} */
  /* SPI_1_SIN_1 input func */
  {303U, 1U}, 
  /* SAI2_SAI2_BCLK_IN input func */
  {502U, 1U}, 
  /* INMUX settings for pad PORT146:    {INMUX reg, PADSEL val} */
  /* SPI_1_SS_1 input func */
  {305U, 2U}, 
  /* SPI_2_SS_2 input func */
  {308U, 3U}, 
  /* SPI_3_SS_3 input func */
  {311U, 2U}, 
  /* SAI1_SAI1_D0_IN input func */
  {498U, 1U}, 
  /* INMUX settings for pad PORT157:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_15_H_IN input func */
  {51U, 3U}, 
  /* FlexCAN_1_RX input func */
  {189U, 5U}, 
  /* FlexCAN_4_RX input func */
  {192U, 5U}, 
  /* FlexCAN_6_RX input func */
  {194U, 2U}, 
  /* INMUX settings for pad PORT158:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_14_H_IN input func */
  {50U, 3U}
[!ENDVAR!]


[!VAR "INPUT_INMUX_2"!]
  /* INMUX settings for pad not available:  */
  { NO_INPUTMUX_U16, 0U},
  /* INMUX settings for pad PORT0:      {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_0_X_IN input func */
  {0U, 2U}, 
  /* EMIOS0_E0UC_13_H_IN input func */
  {13U, 2U}, 
  /* FlexCAN_1_RX input func */
  {189U, 1U}, 
  /* INMUX settings for pad PORT1:      {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_1_G_IN input func */
  {1U, 2U}, 
  /* FlexCAN_3_RX input func */
  {191U, 1U}, 
  /* INMUX settings for pad PORT2:      {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_2_G_IN input func */
  {2U, 2U}, 
  /* INMUX settings for pad PORT3:      {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_3_G_IN input func */
  {3U, 2U}, 
  /* SIUL2_EIRQ0 input func */
  {144U, 1U}, 
  /* ENET0_MII_0_RX_CLK input func */
  {448U, 1U}, 
  /* INMUX settings for pad PORT4:      {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_4_G_IN input func */
  {4U, 2U}, 
  /* LIN_5_LIN5RX input func */
  {205U, 1U}, 
  /* DSPI_1_dSS input func */
  {293U, 1U}, 
  /* EMIOS0_E0UC_24_X_IN input func */
  {24U, 5U}, 
  /* INMUX settings for pad PORT5:      {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_5_G_IN input func */
  {5U, 2U}, 
  /* INMUX settings for pad PORT6:      {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_6_G_IN input func */
  {6U, 2U}, 
  /* SIUL2_EIRQ1 input func */
  {145U, 1U}, 
  /* LIN_4_LIN4RX input func */
  {204U, 1U}, 
  /* INMUX settings for pad PORT7:      {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_7_G_IN input func */
  {7U, 2U}, 
  /* SIUL2_EIRQ2 input func */
  {146U, 1U}, 
  /* ENET0_MII_0_RXD_2 input func */
  {453U, 1U}, 
  /* INMUX settings for pad PORT8:      {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_8_X_IN input func */
  {8U, 2U}, 
  /* EMIOS0_E0UC_14_H_IN input func */
  {14U, 2U}, 
  /* SIUL2_EIRQ3 input func */
  {147U, 1U}, 
  /* LIN_3_LIN3RX input func */
  {203U, 1U}, 
  /* ENET0_MII_RMII_0_RXD_1 input func */
  {452U, 1U}, 
  /* INMUX settings for pad PORT9:      {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_9_H_IN input func */
  {9U, 2U}, 
  /* ENET0_MII_RMII_0_RXD_0 input func */
  {451U, 1U}, 
  /* INMUX settings for pad PORT10:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_10_H_IN input func */
  {10U, 2U}, 
  /* IIC_0_SDA0_IN input func */
  {266U, 1U}, 
  /* DSPI_1_dSIN input func */
  {291U, 1U}, 
  /* ENET0_MII_0_COL input func */
  {456U, 1U}, 
  /* INMUX settings for pad PORT11:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_11_H_IN input func */
  {11U, 2U}, 
  /* SIUL2_EIRQ16 input func */
  {160U, 1U}, 
  /* LIN_2_LIN2RX input func */
  {202U, 1U}, 
  /* IIC_0_SCL0_IN input func */
  {265U, 1U}, 
  /* ENET0_MII_RMII_0_RX_ER input func */
  {455U, 1U}, 
  /* INMUX settings for pad PORT12:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_28_Y_IN input func */
  {28U, 2U}, 
  /* SIUL2_EIRQ17 input func */
  {161U, 1U}, 
  /* DSPI_0_dSIN input func */
  {288U, 1U}, 
  /* EMIOS0_E0UC_26_Y_IN input func */
  {26U, 4U}, 
  /* GLITCH_FILTER0_INP input func */
  {506U, 1U}, 
  /* INMUX settings for pad PORT13:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_29_Y_IN input func */
  {29U, 2U}, 
  /* EMIOS0_E0UC_25_Y_IN input func */
  {25U, 4U}, 
  /* GLITCH_FILTER0_INP input func */
  {506U, 3U}, 
  /* INMUX settings for pad PORT14:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_0_X_IN input func */
  {0U, 3U}, 
  /* SIUL2_EIRQ4 input func */
  {148U, 1U}, 
  /* DSPI_0_dSCLK_IN input func */
  {289U, 1U}, 
  /* DSPI_0_dSS input func */
  {290U, 1U}, 
  /* EMIOS0_E0UC_23_X_IN input func */
  {23U, 5U}, 
  /* INMUX settings for pad PORT15:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_1_G_IN input func */
  {1U, 3U}, 
  /* FlexCAN_0_RX input func */
  {188U, 1U}, 
  /* DSPI_0_dSCLK_IN input func */
  {289U, 2U}, 
  /* DSPI_0_dSS input func */
  {290U, 2U}, 
  /* EMIOS0_E0UC_21_Y_IN input func */
  {21U, 3U}, 
  /* INMUX settings for pad PORT16:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_30_Y_IN input func */
  {30U, 2U}, 
  /* EMIOS0_E0UC_4_G_IN input func */
  {4U, 5U}, 
  /* GLITCH_FILTER1_INP input func */
  {507U, 1U}, 
  /* INMUX settings for pad PORT17:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_31_Y_IN input func */
  {31U, 2U}, 
  /* FlexCAN_0_RX input func */
  {188U, 2U}, 
  /* LIN_0_LIN0RX input func */
  {200U, 1U}, 
  /* EMIOS0_E0UC_5_G_IN input func */
  {5U, 4U}, 
  /* GLITCH_FILTER1_INP input func */
  {507U, 4U}, 
  /* INMUX settings for pad PORT18:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_30_Y_IN input func */
  {30U, 3U}, 
  /* IIC_0_SDA0_IN input func */
  {266U, 2U}, 
  /* GLITCH_FILTER1_INP input func */
  {507U, 2U}, 
  /* INMUX settings for pad PORT19:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_31_Y_IN input func */
  {31U, 3U}, 
  /* LIN_0_LIN0RX input func */
  {200U, 2U}, 
  /* IIC_0_SCL0_IN input func */
  {265U, 2U}, 
  /* EMIOS0_E0UC_8_X_IN input func */
  {8U, 3U}, 
  /* GLITCH_FILTER1_INP input func */
  {507U, 5U}, 
  /* INMUX settings for pad PORT26:     {INMUX reg, PADSEL val} */
  /* FlexCAN_6_RX input func */
  {194U, 1U}, 
  /* SAI0_SAI0_SYNC_IN input func */
  {490U, 1U}, 
  /* EMIOS0_E0UC_29_Y_IN input func */
  {29U, 4U}, 
  /* INMUX settings for pad PORT27:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_3_G_IN input func */
  {3U, 3U}, 
  /* DSPI_0_dSS input func */
  {290U, 3U}, 
  /* INMUX settings for pad PORT28:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_4_G_IN input func */
  {4U, 3U}, 
  /* INMUX settings for pad PORT29:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_5_G_IN input func */
  {5U, 3U}, 
  /* INMUX settings for pad PORT30:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_6_G_IN input func */
  {6U, 3U}, 
  /* INMUX settings for pad PORT31:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_7_G_IN input func */
  {7U, 3U}, 
  /* INMUX settings for pad PORT34:     {INMUX reg, PADSEL val} */
  /* SIUL2_EIRQ5 input func */
  {149U, 1U}, 
  /* DSPI_1_dSCLK_IN input func */
  {292U, 1U}, 
  /* INMUX settings for pad PORT35:     {INMUX reg, PADSEL val} */
  /* SIUL2_EIRQ6 input func */
  {150U, 1U}, 
  /* FlexCAN_1_RX input func */
  {189U, 2U}, 
  /* FlexCAN_4_RX input func */
  {192U, 1U}, 
  /* DSPI_1_dSS input func */
  {293U, 2U}, 
  /* INMUX settings for pad PORT36:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_31_Y_IN input func */
  {67U, 2U}, 
  /* SIUL2_EIRQ18 input func */
  {162U, 1U}, 
  /* FlexCAN_3_RX input func */
  {191U, 2U}, 
  /* DSPI_1_dSIN input func */
  {291U, 2U}, 
  /* GLITCH_FILTER3_INP input func */
  {509U, 5U}, 
  /* INMUX settings for pad PORT37:     {INMUX reg, PADSEL val} */
  /* SIUL2_EIRQ7 input func */
  {151U, 1U}, 
  /* INMUX settings for pad PORT38:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_28_Y_IN input func */
  {64U, 2U}, 
  /* EMIOS0_E0UC_17_Y_IN input func */
  {17U, 3U}, 
  /* GLITCH_FILTER2_INP input func */
  {508U, 1U}, 
  /* INMUX settings for pad PORT39:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_29_Y_IN input func */
  {65U, 2U}, 
  /* LIN_1_LIN1RX input func */
  {201U, 1U}, 
  /* EMIOS0_E0UC_18_Y_IN input func */
  {18U, 3U}, 
  /* GLITCH_FILTER2_INP input func */
  {508U, 4U}, 
  /* INMUX settings for pad PORT40:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_3_G_IN input func */
  {3U, 4U}, 
  /* INMUX settings for pad PORT41:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_7_G_IN input func */
  {7U, 4U}, 
  /* LIN_2_LIN2RX input func */
  {202U, 2U}, 
  /* INMUX settings for pad PORT43:     {INMUX reg, PADSEL val} */
  /* FlexCAN_1_RX input func */
  {189U, 3U}, 
  /* FlexCAN_4_RX input func */
  {192U, 2U}, 
  /* EMIOS0_E0UC_1_G_IN input func */
  {1U, 5U}, 
  /* INMUX settings for pad PORT44:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_12_H_IN input func */
  {12U, 2U}, 
  /* SIUL2_EIRQ19 input func */
  {163U, 1U}, 
  /* DSPI_2_dSIN input func */
  {294U, 1U}, 
  /* INMUX settings for pad PORT45:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_13_H_IN input func */
  {13U, 3U}, 
  /* INMUX settings for pad PORT46:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_14_H_IN input func */
  {14U, 3U}, 
  /* SIUL2_EIRQ8 input func */
  {152U, 1U}, 
  /* DSPI_2_dSCLK_IN input func */
  {295U, 1U}, 
  /* INMUX settings for pad PORT47:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_15_H_IN input func */
  {15U, 2U}, 
  /* SIUL2_EIRQ20 input func */
  {164U, 1U}, 
  /* DSPI_2_dSS input func */
  {296U, 1U}, 
  /* FlexCAN_4_RX input func */
  {192U, 7U}, 
  /* INMUX settings for pad PORT60:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_24_X_IN input func */
  {24U, 2U}, 
  /* INMUX settings for pad PORT61:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_25_Y_IN input func */
  {25U, 2U}, 
  /* DSPI_1_dSS input func */
  {293U, 3U}, 
  /* ENET0_ENET0_TMR0_IN input func */
  {329U, 1U}, 
  /* INMUX settings for pad PORT62:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_26_Y_IN input func */
  {26U, 2U}, 
  /* INMUX settings for pad PORT63:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_27_Y_IN input func */
  {27U, 2U}, 
  /* INMUX settings for pad PORT64:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_16_X_IN input func */
  {16U, 2U}, 
  /* FlexCAN_5_RX input func */
  {193U, 1U}, 
  /* LIN_11_LIN11RX input func */
  {211U, 1U}, 
  /* IIC_1_SCL1_IN input func */
  {267U, 1U}, 
  /* INMUX settings for pad PORT65:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_17_Y_IN input func */
  {17U, 2U}, 
  /* IIC_1_SDA1_IN input func */
  {268U, 1U}, 
  /* INMUX settings for pad PORT66:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_18_Y_IN input func */
  {18U, 2U}, 
  /* SIUL2_EIRQ21 input func */
  {165U, 1U}, 
  /* DSPI_1_dSIN input func */
  {291U, 3U}, 
  /* INMUX settings for pad PORT67:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_19_Y_IN input func */
  {19U, 2U}, 
  /* FlexRay_FR_A_RX input func */
  {224U, 1U}, 
  /* INMUX settings for pad PORT68:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_20_Y_IN input func */
  {20U, 2U}, 
  /* SIUL2_EIRQ9 input func */
  {153U, 1U}, 
  /* DSPI_1_dSCLK_IN input func */
  {292U, 2U}, 
  /* INMUX settings for pad PORT69:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_21_Y_IN input func */
  {21U, 2U}, 
  /* FlexRay_FR_B_RX input func */
  {225U, 1U}, 
  /* DSPI_1_dSS input func */
  {293U, 4U}, 
  /* INMUX settings for pad PORT70:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_22_X_IN input func */
  {22U, 2U}, 
  /* SIUL2_EIRQ22 input func */
  {166U, 1U}, 
  /* INMUX settings for pad PORT71:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_23_X_IN input func */
  {23U, 2U}, 
  /* SIUL2_EIRQ23 input func */
  {167U, 1U}, 
  /* INMUX settings for pad PORT72:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_22_X_IN input func */
  {22U, 3U}, 
  /* IIC_2_SDA2_IN input func */
  {270U, 1U}, 
  /* INMUX settings for pad PORT73:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_23_X_IN input func */
  {23U, 3U}, 
  /* FlexCAN_2_RX input func */
  {190U, 1U}, 
  /* FlexCAN_3_RX input func */
  {191U, 3U}, 
  /* IIC_2_SCL2_IN input func */
  {269U, 1U}, 
  /* INMUX settings for pad PORT74:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_30_Y_IN input func */
  {66U, 2U}, 
  /* SIUL2_EIRQ10 input func */
  {154U, 1U}, 
  /* IIC_3_SDA3_IN input func */
  {272U, 1U}, 
  /* GLITCH_FILTER3_INP input func */
  {509U, 1U}, 
  /* INMUX settings for pad PORT75:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_24_X_IN input func */
  {24U, 3U}, 
  /* LIN_3_LIN3RX input func */
  {203U, 2U}, 
  /* IIC_3_SCL3_IN input func */
  {271U, 1U}, 
  /* INMUX settings for pad PORT76:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_19_Y_IN input func */
  {55U, 2U}, 
  /* SIUL2_EIRQ11 input func */
  {155U, 1U}, 
  /* DSPI_2_dSIN input func */
  {294U, 2U}, 
  /* ENET0_MII_0_CRS input func */
  {458U, 1U}, 
  /* INMUX settings for pad PORT77:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_20_Y_IN input func */
  {56U, 2U}, 
  /* ENET0_MII_0_RXD_3 input func */
  {454U, 1U}, 
  /* INMUX settings for pad PORT78:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_21_Y_IN input func */
  {57U, 2U}, 
  /* SIUL2_EIRQ12 input func */
  {156U, 1U}, 
  /* DSPI_2_dSCLK_IN input func */
  {295U, 2U}, 
  /* INMUX settings for pad PORT79:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_22_X_IN input func */
  {58U, 2U}, 
  /* DSPI_2_dSS input func */
  {296U, 2U}, 
  /* SPI_2_SCLK_2_IN input func */
  {307U, 1U}, 
  /* INMUX settings for pad PORT80:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_10_H_IN input func */
  {10U, 3U}, 
  /* SAI0_SAI0_MCLK_IN input func */
  {489U, 1U}, 
  /* INMUX settings for pad PORT81:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_11_H_IN input func */
  {11U, 3U}, 
  /* SAI0_SAI0_BCLK_IN input func */
  {488U, 1U}, 
  /* INMUX settings for pad PORT82:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_12_H_IN input func */
  {12U, 3U}, 
  /* DSPI_2_dSS input func */
  {296U, 3U}, 
  /* SAI0_SAI0_D3_IN input func */
  {494U, 1U}, 
  /* GLITCH_FILTER0_INP input func */
  {506U, 5U}, 
  /* INMUX settings for pad PORT83:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_13_H_IN input func */
  {13U, 4U}, 
  /* SAI0_SAI0_D2_IN input func */
  {493U, 1U}, 
  /* GLITCH_FILTER1_INP input func */
  {507U, 7U}, 
  /* INMUX settings for pad PORT84:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_14_H_IN input func */
  {14U, 4U}, 
  /* SAI0_SAI0_D1_IN input func */
  {492U, 1U}, 
  /* GLITCH_FILTER2_INP input func */
  {508U, 7U}, 
  /* INMUX settings for pad PORT85:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_22_X_IN input func */
  {22U, 4U}, 
  /* SAI0_SAI0_D0_IN input func */
  {491U, 1U}, 
  /* GLITCH_FILTER3_INP input func */
  {509U, 9U}, 
  /* INMUX settings for pad PORT86:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_23_X_IN input func */
  {23U, 4U}, 
  /* SAI1_SAI1_SYNC_IN input func */
  {497U, 1U}, 
  /* EMIOS0_E0UC_30_Y_IN input func */
  {30U, 5U}, 
  /* INMUX settings for pad PORT87:     {INMUX reg, PADSEL val} */
  /* SPI_0_SCLK_0_IN input func */
  {301U, 1U}, 
  /* SAI1_SAI1_MCLK_IN input func */
  {496U, 1U}, 
  /* INMUX settings for pad PORT88:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_15_H_IN input func */
  {15U, 3U}, 
  /* INMUX settings for pad PORT89:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_1_H_IN input func */
  {37U, 2U}, 
  /* FlexCAN_2_RX input func */
  {190U, 2U}, 
  /* FlexCAN_3_RX input func */
  {191U, 4U}, 
  /* EMIOS0_E0UC_14_H_IN input func */
  {14U, 5U}, 
  /* INMUX settings for pad PORT90:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_2_H_IN input func */
  {38U, 2U}, 
  /* EMIOS0_E0UC_19_Y_IN input func */
  {19U, 3U}, 
  /* INMUX settings for pad PORT91:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_3_H_IN input func */
  {39U, 2U}, 
  /* LIN_4_LIN4RX input func */
  {204U, 2U}, 
  /* EMIOS0_E0UC_20_Y_IN input func */
  {20U, 3U}, 
  /* INMUX settings for pad PORT92:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_25_Y_IN input func */
  {61U, 2U}, 
  /* EMIOS0_E0UC_16_X_IN input func */
  {16U, 3U}, 
  /* INMUX settings for pad PORT93:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_26_Y_IN input func */
  {62U, 2U}, 
  /* LIN_5_LIN5RX input func */
  {205U, 2U}, 
  /* EMIOS0_E0UC_22_X_IN input func */
  {22U, 5U}, 
  /* INMUX settings for pad PORT94:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_27_Y_IN input func */
  {63U, 2U}, 
  /* ENET0_MII_RMII_0_MDIO_IN input func */
  {450U, 1U}, 
  /* INMUX settings for pad PORT95:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_4_H_IN input func */
  {40U, 2U}, 
  /* SIUL2_EIRQ13 input func */
  {157U, 1U}, 
  /* FlexCAN_1_RX input func */
  {189U, 4U}, 
  /* FlexCAN_4_RX input func */
  {192U, 3U}, 
  /* ENET0_MII_RMII_0_RX_DV input func */
  {457U, 1U}, 
  /* INMUX settings for pad PORT96:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_23_X_IN input func */
  {59U, 2U}, 
  /* INMUX settings for pad PORT97:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_24_X_IN input func */
  {60U, 2U}, 
  /* SIUL2_EIRQ14 input func */
  {158U, 1U}, 
  /* FlexCAN_5_RX input func */
  {193U, 2U}, 
  /* ENET0_MII_RMII_0_TX_CLK_IN input func */
  {449U, 1U}, 
  /* INMUX settings for pad PORT98:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_11_H_IN input func */
  {47U, 2U}, 
  /* INMUX settings for pad PORT99:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_12_H_IN input func */
  {48U, 2U}, 
  /* FlexCAN_7_RX input func */
  {195U, 1U}, 
  /* DSPI_3_dSS input func */
  {299U, 1U}, 
  /* INMUX settings for pad PORT100:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_13_H_IN input func */
  {49U, 2U}, 
  /* DSPI_3_dSCLK_IN input func */
  {298U, 1U}, 
  /* INMUX settings for pad PORT101:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_14_H_IN input func */
  {50U, 2U}, 
  /* LIN_10_LIN10RX input func */
  {210U, 1U}, 
  /* DSPI_3_dSIN input func */
  {297U, 1U}, 
  /* EMIOS0_E0UC_2_G_IN input func */
  {2U, 4U}, 
  /* INMUX settings for pad PORT102:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_15_H_IN input func */
  {51U, 2U}, 
  /* EMIOS0_E0UC_3_G_IN input func */
  {3U, 6U}, 
  /* INMUX settings for pad PORT103:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_16_X_IN input func */
  {52U, 2U}, 
  /* EMIOS1_E1UC_30_Y_IN input func */
  {66U, 3U}, 
  /* LIN_6_LIN6RX input func */
  {206U, 1U}, 
  /* GLITCH_FILTER3_INP input func */
  {509U, 2U}, 
  /* INMUX settings for pad PORT104:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_17_Y_IN input func */
  {53U, 2U}, 
  /* SIUL2_EIRQ15 input func */
  {159U, 1U}, 
  /* DSPI_2_dSS input func */
  {296U, 4U}, 
  /* INMUX settings for pad PORT105:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_18_Y_IN input func */
  {54U, 2U}, 
  /* FlexCAN_7_RX input func */
  {195U, 2U}, 
  /* LIN_7_LIN7RX input func */
  {207U, 1U}, 
  /* DSPI_2_dSCLK_IN input func */
  {295U, 3U}, 
  /* EMIOS0_E0UC_0_X_IN input func */
  {0U, 5U}, 
  /* INMUX settings for pad PORT106:    {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_24_X_IN input func */
  {24U, 4U}, 
  /* EMIOS1_E1UC_31_Y_IN input func */
  {67U, 3U}, 
  /* SPI_0_SIN_0 input func */
  {300U, 1U}, 
  /* GLITCH_FILTER3_INP input func */
  {509U, 6U}, 
  /* INMUX settings for pad PORT107:    {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_25_Y_IN input func */
  {25U, 3U}, 
  /* SPI_0_SS_0 input func */
  {302U, 1U}, 
  /* SPI_2_SS_2 input func */
  {308U, 1U}, 
  /* INMUX settings for pad PORT108:    {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_26_Y_IN input func */
  {26U, 3U}, 
  /* INMUX settings for pad PORT109:    {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_27_Y_IN input func */
  {27U, 3U}, 
  /* SPI_0_SCLK_0_IN input func */
  {301U, 2U}, 
  /* INMUX settings for pad PORT110:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_0_X_IN input func */
  {36U, 2U}, 
  /* SPI_2_SIN_2 input func */
  {306U, 1U}, 
  /* INMUX settings for pad PORT111:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_1_H_IN input func */
  {37U, 3U}, 
  /* LIN_8_LIN8RX input func */
  {208U, 1U}, 
  /* INMUX settings for pad PORT112:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_2_H_IN input func */
  {38U, 3U}, 
  /* DSPI_1_dSIN input func */
  {291U, 4U}, 
  /* INMUX settings for pad PORT113:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_3_H_IN input func */
  {39U, 3U}, 
  /* INMUX settings for pad PORT114:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_4_H_IN input func */
  {40U, 3U}, 
  /* DSPI_1_dSCLK_IN input func */
  {292U, 3U}, 
  /* INMUX settings for pad PORT115:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_5_H_IN input func */
  {41U, 2U}, 
  /* DSPI_1_dSS input func */
  {293U, 5U}, 
  /* INMUX settings for pad PORT116:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_6_H_IN input func */
  {42U, 2U}, 
  /* IIC_3_SCL3_IN input func */
  {271U, 2U}, 
  /* INMUX settings for pad PORT117:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_7_H_IN input func */
  {43U, 2U}, 
  /* IIC_3_SDA3_IN input func */
  {272U, 2U}, 
  /* SPI_3_SIN_3 input func */
  {309U, 1U}, 
  /* INMUX settings for pad PORT118:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_8_X_IN input func */
  {44U, 2U}, 
  /* SPI_3_SCLK_3_IN input func */
  {310U, 1U}, 
  /* INMUX settings for pad PORT119:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_9_H_IN input func */
  {45U, 2U}, 
  /* SPI_3_SS_3 input func */
  {311U, 1U}, 
  /* INMUX settings for pad PORT120:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_10_H_IN input func */
  {46U, 2U}, 
  /* INMUX settings for pad PORT123:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_5_H_IN input func */
  {41U, 3U}, 
  /* SPI_0_SS_0 input func */
  {302U, 2U}, 
  /* INMUX settings for pad PORT124:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_25_Y_IN input func */
  {61U, 3U}, 
  /* DSPI_3_dSCLK_IN input func */
  {298U, 2U}, 
  /* INMUX settings for pad PORT125:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_26_Y_IN input func */
  {62U, 3U}, 
  /* DSPI_3_dSS input func */
  {299U, 2U}, 
  /* INMUX settings for pad PORT126:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_27_Y_IN input func */
  {63U, 3U}, 
  /* SPI_0_SCLK_0_IN input func */
  {301U, 3U}, 
  /* FCCU_EIN_ERR input func */
  {501U, 1U}, 
  /* INMUX settings for pad PORT127:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_17_Y_IN input func */
  {53U, 3U}, 
  /* INMUX settings for pad PORT128:    {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_28_Y_IN input func */
  {28U, 3U}, 
  /* IIC_1_SDA1_IN input func */
  {268U, 2U}, 
  /* GLITCH_FILTER0_INP input func */
  {506U, 2U}, 
  /* INMUX settings for pad PORT129:    {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_29_Y_IN input func */
  {29U, 3U}, 
  /* LIN_8_LIN8RX input func */
  {208U, 2U}, 
  /* IIC_1_SCL1_IN input func */
  {267U, 2U}, 
  /* GLITCH_FILTER0_INP input func */
  {506U, 4U}, 
  /* INMUX settings for pad PORT130:    {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_30_Y_IN input func */
  {30U, 4U}, 
  /* IIC_2_SDA2_IN input func */
  {270U, 2U}, 
  /* GLITCH_FILTER1_INP input func */
  {507U, 3U}, 
  /* INMUX settings for pad PORT131:    {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_31_Y_IN input func */
  {31U, 4U}, 
  /* LIN_9_LIN9RX input func */
  {209U, 1U}, 
  /* IIC_2_SCL2_IN input func */
  {269U, 2U}, 
  /* GLITCH_FILTER1_INP input func */
  {507U, 6U}, 
  /* INMUX settings for pad PORT132:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_28_Y_IN input func */
  {64U, 3U}, 
  /* GLITCH_FILTER2_INP input func */
  {508U, 2U}, 
  /* INMUX settings for pad PORT133:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_29_Y_IN input func */
  {65U, 3U}, 
  /* SPI_0_SCLK_0_IN input func */
  {301U, 4U}, 
  /* GLITCH_FILTER2_INP input func */
  {508U, 5U}, 
  /* INMUX settings for pad PORT134:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_30_Y_IN input func */
  {66U, 4U}, 
  /* SPI_0_SS_0 input func */
  {302U, 3U}, 
  /* SPI_1_SS_1 input func */
  {305U, 1U}, 
  /* SPI_2_SS_2 input func */
  {308U, 2U}, 
  /* GLITCH_FILTER3_INP input func */
  {509U, 3U}, 
  /* INMUX settings for pad PORT135:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_31_Y_IN input func */
  {67U, 4U}, 
  /* GLITCH_FILTER3_INP input func */
  {509U, 7U}, 
  /* INMUX settings for pad PORT139:    {INMUX reg, PADSEL val} */
  /* DSPI_3_dSIN input func */
  {297U, 2U}, 
  /* ENET0_ENET0_TMR1_IN input func */
  {330U, 1U}, 
  /* INMUX settings for pad PORT140:    {INMUX reg, PADSEL val} */
  /* DSPI_2_dSS input func */
  {296U, 5U}, 
  /* DSPI_3_dSS input func */
  {299U, 3U}, 
  /* INMUX settings for pad PORT142:    {INMUX reg, PADSEL val} */
  /* SPI_0_SIN_0 input func */
  {300U, 2U}, 
  /* SAI2_SAI2_D0_IN input func */
  {505U, 2U}, 
  /* INMUX settings for pad PORT143:    {INMUX reg, PADSEL val} */
  /* SPI_0_SS_0 input func */
  {302U, 4U}, 
  /* SAI2_SAI2_MCLK_IN input func */
  {503U, 2U}, 
  /* INMUX settings for pad PORT144:    {INMUX reg, PADSEL val} */
  /* SAI2_SAI2_SYNC_IN input func */
  {504U, 2U}, 
  /* INMUX settings for pad PORT145:    {INMUX reg, PADSEL val} */
  /* SPI_1_SIN_1 input func */
  {303U, 1U}, 
  /* SAI2_SAI2_BCLK_IN input func */
  {502U, 1U}, 
  /* INMUX settings for pad PORT146:    {INMUX reg, PADSEL val} */
  /* SPI_1_SS_1 input func */
  {305U, 2U}, 
  /* SPI_2_SS_2 input func */
  {308U, 3U}, 
  /* SPI_3_SS_3 input func */
  {311U, 2U}, 
  /* SAI1_SAI1_D0_IN input func */
  {498U, 1U}, 
  /* INMUX settings for pad PORT147:    {INMUX reg, PADSEL val} */
  /* SAI1_SAI1_BCLK_IN input func */
  {495U, 1U}, 
  /* INMUX settings for pad PORT148:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_18_Y_IN input func */
  {54U, 3U}, 
  /* SPI_1_SCLK_1_IN input func */
  {304U, 1U}, 
  /* FCCU_EIN_ERR input func */
  {501U, 2U}
[!ENDVAR!]


[!VAR "INPUT_INMUX_3"!]
  /* INMUX settings for pad not available:  */
  { NO_INPUTMUX_U16, 0U},
  /* INMUX settings for pad PORT0:      {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_0_X_IN input func */
  {0U, 2U}, 
  /* EMIOS0_E0UC_13_H_IN input func */
  {13U, 2U}, 
  /* FlexCAN_1_RX input func */
  {189U, 1U}, 
  /* INMUX settings for pad PORT1:      {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_1_G_IN input func */
  {1U, 2U}, 
  /* FlexCAN_3_RX input func */
  {191U, 1U}, 
  /* INMUX settings for pad PORT2:      {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_2_G_IN input func */
  {2U, 2U}, 
  /* INMUX settings for pad PORT3:      {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_3_G_IN input func */
  {3U, 2U}, 
  /* SIUL2_EIRQ0 input func */
  {144U, 1U}, 
  /* ENET0_MII_0_RX_CLK input func */
  {448U, 1U}, 
  /* INMUX settings for pad PORT4:      {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_4_G_IN input func */
  {4U, 2U}, 
  /* LIN_5_LIN5RX input func */
  {205U, 1U}, 
  /* DSPI_1_dSS input func */
  {293U, 1U}, 
  /* EMIOS0_E0UC_24_X_IN input func */
  {24U, 5U}, 
  /* INMUX settings for pad PORT5:      {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_5_G_IN input func */
  {5U, 2U}, 
  /* INMUX settings for pad PORT6:      {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_6_G_IN input func */
  {6U, 2U}, 
  /* SIUL2_EIRQ1 input func */
  {145U, 1U}, 
  /* LIN_4_LIN4RX input func */
  {204U, 1U}, 
  /* INMUX settings for pad PORT7:      {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_7_G_IN input func */
  {7U, 2U}, 
  /* SIUL2_EIRQ2 input func */
  {146U, 1U}, 
  /* ENET0_MII_0_RXD_2 input func */
  {453U, 1U}, 
  /* INMUX settings for pad PORT8:      {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_8_X_IN input func */
  {8U, 2U}, 
  /* EMIOS0_E0UC_14_H_IN input func */
  {14U, 2U}, 
  /* SIUL2_EIRQ3 input func */
  {147U, 1U}, 
  /* LIN_3_LIN3RX input func */
  {203U, 1U}, 
  /* ENET0_MII_RMII_0_RXD_1 input func */
  {452U, 1U}, 
  /* INMUX settings for pad PORT9:      {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_9_H_IN input func */
  {9U, 2U}, 
  /* ENET0_MII_RMII_0_RXD_0 input func */
  {451U, 1U}, 
  /* INMUX settings for pad PORT10:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_10_H_IN input func */
  {10U, 2U}, 
  /* IIC_0_SDA0_IN input func */
  {266U, 1U}, 
  /* DSPI_1_dSIN input func */
  {291U, 1U}, 
  /* ENET0_MII_0_COL input func */
  {456U, 1U}, 
  /* INMUX settings for pad PORT11:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_11_H_IN input func */
  {11U, 2U}, 
  /* SIUL2_EIRQ16 input func */
  {160U, 1U}, 
  /* LIN_2_LIN2RX input func */
  {202U, 1U}, 
  /* IIC_0_SCL0_IN input func */
  {265U, 1U}, 
  /* ENET0_MII_RMII_0_RX_ER input func */
  {455U, 1U}, 
  /* INMUX settings for pad PORT12:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_28_Y_IN input func */
  {28U, 2U}, 
  /* SIUL2_EIRQ17 input func */
  {161U, 1U}, 
  /* DSPI_0_dSIN input func */
  {288U, 1U}, 
  /* EMIOS0_E0UC_26_Y_IN input func */
  {26U, 4U}, 
  /* GLITCH_FILTER0_INP input func */
  {506U, 1U}, 
  /* INMUX settings for pad PORT13:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_29_Y_IN input func */
  {29U, 2U}, 
  /* EMIOS0_E0UC_25_Y_IN input func */
  {25U, 4U}, 
  /* GLITCH_FILTER0_INP input func */
  {506U, 3U}, 
  /* INMUX settings for pad PORT14:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_0_X_IN input func */
  {0U, 3U}, 
  /* SIUL2_EIRQ4 input func */
  {148U, 1U}, 
  /* DSPI_0_dSCLK_IN input func */
  {289U, 1U}, 
  /* DSPI_0_dSS input func */
  {290U, 1U}, 
  /* EMIOS0_E0UC_23_X_IN input func */
  {23U, 5U}, 
  /* INMUX settings for pad PORT15:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_1_G_IN input func */
  {1U, 3U}, 
  /* FlexCAN_0_RX input func */
  {188U, 1U}, 
  /* DSPI_0_dSCLK_IN input func */
  {289U, 2U}, 
  /* DSPI_0_dSS input func */
  {290U, 2U}, 
  /* EMIOS0_E0UC_21_Y_IN input func */
  {21U, 3U}, 
  /* INMUX settings for pad PORT16:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_30_Y_IN input func */
  {30U, 2U}, 
  /* EMIOS0_E0UC_4_G_IN input func */
  {4U, 5U}, 
  /* GLITCH_FILTER1_INP input func */
  {507U, 1U}, 
  /* INMUX settings for pad PORT17:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_31_Y_IN input func */
  {31U, 2U}, 
  /* FlexCAN_0_RX input func */
  {188U, 2U}, 
  /* LIN_0_LIN0RX input func */
  {200U, 1U}, 
  /* EMIOS0_E0UC_5_G_IN input func */
  {5U, 4U}, 
  /* GLITCH_FILTER1_INP input func */
  {507U, 4U}, 
  /* INMUX settings for pad PORT18:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_30_Y_IN input func */
  {30U, 3U}, 
  /* IIC_0_SDA0_IN input func */
  {266U, 2U}, 
  /* GLITCH_FILTER1_INP input func */
  {507U, 2U}, 
  /* INMUX settings for pad PORT19:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_31_Y_IN input func */
  {31U, 3U}, 
  /* LIN_0_LIN0RX input func */
  {200U, 2U}, 
  /* IIC_0_SCL0_IN input func */
  {265U, 2U}, 
  /* EMIOS0_E0UC_8_X_IN input func */
  {8U, 3U}, 
  /* GLITCH_FILTER1_INP input func */
  {507U, 5U}, 
  /* INMUX settings for pad PORT26:     {INMUX reg, PADSEL val} */
  /* FlexCAN_6_RX input func */
  {194U, 1U}, 
  /* SAI0_SAI0_SYNC_IN input func */
  {490U, 1U}, 
  /* EMIOS0_E0UC_29_Y_IN input func */
  {29U, 4U}, 
  /* INMUX settings for pad PORT27:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_3_G_IN input func */
  {3U, 3U}, 
  /* DSPI_0_dSS input func */
  {290U, 3U}, 
  /* INMUX settings for pad PORT28:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_4_G_IN input func */
  {4U, 3U}, 
  /* INMUX settings for pad PORT29:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_5_G_IN input func */
  {5U, 3U}, 
  /* INMUX settings for pad PORT30:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_6_G_IN input func */
  {6U, 3U}, 
  /* INMUX settings for pad PORT31:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_7_G_IN input func */
  {7U, 3U}, 
  /* INMUX settings for pad PORT34:     {INMUX reg, PADSEL val} */
  /* SIUL2_EIRQ5 input func */
  {149U, 1U}, 
  /* DSPI_1_dSCLK_IN input func */
  {292U, 1U}, 
  /* INMUX settings for pad PORT35:     {INMUX reg, PADSEL val} */
  /* SIUL2_EIRQ6 input func */
  {150U, 1U}, 
  /* FlexCAN_1_RX input func */
  {189U, 2U}, 
  /* FlexCAN_4_RX input func */
  {192U, 1U}, 
  /* DSPI_1_dSS input func */
  {293U, 2U}, 
  /* INMUX settings for pad PORT36:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_31_Y_IN input func */
  {67U, 2U}, 
  /* SIUL2_EIRQ18 input func */
  {162U, 1U}, 
  /* FlexCAN_3_RX input func */
  {191U, 2U}, 
  /* DSPI_1_dSIN input func */
  {291U, 2U}, 
  /* GLITCH_FILTER3_INP input func */
  {509U, 5U}, 
  /* INMUX settings for pad PORT37:     {INMUX reg, PADSEL val} */
  /* SIUL2_EIRQ7 input func */
  {151U, 1U}, 
  /* INMUX settings for pad PORT38:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_28_Y_IN input func */
  {64U, 2U}, 
  /* EMIOS0_E0UC_17_Y_IN input func */
  {17U, 3U}, 
  /* GLITCH_FILTER2_INP input func */
  {508U, 1U}, 
  /* INMUX settings for pad PORT39:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_29_Y_IN input func */
  {65U, 2U}, 
  /* LIN_1_LIN1RX input func */
  {201U, 1U}, 
  /* EMIOS0_E0UC_18_Y_IN input func */
  {18U, 3U}, 
  /* GLITCH_FILTER2_INP input func */
  {508U, 4U}, 
  /* INMUX settings for pad PORT40:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_3_G_IN input func */
  {3U, 4U}, 
  /* INMUX settings for pad PORT41:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_7_G_IN input func */
  {7U, 4U}, 
  /* LIN_2_LIN2RX input func */
  {202U, 2U}, 
  /* INMUX settings for pad PORT43:     {INMUX reg, PADSEL val} */
  /* FlexCAN_1_RX input func */
  {189U, 3U}, 
  /* FlexCAN_4_RX input func */
  {192U, 2U}, 
  /* EMIOS0_E0UC_1_G_IN input func */
  {1U, 5U}, 
  /* INMUX settings for pad PORT44:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_12_H_IN input func */
  {12U, 2U}, 
  /* SIUL2_EIRQ19 input func */
  {163U, 1U}, 
  /* DSPI_2_dSIN input func */
  {294U, 1U}, 
  /* INMUX settings for pad PORT45:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_13_H_IN input func */
  {13U, 3U}, 
  /* INMUX settings for pad PORT46:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_14_H_IN input func */
  {14U, 3U}, 
  /* SIUL2_EIRQ8 input func */
  {152U, 1U}, 
  /* DSPI_2_dSCLK_IN input func */
  {295U, 1U}, 
  /* INMUX settings for pad PORT47:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_15_H_IN input func */
  {15U, 2U}, 
  /* SIUL2_EIRQ20 input func */
  {164U, 1U}, 
  /* DSPI_2_dSS input func */
  {296U, 1U}, 
  /* FlexCAN_4_RX input func */
  {192U, 7U}, 
  /* INMUX settings for pad PORT60:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_24_X_IN input func */
  {24U, 2U}, 
  /* INMUX settings for pad PORT61:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_25_Y_IN input func */
  {25U, 2U}, 
  /* DSPI_1_dSS input func */
  {293U, 3U}, 
  /* ENET0_ENET0_TMR0_IN input func */
  {329U, 1U}, 
  /* INMUX settings for pad PORT62:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_26_Y_IN input func */
  {26U, 2U}, 
  /* INMUX settings for pad PORT63:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_27_Y_IN input func */
  {27U, 2U}, 
  /* INMUX settings for pad PORT64:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_16_X_IN input func */
  {16U, 2U}, 
  /* FlexCAN_5_RX input func */
  {193U, 1U}, 
  /* LIN_11_LIN11RX input func */
  {211U, 1U}, 
  /* IIC_1_SCL1_IN input func */
  {267U, 1U}, 
  /* INMUX settings for pad PORT65:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_17_Y_IN input func */
  {17U, 2U}, 
  /* IIC_1_SDA1_IN input func */
  {268U, 1U}, 
  /* INMUX settings for pad PORT66:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_18_Y_IN input func */
  {18U, 2U}, 
  /* SIUL2_EIRQ21 input func */
  {165U, 1U}, 
  /* DSPI_1_dSIN input func */
  {291U, 3U}, 
  /* INMUX settings for pad PORT67:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_19_Y_IN input func */
  {19U, 2U}, 
  /* FlexRay_FR_A_RX input func */
  {224U, 1U}, 
  /* INMUX settings for pad PORT68:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_20_Y_IN input func */
  {20U, 2U}, 
  /* SIUL2_EIRQ9 input func */
  {153U, 1U}, 
  /* DSPI_1_dSCLK_IN input func */
  {292U, 2U}, 
  /* INMUX settings for pad PORT69:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_21_Y_IN input func */
  {21U, 2U}, 
  /* FlexRay_FR_B_RX input func */
  {225U, 1U}, 
  /* DSPI_1_dSS input func */
  {293U, 4U}, 
  /* INMUX settings for pad PORT70:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_22_X_IN input func */
  {22U, 2U}, 
  /* SIUL2_EIRQ22 input func */
  {166U, 1U}, 
  /* INMUX settings for pad PORT71:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_23_X_IN input func */
  {23U, 2U}, 
  /* SIUL2_EIRQ23 input func */
  {167U, 1U}, 
  /* INMUX settings for pad PORT72:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_22_X_IN input func */
  {22U, 3U}, 
  /* IIC_2_SDA2_IN input func */
  {270U, 1U}, 
  /* INMUX settings for pad PORT73:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_23_X_IN input func */
  {23U, 3U}, 
  /* FlexCAN_2_RX input func */
  {190U, 1U}, 
  /* FlexCAN_3_RX input func */
  {191U, 3U}, 
  /* IIC_2_SCL2_IN input func */
  {269U, 1U}, 
  /* INMUX settings for pad PORT74:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_30_Y_IN input func */
  {66U, 2U}, 
  /* SIUL2_EIRQ10 input func */
  {154U, 1U}, 
  /* IIC_3_SDA3_IN input func */
  {272U, 1U}, 
  /* GLITCH_FILTER3_INP input func */
  {509U, 1U}, 
  /* INMUX settings for pad PORT75:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_24_X_IN input func */
  {24U, 3U}, 
  /* LIN_3_LIN3RX input func */
  {203U, 2U}, 
  /* IIC_3_SCL3_IN input func */
  {271U, 1U}, 
  /* INMUX settings for pad PORT76:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_19_Y_IN input func */
  {55U, 2U}, 
  /* SIUL2_EIRQ11 input func */
  {155U, 1U}, 
  /* DSPI_2_dSIN input func */
  {294U, 2U}, 
  /* ENET0_MII_0_CRS input func */
  {458U, 1U}, 
  /* INMUX settings for pad PORT77:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_20_Y_IN input func */
  {56U, 2U}, 
  /* ENET0_MII_0_RXD_3 input func */
  {454U, 1U}, 
  /* INMUX settings for pad PORT78:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_21_Y_IN input func */
  {57U, 2U}, 
  /* SIUL2_EIRQ12 input func */
  {156U, 1U}, 
  /* DSPI_2_dSCLK_IN input func */
  {295U, 2U}, 
  /* INMUX settings for pad PORT79:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_22_X_IN input func */
  {58U, 2U}, 
  /* DSPI_2_dSS input func */
  {296U, 2U}, 
  /* SPI_2_SCLK_2_IN input func */
  {307U, 1U}, 
  /* INMUX settings for pad PORT80:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_10_H_IN input func */
  {10U, 3U}, 
  /* SAI0_SAI0_MCLK_IN input func */
  {489U, 1U}, 
  /* INMUX settings for pad PORT81:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_11_H_IN input func */
  {11U, 3U}, 
  /* SAI0_SAI0_BCLK_IN input func */
  {488U, 1U}, 
  /* INMUX settings for pad PORT82:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_12_H_IN input func */
  {12U, 3U}, 
  /* DSPI_2_dSS input func */
  {296U, 3U}, 
  /* SAI0_SAI0_D3_IN input func */
  {494U, 1U}, 
  /* GLITCH_FILTER0_INP input func */
  {506U, 5U}, 
  /* INMUX settings for pad PORT83:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_13_H_IN input func */
  {13U, 4U}, 
  /* SAI0_SAI0_D2_IN input func */
  {493U, 1U}, 
  /* GLITCH_FILTER1_INP input func */
  {507U, 7U}, 
  /* INMUX settings for pad PORT84:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_14_H_IN input func */
  {14U, 4U}, 
  /* SAI0_SAI0_D1_IN input func */
  {492U, 1U}, 
  /* GLITCH_FILTER2_INP input func */
  {508U, 7U}, 
  /* INMUX settings for pad PORT85:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_22_X_IN input func */
  {22U, 4U}, 
  /* SAI0_SAI0_D0_IN input func */
  {491U, 1U}, 
  /* GLITCH_FILTER3_INP input func */
  {509U, 9U}, 
  /* INMUX settings for pad PORT86:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_23_X_IN input func */
  {23U, 4U}, 
  /* SAI1_SAI1_SYNC_IN input func */
  {497U, 1U}, 
  /* EMIOS0_E0UC_30_Y_IN input func */
  {30U, 5U}, 
  /* INMUX settings for pad PORT87:     {INMUX reg, PADSEL val} */
  /* SPI_0_SCLK_0_IN input func */
  {301U, 1U}, 
  /* SAI1_SAI1_MCLK_IN input func */
  {496U, 1U}, 
  /* INMUX settings for pad PORT88:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_15_H_IN input func */
  {15U, 3U}, 
  /* INMUX settings for pad PORT89:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_1_H_IN input func */
  {37U, 2U}, 
  /* FlexCAN_2_RX input func */
  {190U, 2U}, 
  /* FlexCAN_3_RX input func */
  {191U, 4U}, 
  /* EMIOS0_E0UC_14_H_IN input func */
  {14U, 5U}, 
  /* INMUX settings for pad PORT90:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_2_H_IN input func */
  {38U, 2U}, 
  /* EMIOS0_E0UC_19_Y_IN input func */
  {19U, 3U}, 
  /* INMUX settings for pad PORT91:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_3_H_IN input func */
  {39U, 2U}, 
  /* LIN_4_LIN4RX input func */
  {204U, 2U}, 
  /* EMIOS0_E0UC_20_Y_IN input func */
  {20U, 3U}, 
  /* INMUX settings for pad PORT92:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_25_Y_IN input func */
  {61U, 2U}, 
  /* EMIOS0_E0UC_16_X_IN input func */
  {16U, 3U}, 
  /* INMUX settings for pad PORT93:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_26_Y_IN input func */
  {62U, 2U}, 
  /* LIN_5_LIN5RX input func */
  {205U, 2U}, 
  /* EMIOS0_E0UC_22_X_IN input func */
  {22U, 5U}, 
  /* INMUX settings for pad PORT94:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_27_Y_IN input func */
  {63U, 2U}, 
  /* ENET0_MII_RMII_0_MDIO_IN input func */
  {450U, 1U}, 
  /* INMUX settings for pad PORT95:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_4_H_IN input func */
  {40U, 2U}, 
  /* SIUL2_EIRQ13 input func */
  {157U, 1U}, 
  /* FlexCAN_1_RX input func */
  {189U, 4U}, 
  /* FlexCAN_4_RX input func */
  {192U, 3U}, 
  /* ENET0_MII_RMII_0_RX_DV input func */
  {457U, 1U}, 
  /* INMUX settings for pad PORT96:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_23_X_IN input func */
  {59U, 2U}, 
  /* INMUX settings for pad PORT97:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_24_X_IN input func */
  {60U, 2U}, 
  /* SIUL2_EIRQ14 input func */
  {158U, 1U}, 
  /* FlexCAN_5_RX input func */
  {193U, 2U}, 
  /* ENET0_MII_RMII_0_TX_CLK_IN input func */
  {449U, 1U}, 
  /* INMUX settings for pad PORT98:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_11_H_IN input func */
  {47U, 2U}, 
  /* INMUX settings for pad PORT99:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_12_H_IN input func */
  {48U, 2U}, 
  /* FlexCAN_7_RX input func */
  {195U, 1U}, 
  /* DSPI_3_dSS input func */
  {299U, 1U}, 
  /* INMUX settings for pad PORT100:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_13_H_IN input func */
  {49U, 2U}, 
  /* DSPI_3_dSCLK_IN input func */
  {298U, 1U}, 
  /* INMUX settings for pad PORT101:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_14_H_IN input func */
  {50U, 2U}, 
  /* LIN_10_LIN10RX input func */
  {210U, 1U}, 
  /* DSPI_3_dSIN input func */
  {297U, 1U}, 
  /* EMIOS0_E0UC_2_G_IN input func */
  {2U, 4U}, 
  /* INMUX settings for pad PORT102:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_15_H_IN input func */
  {51U, 2U}, 
  /* EMIOS0_E0UC_3_G_IN input func */
  {3U, 6U}, 
  /* INMUX settings for pad PORT103:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_16_X_IN input func */
  {52U, 2U}, 
  /* EMIOS1_E1UC_30_Y_IN input func */
  {66U, 3U}, 
  /* LIN_6_LIN6RX input func */
  {206U, 1U}, 
  /* GLITCH_FILTER3_INP input func */
  {509U, 2U}, 
  /* INMUX settings for pad PORT104:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_17_Y_IN input func */
  {53U, 2U}, 
  /* SIUL2_EIRQ15 input func */
  {159U, 1U}, 
  /* DSPI_2_dSS input func */
  {296U, 4U}, 
  /* INMUX settings for pad PORT105:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_18_Y_IN input func */
  {54U, 2U}, 
  /* FlexCAN_7_RX input func */
  {195U, 2U}, 
  /* LIN_7_LIN7RX input func */
  {207U, 1U}, 
  /* DSPI_2_dSCLK_IN input func */
  {295U, 3U}, 
  /* EMIOS0_E0UC_0_X_IN input func */
  {0U, 5U}, 
  /* INMUX settings for pad PORT106:    {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_24_X_IN input func */
  {24U, 4U}, 
  /* EMIOS1_E1UC_31_Y_IN input func */
  {67U, 3U}, 
  /* SPI_0_SIN_0 input func */
  {300U, 1U}, 
  /* GLITCH_FILTER3_INP input func */
  {509U, 6U}, 
  /* INMUX settings for pad PORT107:    {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_25_Y_IN input func */
  {25U, 3U}, 
  /* SPI_0_SS_0 input func */
  {302U, 1U}, 
  /* SPI_2_SS_2 input func */
  {308U, 1U}, 
  /* INMUX settings for pad PORT108:    {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_26_Y_IN input func */
  {26U, 3U}, 
  /* INMUX settings for pad PORT109:    {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_27_Y_IN input func */
  {27U, 3U}, 
  /* SPI_0_SCLK_0_IN input func */
  {301U, 2U}, 
  /* INMUX settings for pad PORT110:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_0_X_IN input func */
  {36U, 2U}, 
  /* SPI_2_SIN_2 input func */
  {306U, 1U}, 
  /* INMUX settings for pad PORT111:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_1_H_IN input func */
  {37U, 3U}, 
  /* LIN_8_LIN8RX input func */
  {208U, 1U}, 
  /* INMUX settings for pad PORT112:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_2_H_IN input func */
  {38U, 3U}, 
  /* DSPI_1_dSIN input func */
  {291U, 4U}, 
  /* INMUX settings for pad PORT113:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_3_H_IN input func */
  {39U, 3U}, 
  /* INMUX settings for pad PORT114:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_4_H_IN input func */
  {40U, 3U}, 
  /* DSPI_1_dSCLK_IN input func */
  {292U, 3U}, 
  /* INMUX settings for pad PORT115:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_5_H_IN input func */
  {41U, 2U}, 
  /* DSPI_1_dSS input func */
  {293U, 5U}, 
  /* INMUX settings for pad PORT116:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_6_H_IN input func */
  {42U, 2U}, 
  /* IIC_3_SCL3_IN input func */
  {271U, 2U}, 
  /* INMUX settings for pad PORT117:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_7_H_IN input func */
  {43U, 2U}, 
  /* IIC_3_SDA3_IN input func */
  {272U, 2U}, 
  /* SPI_3_SIN_3 input func */
  {309U, 1U}, 
  /* INMUX settings for pad PORT118:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_8_X_IN input func */
  {44U, 2U}, 
  /* SPI_3_SCLK_3_IN input func */
  {310U, 1U}, 
  /* INMUX settings for pad PORT119:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_9_H_IN input func */
  {45U, 2U}, 
  /* SPI_3_SS_3 input func */
  {311U, 1U}, 
  /* INMUX settings for pad PORT120:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_10_H_IN input func */
  {46U, 2U}, 
  /* INMUX settings for pad PORT123:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_5_H_IN input func */
  {41U, 3U}, 
  /* SPI_0_SS_0 input func */
  {302U, 2U}, 
  /* INMUX settings for pad PORT124:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_25_Y_IN input func */
  {61U, 3U}, 
  /* DSPI_3_dSCLK_IN input func */
  {298U, 2U}, 
  /* INMUX settings for pad PORT125:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_26_Y_IN input func */
  {62U, 3U}, 
  /* DSPI_3_dSS input func */
  {299U, 2U}, 
  /* INMUX settings for pad PORT126:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_27_Y_IN input func */
  {63U, 3U}, 
  /* SPI_0_SCLK_0_IN input func */
  {301U, 3U}, 
  /* FCCU_EIN_ERR input func */
  {501U, 1U}, 
  /* INMUX settings for pad PORT127:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_17_Y_IN input func */
  {53U, 3U}, 
  /* INMUX settings for pad PORT128:    {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_28_Y_IN input func */
  {28U, 3U}, 
  /* IIC_1_SDA1_IN input func */
  {268U, 2U}, 
  /* GLITCH_FILTER0_INP input func */
  {506U, 2U}, 
  /* INMUX settings for pad PORT129:    {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_29_Y_IN input func */
  {29U, 3U}, 
  /* LIN_8_LIN8RX input func */
  {208U, 2U}, 
  /* IIC_1_SCL1_IN input func */
  {267U, 2U}, 
  /* GLITCH_FILTER0_INP input func */
  {506U, 4U}, 
  /* INMUX settings for pad PORT130:    {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_30_Y_IN input func */
  {30U, 4U}, 
  /* IIC_2_SDA2_IN input func */
  {270U, 2U}, 
  /* GLITCH_FILTER1_INP input func */
  {507U, 3U}, 
  /* INMUX settings for pad PORT131:    {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_31_Y_IN input func */
  {31U, 4U}, 
  /* LIN_9_LIN9RX input func */
  {209U, 1U}, 
  /* IIC_2_SCL2_IN input func */
  {269U, 2U}, 
  /* GLITCH_FILTER1_INP input func */
  {507U, 6U}, 
  /* INMUX settings for pad PORT132:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_28_Y_IN input func */
  {64U, 3U}, 
  /* GLITCH_FILTER2_INP input func */
  {508U, 2U}, 
  /* INMUX settings for pad PORT133:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_29_Y_IN input func */
  {65U, 3U}, 
  /* SPI_0_SCLK_0_IN input func */
  {301U, 4U}, 
  /* GLITCH_FILTER2_INP input func */
  {508U, 5U}, 
  /* INMUX settings for pad PORT134:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_30_Y_IN input func */
  {66U, 4U}, 
  /* SPI_0_SS_0 input func */
  {302U, 3U}, 
  /* SPI_1_SS_1 input func */
  {305U, 1U}, 
  /* SPI_2_SS_2 input func */
  {308U, 2U}, 
  /* GLITCH_FILTER3_INP input func */
  {509U, 3U}, 
  /* INMUX settings for pad PORT135:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_31_Y_IN input func */
  {67U, 4U}, 
  /* GLITCH_FILTER3_INP input func */
  {509U, 7U}, 
  /* INMUX settings for pad PORT139:    {INMUX reg, PADSEL val} */
  /* DSPI_3_dSIN input func */
  {297U, 2U}, 
  /* ENET0_ENET0_TMR1_IN input func */
  {330U, 1U}, 
  /* INMUX settings for pad PORT140:    {INMUX reg, PADSEL val} */
  /* DSPI_2_dSS input func */
  {296U, 5U}, 
  /* DSPI_3_dSS input func */
  {299U, 3U}, 
  /* INMUX settings for pad PORT142:    {INMUX reg, PADSEL val} */
  /* SPI_0_SIN_0 input func */
  {300U, 2U}, 
  /* SAI2_SAI2_D0_IN input func */
  {505U, 2U}, 
  /* INMUX settings for pad PORT143:    {INMUX reg, PADSEL val} */
  /* SPI_0_SS_0 input func */
  {302U, 4U}, 
  /* SAI2_SAI2_MCLK_IN input func */
  {503U, 2U}, 
  /* INMUX settings for pad PORT144:    {INMUX reg, PADSEL val} */
  /* SAI2_SAI2_SYNC_IN input func */
  {504U, 2U}, 
  /* INMUX settings for pad PORT145:    {INMUX reg, PADSEL val} */
  /* SPI_1_SIN_1 input func */
  {303U, 1U}, 
  /* SAI2_SAI2_BCLK_IN input func */
  {502U, 1U}, 
  /* INMUX settings for pad PORT146:    {INMUX reg, PADSEL val} */
  /* SPI_1_SS_1 input func */
  {305U, 2U}, 
  /* SPI_2_SS_2 input func */
  {308U, 3U}, 
  /* SPI_3_SS_3 input func */
  {311U, 2U}, 
  /* SAI1_SAI1_D0_IN input func */
  {498U, 1U}, 
  /* INMUX settings for pad PORT147:    {INMUX reg, PADSEL val} */
  /* SAI1_SAI1_BCLK_IN input func */
  {495U, 1U}, 
  /* INMUX settings for pad PORT148:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_18_Y_IN input func */
  {54U, 3U}, 
  /* SPI_1_SCLK_1_IN input func */
  {304U, 1U}, 
  /* FCCU_EIN_ERR input func */
  {501U, 2U}, 
  /* INMUX settings for pad PORT149:    {INMUX reg, PADSEL val} */
  /* SAI2_SAI2_D0_IN input func */
  {505U, 1U}, 
  /* INMUX settings for pad PORT150:    {INMUX reg, PADSEL val} */
  /* SAI2_SAI2_BCLK_IN input func */
  {502U, 2U}, 
  /* INMUX settings for pad PORT151:    {INMUX reg, PADSEL val} */
  /* SAI2_SAI2_MCLK_IN input func */
  {503U, 1U}, 
  /* INMUX settings for pad PORT152:    {INMUX reg, PADSEL val} */
  /* SAI2_SAI2_SYNC_IN input func */
  {504U, 1U}, 
  /* INMUX settings for pad PORT153:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_17_Y_IN input func */
  {53U, 4U}, 
  /* INMUX settings for pad PORT154:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_16_X_IN input func */
  {52U, 3U}, 
  /* FlexCAN_4_RX input func */
  {192U, 4U}, 
  /* INMUX settings for pad PORT155:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_11_H_IN input func */
  {47U, 3U}, 
  /* INMUX settings for pad PORT156:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_10_H_IN input func */
  {46U, 3U}, 
  /* FlexCAN_2_RX input func */
  {190U, 3U}, 
  /* INMUX settings for pad PORT157:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_15_H_IN input func */
  {51U, 3U}, 
  /* FlexCAN_1_RX input func */
  {189U, 5U}, 
  /* FlexCAN_4_RX input func */
  {192U, 5U}, 
  /* FlexCAN_6_RX input func */
  {194U, 2U}, 
  /* INMUX settings for pad PORT158:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_14_H_IN input func */
  {50U, 3U}, 
  /* INMUX settings for pad PORT159:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_13_H_IN input func */
  {49U, 3U}, 
  /* FlexCAN_1_RX input func */
  {189U, 6U}, 
  /* FlexCAN_3_RX input func */
  {191U, 5U}, 
  /* INMUX settings for pad PORT160:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_12_H_IN input func */
  {48U, 3U}, 
  /* INMUX settings for pad PORT161:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_1_H_IN input func */
  {37U, 4U}, 
  /* FlexCAN_4_RX input func */
  {192U, 6U}, 
  /* EMIOS0_E0UC_6_G_IN input func */
  {6U, 4U}, 
  /* INMUX settings for pad PORT162:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_2_H_IN input func */
  {38U, 4U}, 
  /* INMUX settings for pad PORT163:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_0_X_IN input func */
  {36U, 3U}, 
  /* EMIOS1_E1UC_3_H_IN input func */
  {39U, 4U}, 
  /* SIUL2_EIRQ31 input func */
  {175U, 1U}, 
  /* FlexCAN_5_RX input func */
  {193U, 3U}, 
  /* LIN_8_LIN8RX input func */
  {208U, 3U}, 
  /* INMUX settings for pad PORT164:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_1_H_IN input func */
  {37U, 5U}, 
  /* EMIOS0_E0UC_9_H_IN input func */
  {9U, 3U}, 
  /* INMUX settings for pad PORT165:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_4_H_IN input func */
  {40U, 4U}, 
  /* FlexCAN_2_RX input func */
  {190U, 4U}, 
  /* LIN_2_LIN2RX input func */
  {202U, 3U}, 
  /* EMIOS0_E0UC_10_H_IN input func */
  {10U, 4U}, 
  /* INMUX settings for pad PORT166:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_5_H_IN input func */
  {41U, 4U}, 
  /* EMIOS0_E0UC_11_H_IN input func */
  {11U, 4U}, 
  /* INMUX settings for pad PORT167:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_6_H_IN input func */
  {42U, 3U}, 
  /* FlexCAN_3_RX input func */
  {191U, 6U}, 
  /* LIN_3_LIN3RX input func */
  {203U, 3U}, 
  /* EMIOS0_E0UC_12_H_IN input func */
  {12U, 4U}, 
  /* INMUX settings for pad PORT168:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_7_H_IN input func */
  {43U, 3U}, 
  /* EMIOS0_E0UC_13_H_IN input func */
  {13U, 5U}, 
  /* INMUX settings for pad PORT169:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_29_Y_IN input func */
  {65U, 4U}, 
  /* LIN_15_LIN15RX input func */
  {215U, 2U}, 
  /* SPI_0_SIN_0 input func */
  {300U, 3U}, 
  /* GLITCH_FILTER2_INP input func */
  {508U, 6U}, 
  /* INMUX settings for pad PORT170:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_30_Y_IN input func */
  {66U, 5U}, 
  /* GLITCH_FILTER3_INP input func */
  {509U, 4U}, 
  /* INMUX settings for pad PORT171:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_31_Y_IN input func */
  {67U, 5U}, 
  /* SPI_0_SCLK_0_IN input func */
  {301U, 5U}, 
  /* GLITCH_FILTER3_INP input func */
  {509U, 8U}, 
  /* INMUX settings for pad PORT172:    {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_0_X_IN input func */
  {0U, 4U}, 
  /* LIN_14_LIN14RX input func */
  {214U, 2U}, 
  /* SPI_0_SS_0 input func */
  {302U, 5U}, 
  /* INMUX settings for pad PORT173:    {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_1_G_IN input func */
  {1U, 4U}, 
  /* FlexCAN_3_RX input func */
  {191U, 7U}, 
  /* SPI_1_SCLK_1_IN input func */
  {304U, 2U}, 
  /* INMUX settings for pad PORT174:    {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_2_G_IN input func */
  {2U, 3U}, 
  /* SPI_1_SS_1 input func */
  {305U, 3U}, 
  /* INMUX settings for pad PORT175:    {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_3_G_IN input func */
  {3U, 5U}, 
  /* SPI_1_SIN_1 input func */
  {303U, 2U}, 
  /* SPI_3_SIN_3 input func */
  {309U, 2U}, 
  /* INMUX settings for pad PORT176:    {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_4_G_IN input func */
  {4U, 4U}, 
  /* LIN_13_LIN13RX input func */
  {213U, 2U}, 
  /* INMUX settings for pad PORT177:    {INMUX reg, PADSEL val} */
  /* SAI0_SAI0_D0_IN input func */
  {491U, 2U}, 
  /* INMUX settings for pad PORT195:    {INMUX reg, PADSEL val} */
  /* SAI0_SAI0_D1_IN input func */
  {492U, 3U}, 
  /* ENET0_ENET0_TMR2_IN input func */
  {331U, 1U}, 
  /* INMUX settings for pad PORT196:    {INMUX reg, PADSEL val} */
  /* SAI0_SAI0_D2_IN input func */
  {493U, 3U}, 
  /* INMUX settings for pad PORT197:    {INMUX reg, PADSEL val} */
  /* SAI0_SAI0_D3_IN input func */
  {494U, 3U}, 
  /* INMUX settings for pad PORT206:    {INMUX reg, PADSEL val} */
  /* SAI0_SAI0_MCLK_IN input func */
  {489U, 3U}, 
  /* INMUX settings for pad PORT224:    {INMUX reg, PADSEL val} */
  /* IIC_0_SDA0_IN input func */
  {266U, 3U}, 
  /* INMUX settings for pad PORT225:    {INMUX reg, PADSEL val} */
  /* LIN_12_LIN12RX input func */
  {212U, 2U}, 
  /* IIC_0_SCL0_IN input func */
  {265U, 3U}, 
  /* INMUX settings for pad PORT252:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_24_X_IN input func */
  {60U, 3U}, 
  /* SPI_2_SS_2 input func */
  {308U, 4U}, 
  /* INMUX settings for pad PORT253:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_23_X_IN input func */
  {59U, 3U}, 
  /* INMUX settings for pad PORT254:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_22_X_IN input func */
  {58U, 3U}, 
  /* SPI_2_SCLK_2_IN input func */
  {307U, 2U}, 
  /* INMUX settings for pad PORT255:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_21_Y_IN input func */
  {57U, 3U}, 
  /* SPI_2_SIN_2 input func */
  {306U, 2U}, 
  /* INMUX settings for pad PORT257:    {INMUX reg, PADSEL val} */
  /* DSPI_0_dSS input func */
  {290U, 4U}, 
  /* INMUX settings for pad PORT258:    {INMUX reg, PADSEL val} */
  /* DSPI_0_dSCLK_IN input func */
  {289U, 3U}, 
  /* INMUX settings for pad PORT259:    {INMUX reg, PADSEL val} */
  /* DSPI_0_dSIN input func */
  {288U, 2U}, 
  /* INMUX settings for pad PORT260:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_28_Y_IN input func */
  {64U, 4U}, 
  /* GLITCH_FILTER2_INP input func */
  {508U, 3U}, 
  /* INMUX settings for pad PORT261:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_27_Y_IN input func */
  {63U, 4U}, 
  /* INMUX settings for pad PORT262:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_26_Y_IN input func */
  {62U, 4U}, 
  /* INMUX settings for pad PORT263:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_25_Y_IN input func */
  {61U, 4U}
[!ENDVAR!]


[!VAR "INPUT_INMUX_4"!]
  /* INMUX settings for pad not available:  */
  { NO_INPUTMUX_U16, 0U},
  /* INMUX settings for pad PORT0:      {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_0_X_IN input func */
  {0U, 2U}, 
  /* EMIOS0_E0UC_13_H_IN input func */
  {13U, 2U}, 
  /* FlexCAN_1_RX input func */
  {189U, 1U}, 
  /* INMUX settings for pad PORT1:      {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_1_G_IN input func */
  {1U, 2U}, 
  /* FlexCAN_3_RX input func */
  {191U, 1U}, 
  /* INMUX settings for pad PORT2:      {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_2_G_IN input func */
  {2U, 2U}, 
  /* INMUX settings for pad PORT3:      {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_3_G_IN input func */
  {3U, 2U}, 
  /* SIUL2_EIRQ0 input func */
  {144U, 1U}, 
  /* ENET0_MII_0_RX_CLK input func */
  {448U, 1U}, 
  /* INMUX settings for pad PORT4:      {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_4_G_IN input func */
  {4U, 2U}, 
  /* LIN_5_LIN5RX input func */
  {205U, 1U}, 
  /* DSPI_1_dSS input func */
  {293U, 1U}, 
  /* EMIOS0_E0UC_24_X_IN input func */
  {24U, 5U}, 
  /* INMUX settings for pad PORT5:      {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_5_G_IN input func */
  {5U, 2U}, 
  /* INMUX settings for pad PORT6:      {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_6_G_IN input func */
  {6U, 2U}, 
  /* SIUL2_EIRQ1 input func */
  {145U, 1U}, 
  /* LIN_4_LIN4RX input func */
  {204U, 1U}, 
  /* INMUX settings for pad PORT7:      {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_7_G_IN input func */
  {7U, 2U}, 
  /* SIUL2_EIRQ2 input func */
  {146U, 1U}, 
  /* ENET0_MII_0_RXD_2 input func */
  {453U, 1U}, 
  /* INMUX settings for pad PORT8:      {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_8_X_IN input func */
  {8U, 2U}, 
  /* EMIOS0_E0UC_14_H_IN input func */
  {14U, 2U}, 
  /* SIUL2_EIRQ3 input func */
  {147U, 1U}, 
  /* LIN_3_LIN3RX input func */
  {203U, 1U}, 
  /* ENET0_MII_RMII_0_RXD_1 input func */
  {452U, 1U}, 
  /* INMUX settings for pad PORT9:      {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_9_H_IN input func */
  {9U, 2U}, 
  /* ENET0_MII_RMII_0_RXD_0 input func */
  {451U, 1U}, 
  /* INMUX settings for pad PORT10:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_10_H_IN input func */
  {10U, 2U}, 
  /* IIC_0_SDA0_IN input func */
  {266U, 1U}, 
  /* DSPI_1_dSIN input func */
  {291U, 1U}, 
  /* ENET0_MII_0_COL input func */
  {456U, 1U}, 
  /* INMUX settings for pad PORT11:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_11_H_IN input func */
  {11U, 2U}, 
  /* SIUL2_EIRQ16 input func */
  {160U, 1U}, 
  /* LIN_2_LIN2RX input func */
  {202U, 1U}, 
  /* IIC_0_SCL0_IN input func */
  {265U, 1U}, 
  /* ENET0_MII_RMII_0_RX_ER input func */
  {455U, 1U}, 
  /* INMUX settings for pad PORT12:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_28_Y_IN input func */
  {28U, 2U}, 
  /* SIUL2_EIRQ17 input func */
  {161U, 1U}, 
  /* DSPI_0_dSIN input func */
  {288U, 1U}, 
  /* EMIOS0_E0UC_26_Y_IN input func */
  {26U, 4U}, 
  /* GLITCH_FILTER0_INP input func */
  {506U, 1U}, 
  /* INMUX settings for pad PORT13:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_29_Y_IN input func */
  {29U, 2U}, 
  /* EMIOS0_E0UC_25_Y_IN input func */
  {25U, 4U}, 
  /* GLITCH_FILTER0_INP input func */
  {506U, 3U}, 
  /* INMUX settings for pad PORT14:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_0_X_IN input func */
  {0U, 3U}, 
  /* SIUL2_EIRQ4 input func */
  {148U, 1U}, 
  /* DSPI_0_dSCLK_IN input func */
  {289U, 1U}, 
  /* DSPI_0_dSS input func */
  {290U, 1U}, 
  /* EMIOS0_E0UC_23_X_IN input func */
  {23U, 5U}, 
  /* INMUX settings for pad PORT15:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_1_G_IN input func */
  {1U, 3U}, 
  /* FlexCAN_0_RX input func */
  {188U, 1U}, 
  /* DSPI_0_dSCLK_IN input func */
  {289U, 2U}, 
  /* DSPI_0_dSS input func */
  {290U, 2U}, 
  /* EMIOS0_E0UC_21_Y_IN input func */
  {21U, 3U}, 
  /* INMUX settings for pad PORT16:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_30_Y_IN input func */
  {30U, 2U}, 
  /* EMIOS0_E0UC_4_G_IN input func */
  {4U, 5U}, 
  /* GLITCH_FILTER1_INP input func */
  {507U, 1U}, 
  /* INMUX settings for pad PORT17:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_31_Y_IN input func */
  {31U, 2U}, 
  /* FlexCAN_0_RX input func */
  {188U, 2U}, 
  /* LIN_0_LIN0RX input func */
  {200U, 1U}, 
  /* EMIOS0_E0UC_5_G_IN input func */
  {5U, 4U}, 
  /* GLITCH_FILTER1_INP input func */
  {507U, 4U}, 
  /* INMUX settings for pad PORT18:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_30_Y_IN input func */
  {30U, 3U}, 
  /* IIC_0_SDA0_IN input func */
  {266U, 2U}, 
  /* GLITCH_FILTER1_INP input func */
  {507U, 2U}, 
  /* INMUX settings for pad PORT19:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_31_Y_IN input func */
  {31U, 3U}, 
  /* LIN_0_LIN0RX input func */
  {200U, 2U}, 
  /* IIC_0_SCL0_IN input func */
  {265U, 2U}, 
  /* EMIOS0_E0UC_8_X_IN input func */
  {8U, 3U}, 
  /* GLITCH_FILTER1_INP input func */
  {507U, 5U}, 
  /* INMUX settings for pad PORT26:     {INMUX reg, PADSEL val} */
  /* FlexCAN_6_RX input func */
  {194U, 1U}, 
  /* SAI0_SAI0_SYNC_IN input func */
  {490U, 1U}, 
  /* EMIOS0_E0UC_29_Y_IN input func */
  {29U, 4U}, 
  /* INMUX settings for pad PORT27:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_3_G_IN input func */
  {3U, 3U}, 
  /* DSPI_0_dSS input func */
  {290U, 3U}, 
  /* INMUX settings for pad PORT28:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_4_G_IN input func */
  {4U, 3U}, 
  /* INMUX settings for pad PORT29:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_5_G_IN input func */
  {5U, 3U}, 
  /* INMUX settings for pad PORT30:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_6_G_IN input func */
  {6U, 3U}, 
  /* INMUX settings for pad PORT31:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_7_G_IN input func */
  {7U, 3U}, 
  /* INMUX settings for pad PORT34:     {INMUX reg, PADSEL val} */
  /* SIUL2_EIRQ5 input func */
  {149U, 1U}, 
  /* DSPI_1_dSCLK_IN input func */
  {292U, 1U}, 
  /* INMUX settings for pad PORT35:     {INMUX reg, PADSEL val} */
  /* SIUL2_EIRQ6 input func */
  {150U, 1U}, 
  /* FlexCAN_1_RX input func */
  {189U, 2U}, 
  /* FlexCAN_4_RX input func */
  {192U, 1U}, 
  /* DSPI_1_dSS input func */
  {293U, 2U}, 
  /* INMUX settings for pad PORT36:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_31_Y_IN input func */
  {67U, 2U}, 
  /* SIUL2_EIRQ18 input func */
  {162U, 1U}, 
  /* FlexCAN_3_RX input func */
  {191U, 2U}, 
  /* DSPI_1_dSIN input func */
  {291U, 2U}, 
  /* GLITCH_FILTER3_INP input func */
  {509U, 5U}, 
  /* INMUX settings for pad PORT37:     {INMUX reg, PADSEL val} */
  /* SIUL2_EIRQ7 input func */
  {151U, 1U}, 
  /* INMUX settings for pad PORT38:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_28_Y_IN input func */
  {64U, 2U}, 
  /* EMIOS0_E0UC_17_Y_IN input func */
  {17U, 3U}, 
  /* GLITCH_FILTER2_INP input func */
  {508U, 1U}, 
  /* INMUX settings for pad PORT39:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_29_Y_IN input func */
  {65U, 2U}, 
  /* LIN_1_LIN1RX input func */
  {201U, 1U}, 
  /* EMIOS0_E0UC_18_Y_IN input func */
  {18U, 3U}, 
  /* GLITCH_FILTER2_INP input func */
  {508U, 4U}, 
  /* INMUX settings for pad PORT40:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_3_G_IN input func */
  {3U, 4U}, 
  /* INMUX settings for pad PORT41:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_7_G_IN input func */
  {7U, 4U}, 
  /* LIN_2_LIN2RX input func */
  {202U, 2U}, 
  /* INMUX settings for pad PORT43:     {INMUX reg, PADSEL val} */
  /* FlexCAN_1_RX input func */
  {189U, 3U}, 
  /* FlexCAN_4_RX input func */
  {192U, 2U}, 
  /* EMIOS0_E0UC_1_G_IN input func */
  {1U, 5U}, 
  /* INMUX settings for pad PORT44:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_12_H_IN input func */
  {12U, 2U}, 
  /* SIUL2_EIRQ19 input func */
  {163U, 1U}, 
  /* DSPI_2_dSIN input func */
  {294U, 1U}, 
  /* INMUX settings for pad PORT45:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_13_H_IN input func */
  {13U, 3U}, 
  /* INMUX settings for pad PORT46:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_14_H_IN input func */
  {14U, 3U}, 
  /* SIUL2_EIRQ8 input func */
  {152U, 1U}, 
  /* DSPI_2_dSCLK_IN input func */
  {295U, 1U}, 
  /* INMUX settings for pad PORT47:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_15_H_IN input func */
  {15U, 2U}, 
  /* SIUL2_EIRQ20 input func */
  {164U, 1U}, 
  /* DSPI_2_dSS input func */
  {296U, 1U}, 
  /* FlexCAN_4_RX input func */
  {192U, 7U}, 
  /* INMUX settings for pad PORT60:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_24_X_IN input func */
  {24U, 2U}, 
  /* INMUX settings for pad PORT61:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_25_Y_IN input func */
  {25U, 2U}, 
  /* DSPI_1_dSS input func */
  {293U, 3U}, 
  /* ENET0_ENET0_TMR0_IN input func */
  {329U, 1U}, 
  /* INMUX settings for pad PORT62:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_26_Y_IN input func */
  {26U, 2U}, 
  /* INMUX settings for pad PORT63:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_27_Y_IN input func */
  {27U, 2U}, 
  /* INMUX settings for pad PORT64:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_16_X_IN input func */
  {16U, 2U}, 
  /* FlexCAN_5_RX input func */
  {193U, 1U}, 
  /* LIN_11_LIN11RX input func */
  {211U, 1U}, 
  /* IIC_1_SCL1_IN input func */
  {267U, 1U}, 
  /* INMUX settings for pad PORT65:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_17_Y_IN input func */
  {17U, 2U}, 
  /* IIC_1_SDA1_IN input func */
  {268U, 1U}, 
  /* INMUX settings for pad PORT66:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_18_Y_IN input func */
  {18U, 2U}, 
  /* SIUL2_EIRQ21 input func */
  {165U, 1U}, 
  /* DSPI_1_dSIN input func */
  {291U, 3U}, 
  /* INMUX settings for pad PORT67:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_19_Y_IN input func */
  {19U, 2U}, 
  /* FlexRay_FR_A_RX input func */
  {224U, 1U}, 
  /* INMUX settings for pad PORT68:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_20_Y_IN input func */
  {20U, 2U}, 
  /* SIUL2_EIRQ9 input func */
  {153U, 1U}, 
  /* DSPI_1_dSCLK_IN input func */
  {292U, 2U}, 
  /* INMUX settings for pad PORT69:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_21_Y_IN input func */
  {21U, 2U}, 
  /* FlexRay_FR_B_RX input func */
  {225U, 1U}, 
  /* DSPI_1_dSS input func */
  {293U, 4U}, 
  /* INMUX settings for pad PORT70:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_22_X_IN input func */
  {22U, 2U}, 
  /* SIUL2_EIRQ22 input func */
  {166U, 1U}, 
  /* INMUX settings for pad PORT71:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_23_X_IN input func */
  {23U, 2U}, 
  /* SIUL2_EIRQ23 input func */
  {167U, 1U}, 
  /* INMUX settings for pad PORT72:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_22_X_IN input func */
  {22U, 3U}, 
  /* IIC_2_SDA2_IN input func */
  {270U, 1U}, 
  /* INMUX settings for pad PORT73:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_23_X_IN input func */
  {23U, 3U}, 
  /* FlexCAN_2_RX input func */
  {190U, 1U}, 
  /* FlexCAN_3_RX input func */
  {191U, 3U}, 
  /* IIC_2_SCL2_IN input func */
  {269U, 1U}, 
  /* INMUX settings for pad PORT74:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_30_Y_IN input func */
  {66U, 2U}, 
  /* SIUL2_EIRQ10 input func */
  {154U, 1U}, 
  /* IIC_3_SDA3_IN input func */
  {272U, 1U}, 
  /* GLITCH_FILTER3_INP input func */
  {509U, 1U}, 
  /* INMUX settings for pad PORT75:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_24_X_IN input func */
  {24U, 3U}, 
  /* LIN_3_LIN3RX input func */
  {203U, 2U}, 
  /* IIC_3_SCL3_IN input func */
  {271U, 1U}, 
  /* INMUX settings for pad PORT76:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_19_Y_IN input func */
  {55U, 2U}, 
  /* SIUL2_EIRQ11 input func */
  {155U, 1U}, 
  /* DSPI_2_dSIN input func */
  {294U, 2U}, 
  /* ENET0_MII_0_CRS input func */
  {458U, 1U}, 
  /* INMUX settings for pad PORT77:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_20_Y_IN input func */
  {56U, 2U}, 
  /* ENET0_MII_0_RXD_3 input func */
  {454U, 1U}, 
  /* INMUX settings for pad PORT78:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_21_Y_IN input func */
  {57U, 2U}, 
  /* SIUL2_EIRQ12 input func */
  {156U, 1U}, 
  /* DSPI_2_dSCLK_IN input func */
  {295U, 2U}, 
  /* INMUX settings for pad PORT79:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_22_X_IN input func */
  {58U, 2U}, 
  /* DSPI_2_dSS input func */
  {296U, 2U}, 
  /* SPI_2_SCLK_2_IN input func */
  {307U, 1U}, 
  /* INMUX settings for pad PORT80:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_10_H_IN input func */
  {10U, 3U}, 
  /* SAI0_SAI0_MCLK_IN input func */
  {489U, 1U}, 
  /* INMUX settings for pad PORT81:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_11_H_IN input func */
  {11U, 3U}, 
  /* SAI0_SAI0_BCLK_IN input func */
  {488U, 1U}, 
  /* INMUX settings for pad PORT82:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_12_H_IN input func */
  {12U, 3U}, 
  /* DSPI_2_dSS input func */
  {296U, 3U}, 
  /* SAI0_SAI0_D3_IN input func */
  {494U, 1U}, 
  /* GLITCH_FILTER0_INP input func */
  {506U, 5U}, 
  /* INMUX settings for pad PORT83:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_13_H_IN input func */
  {13U, 4U}, 
  /* SAI0_SAI0_D2_IN input func */
  {493U, 1U}, 
  /* GLITCH_FILTER1_INP input func */
  {507U, 7U}, 
  /* INMUX settings for pad PORT84:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_14_H_IN input func */
  {14U, 4U}, 
  /* SAI0_SAI0_D1_IN input func */
  {492U, 1U}, 
  /* GLITCH_FILTER2_INP input func */
  {508U, 7U}, 
  /* INMUX settings for pad PORT85:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_22_X_IN input func */
  {22U, 4U}, 
  /* SAI0_SAI0_D0_IN input func */
  {491U, 1U}, 
  /* GLITCH_FILTER3_INP input func */
  {509U, 9U}, 
  /* INMUX settings for pad PORT86:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_23_X_IN input func */
  {23U, 4U}, 
  /* SAI1_SAI1_SYNC_IN input func */
  {497U, 1U}, 
  /* EMIOS0_E0UC_30_Y_IN input func */
  {30U, 5U}, 
  /* INMUX settings for pad PORT87:     {INMUX reg, PADSEL val} */
  /* SPI_0_SCLK_0_IN input func */
  {301U, 1U}, 
  /* SAI1_SAI1_MCLK_IN input func */
  {496U, 1U}, 
  /* INMUX settings for pad PORT88:     {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_15_H_IN input func */
  {15U, 3U}, 
  /* INMUX settings for pad PORT89:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_1_H_IN input func */
  {37U, 2U}, 
  /* FlexCAN_2_RX input func */
  {190U, 2U}, 
  /* FlexCAN_3_RX input func */
  {191U, 4U}, 
  /* EMIOS0_E0UC_14_H_IN input func */
  {14U, 5U}, 
  /* INMUX settings for pad PORT90:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_2_H_IN input func */
  {38U, 2U}, 
  /* EMIOS0_E0UC_19_Y_IN input func */
  {19U, 3U}, 
  /* INMUX settings for pad PORT91:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_3_H_IN input func */
  {39U, 2U}, 
  /* LIN_4_LIN4RX input func */
  {204U, 2U}, 
  /* EMIOS0_E0UC_20_Y_IN input func */
  {20U, 3U}, 
  /* INMUX settings for pad PORT92:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_25_Y_IN input func */
  {61U, 2U}, 
  /* EMIOS0_E0UC_16_X_IN input func */
  {16U, 3U}, 
  /* INMUX settings for pad PORT93:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_26_Y_IN input func */
  {62U, 2U}, 
  /* LIN_5_LIN5RX input func */
  {205U, 2U}, 
  /* EMIOS0_E0UC_22_X_IN input func */
  {22U, 5U}, 
  /* INMUX settings for pad PORT94:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_27_Y_IN input func */
  {63U, 2U}, 
  /* ENET0_MII_RMII_0_MDIO_IN input func */
  {450U, 1U}, 
  /* INMUX settings for pad PORT95:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_4_H_IN input func */
  {40U, 2U}, 
  /* SIUL2_EIRQ13 input func */
  {157U, 1U}, 
  /* FlexCAN_1_RX input func */
  {189U, 4U}, 
  /* FlexCAN_4_RX input func */
  {192U, 3U}, 
  /* ENET0_MII_RMII_0_RX_DV input func */
  {457U, 1U}, 
  /* INMUX settings for pad PORT96:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_23_X_IN input func */
  {59U, 2U}, 
  /* INMUX settings for pad PORT97:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_24_X_IN input func */
  {60U, 2U}, 
  /* SIUL2_EIRQ14 input func */
  {158U, 1U}, 
  /* FlexCAN_5_RX input func */
  {193U, 2U}, 
  /* ENET0_MII_RMII_0_TX_CLK_IN input func */
  {449U, 1U}, 
  /* INMUX settings for pad PORT98:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_11_H_IN input func */
  {47U, 2U}, 
  /* INMUX settings for pad PORT99:     {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_12_H_IN input func */
  {48U, 2U}, 
  /* FlexCAN_7_RX input func */
  {195U, 1U}, 
  /* DSPI_3_dSS input func */
  {299U, 1U}, 
  /* INMUX settings for pad PORT100:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_13_H_IN input func */
  {49U, 2U}, 
  /* DSPI_3_dSCLK_IN input func */
  {298U, 1U}, 
  /* INMUX settings for pad PORT101:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_14_H_IN input func */
  {50U, 2U}, 
  /* LIN_10_LIN10RX input func */
  {210U, 1U}, 
  /* DSPI_3_dSIN input func */
  {297U, 1U}, 
  /* EMIOS0_E0UC_2_G_IN input func */
  {2U, 4U}, 
  /* INMUX settings for pad PORT102:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_15_H_IN input func */
  {51U, 2U}, 
  /* EMIOS0_E0UC_3_G_IN input func */
  {3U, 6U}, 
  /* INMUX settings for pad PORT103:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_16_X_IN input func */
  {52U, 2U}, 
  /* EMIOS1_E1UC_30_Y_IN input func */
  {66U, 3U}, 
  /* LIN_6_LIN6RX input func */
  {206U, 1U}, 
  /* GLITCH_FILTER3_INP input func */
  {509U, 2U}, 
  /* INMUX settings for pad PORT104:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_17_Y_IN input func */
  {53U, 2U}, 
  /* SIUL2_EIRQ15 input func */
  {159U, 1U}, 
  /* DSPI_2_dSS input func */
  {296U, 4U}, 
  /* INMUX settings for pad PORT105:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_18_Y_IN input func */
  {54U, 2U}, 
  /* FlexCAN_7_RX input func */
  {195U, 2U}, 
  /* LIN_7_LIN7RX input func */
  {207U, 1U}, 
  /* DSPI_2_dSCLK_IN input func */
  {295U, 3U}, 
  /* EMIOS0_E0UC_0_X_IN input func */
  {0U, 5U}, 
  /* INMUX settings for pad PORT106:    {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_24_X_IN input func */
  {24U, 4U}, 
  /* EMIOS1_E1UC_31_Y_IN input func */
  {67U, 3U}, 
  /* SPI_0_SIN_0 input func */
  {300U, 1U}, 
  /* GLITCH_FILTER3_INP input func */
  {509U, 6U}, 
  /* INMUX settings for pad PORT107:    {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_25_Y_IN input func */
  {25U, 3U}, 
  /* SPI_0_SS_0 input func */
  {302U, 1U}, 
  /* SPI_2_SS_2 input func */
  {308U, 1U}, 
  /* INMUX settings for pad PORT108:    {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_26_Y_IN input func */
  {26U, 3U}, 
  /* INMUX settings for pad PORT109:    {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_27_Y_IN input func */
  {27U, 3U}, 
  /* SPI_0_SCLK_0_IN input func */
  {301U, 2U}, 
  /* INMUX settings for pad PORT110:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_0_X_IN input func */
  {36U, 2U}, 
  /* SPI_2_SIN_2 input func */
  {306U, 1U}, 
  /* INMUX settings for pad PORT111:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_1_H_IN input func */
  {37U, 3U}, 
  /* LIN_8_LIN8RX input func */
  {208U, 1U}, 
  /* INMUX settings for pad PORT112:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_2_H_IN input func */
  {38U, 3U}, 
  /* DSPI_1_dSIN input func */
  {291U, 4U}, 
  /* INMUX settings for pad PORT113:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_3_H_IN input func */
  {39U, 3U}, 
  /* INMUX settings for pad PORT114:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_4_H_IN input func */
  {40U, 3U}, 
  /* DSPI_1_dSCLK_IN input func */
  {292U, 3U}, 
  /* INMUX settings for pad PORT115:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_5_H_IN input func */
  {41U, 2U}, 
  /* DSPI_1_dSS input func */
  {293U, 5U}, 
  /* INMUX settings for pad PORT116:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_6_H_IN input func */
  {42U, 2U}, 
  /* IIC_3_SCL3_IN input func */
  {271U, 2U}, 
  /* INMUX settings for pad PORT117:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_7_H_IN input func */
  {43U, 2U}, 
  /* IIC_3_SDA3_IN input func */
  {272U, 2U}, 
  /* SPI_3_SIN_3 input func */
  {309U, 1U}, 
  /* INMUX settings for pad PORT118:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_8_X_IN input func */
  {44U, 2U}, 
  /* SPI_3_SCLK_3_IN input func */
  {310U, 1U}, 
  /* INMUX settings for pad PORT119:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_9_H_IN input func */
  {45U, 2U}, 
  /* SPI_3_SS_3 input func */
  {311U, 1U}, 
  /* INMUX settings for pad PORT120:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_10_H_IN input func */
  {46U, 2U}, 
  /* INMUX settings for pad PORT123:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_5_H_IN input func */
  {41U, 3U}, 
  /* SPI_0_SS_0 input func */
  {302U, 2U}, 
  /* INMUX settings for pad PORT124:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_25_Y_IN input func */
  {61U, 3U}, 
  /* DSPI_3_dSCLK_IN input func */
  {298U, 2U}, 
  /* INMUX settings for pad PORT125:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_26_Y_IN input func */
  {62U, 3U}, 
  /* DSPI_3_dSS input func */
  {299U, 2U}, 
  /* INMUX settings for pad PORT126:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_27_Y_IN input func */
  {63U, 3U}, 
  /* SPI_0_SCLK_0_IN input func */
  {301U, 3U}, 
  /* FCCU_EIN_ERR input func */
  {501U, 1U}, 
  /* INMUX settings for pad PORT127:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_17_Y_IN input func */
  {53U, 3U}, 
  /* INMUX settings for pad PORT128:    {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_28_Y_IN input func */
  {28U, 3U}, 
  /* IIC_1_SDA1_IN input func */
  {268U, 2U}, 
  /* GLITCH_FILTER0_INP input func */
  {506U, 2U}, 
  /* INMUX settings for pad PORT129:    {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_29_Y_IN input func */
  {29U, 3U}, 
  /* LIN_8_LIN8RX input func */
  {208U, 2U}, 
  /* IIC_1_SCL1_IN input func */
  {267U, 2U}, 
  /* GLITCH_FILTER0_INP input func */
  {506U, 4U}, 
  /* INMUX settings for pad PORT130:    {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_30_Y_IN input func */
  {30U, 4U}, 
  /* IIC_2_SDA2_IN input func */
  {270U, 2U}, 
  /* GLITCH_FILTER1_INP input func */
  {507U, 3U}, 
  /* INMUX settings for pad PORT131:    {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_31_Y_IN input func */
  {31U, 4U}, 
  /* LIN_9_LIN9RX input func */
  {209U, 1U}, 
  /* IIC_2_SCL2_IN input func */
  {269U, 2U}, 
  /* GLITCH_FILTER1_INP input func */
  {507U, 6U}, 
  /* INMUX settings for pad PORT132:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_28_Y_IN input func */
  {64U, 3U}, 
  /* GLITCH_FILTER2_INP input func */
  {508U, 2U}, 
  /* INMUX settings for pad PORT133:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_29_Y_IN input func */
  {65U, 3U}, 
  /* SPI_0_SCLK_0_IN input func */
  {301U, 4U}, 
  /* GLITCH_FILTER2_INP input func */
  {508U, 5U}, 
  /* INMUX settings for pad PORT134:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_30_Y_IN input func */
  {66U, 4U}, 
  /* SPI_0_SS_0 input func */
  {302U, 3U}, 
  /* SPI_1_SS_1 input func */
  {305U, 1U}, 
  /* SPI_2_SS_2 input func */
  {308U, 2U}, 
  /* GLITCH_FILTER3_INP input func */
  {509U, 3U}, 
  /* INMUX settings for pad PORT135:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_31_Y_IN input func */
  {67U, 4U}, 
  /* GLITCH_FILTER3_INP input func */
  {509U, 7U}, 
  /* INMUX settings for pad PORT139:    {INMUX reg, PADSEL val} */
  /* DSPI_3_dSIN input func */
  {297U, 2U}, 
  /* ENET0_ENET0_TMR1_IN input func */
  {330U, 1U}, 
  /* INMUX settings for pad PORT140:    {INMUX reg, PADSEL val} */
  /* DSPI_2_dSS input func */
  {296U, 5U}, 
  /* DSPI_3_dSS input func */
  {299U, 3U}, 
  /* INMUX settings for pad PORT142:    {INMUX reg, PADSEL val} */
  /* SPI_0_SIN_0 input func */
  {300U, 2U}, 
  /* SAI2_SAI2_D0_IN input func */
  {505U, 2U}, 
  /* INMUX settings for pad PORT143:    {INMUX reg, PADSEL val} */
  /* SPI_0_SS_0 input func */
  {302U, 4U}, 
  /* SAI2_SAI2_MCLK_IN input func */
  {503U, 2U}, 
  /* INMUX settings for pad PORT144:    {INMUX reg, PADSEL val} */
  /* SAI2_SAI2_SYNC_IN input func */
  {504U, 2U}, 
  /* INMUX settings for pad PORT145:    {INMUX reg, PADSEL val} */
  /* SPI_1_SIN_1 input func */
  {303U, 1U}, 
  /* SAI2_SAI2_BCLK_IN input func */
  {502U, 1U}, 
  /* INMUX settings for pad PORT146:    {INMUX reg, PADSEL val} */
  /* SPI_1_SS_1 input func */
  {305U, 2U}, 
  /* SPI_2_SS_2 input func */
  {308U, 3U}, 
  /* SPI_3_SS_3 input func */
  {311U, 2U}, 
  /* SAI1_SAI1_D0_IN input func */
  {498U, 1U}, 
  /* INMUX settings for pad PORT147:    {INMUX reg, PADSEL val} */
  /* SAI1_SAI1_BCLK_IN input func */
  {495U, 1U}, 
  /* INMUX settings for pad PORT148:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_18_Y_IN input func */
  {54U, 3U}, 
  /* SPI_1_SCLK_1_IN input func */
  {304U, 1U}, 
  /* FCCU_EIN_ERR input func */
  {501U, 2U}, 
  /* INMUX settings for pad PORT149:    {INMUX reg, PADSEL val} */
  /* SAI2_SAI2_D0_IN input func */
  {505U, 1U}, 
  /* INMUX settings for pad PORT150:    {INMUX reg, PADSEL val} */
  /* SAI2_SAI2_BCLK_IN input func */
  {502U, 2U}, 
  /* INMUX settings for pad PORT151:    {INMUX reg, PADSEL val} */
  /* SAI2_SAI2_MCLK_IN input func */
  {503U, 1U}, 
  /* INMUX settings for pad PORT152:    {INMUX reg, PADSEL val} */
  /* SAI2_SAI2_SYNC_IN input func */
  {504U, 1U}, 
  /* INMUX settings for pad PORT153:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_17_Y_IN input func */
  {53U, 4U}, 
  /* INMUX settings for pad PORT154:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_16_X_IN input func */
  {52U, 3U}, 
  /* FlexCAN_4_RX input func */
  {192U, 4U}, 
  /* INMUX settings for pad PORT155:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_11_H_IN input func */
  {47U, 3U}, 
  /* INMUX settings for pad PORT156:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_10_H_IN input func */
  {46U, 3U}, 
  /* FlexCAN_2_RX input func */
  {190U, 3U}, 
  /* INMUX settings for pad PORT157:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_15_H_IN input func */
  {51U, 3U}, 
  /* FlexCAN_1_RX input func */
  {189U, 5U}, 
  /* FlexCAN_4_RX input func */
  {192U, 5U}, 
  /* FlexCAN_6_RX input func */
  {194U, 2U}, 
  /* INMUX settings for pad PORT158:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_14_H_IN input func */
  {50U, 3U}, 
  /* INMUX settings for pad PORT159:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_13_H_IN input func */
  {49U, 3U}, 
  /* FlexCAN_1_RX input func */
  {189U, 6U}, 
  /* FlexCAN_3_RX input func */
  {191U, 5U}, 
  /* INMUX settings for pad PORT160:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_12_H_IN input func */
  {48U, 3U}, 
  /* INMUX settings for pad PORT161:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_1_H_IN input func */
  {37U, 4U}, 
  /* FlexCAN_4_RX input func */
  {192U, 6U}, 
  /* EMIOS0_E0UC_6_G_IN input func */
  {6U, 4U}, 
  /* INMUX settings for pad PORT162:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_2_H_IN input func */
  {38U, 4U}, 
  /* INMUX settings for pad PORT163:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_0_X_IN input func */
  {36U, 3U}, 
  /* EMIOS1_E1UC_3_H_IN input func */
  {39U, 4U}, 
  /* SIUL2_EIRQ31 input func */
  {175U, 1U}, 
  /* FlexCAN_5_RX input func */
  {193U, 3U}, 
  /* LIN_8_LIN8RX input func */
  {208U, 3U}, 
  /* INMUX settings for pad PORT164:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_1_H_IN input func */
  {37U, 5U}, 
  /* EMIOS0_E0UC_9_H_IN input func */
  {9U, 3U}, 
  /* INMUX settings for pad PORT165:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_4_H_IN input func */
  {40U, 4U}, 
  /* FlexCAN_2_RX input func */
  {190U, 4U}, 
  /* LIN_2_LIN2RX input func */
  {202U, 3U}, 
  /* EMIOS0_E0UC_10_H_IN input func */
  {10U, 4U}, 
  /* INMUX settings for pad PORT166:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_5_H_IN input func */
  {41U, 4U}, 
  /* EMIOS0_E0UC_11_H_IN input func */
  {11U, 4U}, 
  /* INMUX settings for pad PORT167:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_6_H_IN input func */
  {42U, 3U}, 
  /* FlexCAN_3_RX input func */
  {191U, 6U}, 
  /* LIN_3_LIN3RX input func */
  {203U, 3U}, 
  /* EMIOS0_E0UC_12_H_IN input func */
  {12U, 4U}, 
  /* INMUX settings for pad PORT168:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_7_H_IN input func */
  {43U, 3U}, 
  /* EMIOS0_E0UC_13_H_IN input func */
  {13U, 5U}, 
  /* INMUX settings for pad PORT169:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_29_Y_IN input func */
  {65U, 4U}, 
  /* LIN_15_LIN15RX input func */
  {215U, 2U}, 
  /* SPI_0_SIN_0 input func */
  {300U, 3U}, 
  /* GLITCH_FILTER2_INP input func */
  {508U, 6U}, 
  /* INMUX settings for pad PORT170:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_30_Y_IN input func */
  {66U, 5U}, 
  /* GLITCH_FILTER3_INP input func */
  {509U, 4U}, 
  /* INMUX settings for pad PORT171:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_31_Y_IN input func */
  {67U, 5U}, 
  /* SPI_0_SCLK_0_IN input func */
  {301U, 5U}, 
  /* GLITCH_FILTER3_INP input func */
  {509U, 8U}, 
  /* INMUX settings for pad PORT172:    {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_0_X_IN input func */
  {0U, 4U}, 
  /* LIN_14_LIN14RX input func */
  {214U, 2U}, 
  /* SPI_0_SS_0 input func */
  {302U, 5U}, 
  /* INMUX settings for pad PORT173:    {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_1_G_IN input func */
  {1U, 4U}, 
  /* FlexCAN_3_RX input func */
  {191U, 7U}, 
  /* SPI_1_SCLK_1_IN input func */
  {304U, 2U}, 
  /* INMUX settings for pad PORT174:    {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_2_G_IN input func */
  {2U, 3U}, 
  /* SPI_1_SS_1 input func */
  {305U, 3U}, 
  /* INMUX settings for pad PORT175:    {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_3_G_IN input func */
  {3U, 5U}, 
  /* SPI_1_SIN_1 input func */
  {303U, 2U}, 
  /* SPI_3_SIN_3 input func */
  {309U, 2U}, 
  /* INMUX settings for pad PORT176:    {INMUX reg, PADSEL val} */
  /* EMIOS0_E0UC_4_G_IN input func */
  {4U, 4U}, 
  /* LIN_13_LIN13RX input func */
  {213U, 2U}, 
  /* INMUX settings for pad PORT177:    {INMUX reg, PADSEL val} */
  /* SAI0_SAI0_D0_IN input func */
  {491U, 2U}, 
  /* INMUX settings for pad PORT195:    {INMUX reg, PADSEL val} */
  /* SAI0_SAI0_D1_IN input func */
  {492U, 3U}, 
  /* ENET0_ENET0_TMR2_IN input func */
  {331U, 1U}, 
  /* INMUX settings for pad PORT196:    {INMUX reg, PADSEL val} */
  /* SAI0_SAI0_D2_IN input func */
  {493U, 3U}, 
  /* INMUX settings for pad PORT197:    {INMUX reg, PADSEL val} */
  /* SAI0_SAI0_D3_IN input func */
  {494U, 3U}, 
  /* INMUX settings for pad PORT206:    {INMUX reg, PADSEL val} */
  /* SAI0_SAI0_MCLK_IN input func */
  {489U, 3U}, 
  /* INMUX settings for pad PORT224:    {INMUX reg, PADSEL val} */
  /* IIC_0_SDA0_IN input func */
  {266U, 3U}, 
  /* INMUX settings for pad PORT225:    {INMUX reg, PADSEL val} */
  /* LIN_12_LIN12RX input func */
  {212U, 2U}, 
  /* IIC_0_SCL0_IN input func */
  {265U, 3U}, 
  /* INMUX settings for pad PORT252:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_24_X_IN input func */
  {60U, 3U}, 
  /* SPI_2_SS_2 input func */
  {308U, 4U}, 
  /* INMUX settings for pad PORT253:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_23_X_IN input func */
  {59U, 3U}, 
  /* INMUX settings for pad PORT254:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_22_X_IN input func */
  {58U, 3U}, 
  /* SPI_2_SCLK_2_IN input func */
  {307U, 2U}, 
  /* INMUX settings for pad PORT255:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_21_Y_IN input func */
  {57U, 3U}, 
  /* SPI_2_SIN_2 input func */
  {306U, 2U}, 
  /* INMUX settings for pad PORT257:    {INMUX reg, PADSEL val} */
  /* DSPI_0_dSS input func */
  {290U, 4U}, 
  /* INMUX settings for pad PORT258:    {INMUX reg, PADSEL val} */
  /* DSPI_0_dSCLK_IN input func */
  {289U, 3U}, 
  /* INMUX settings for pad PORT259:    {INMUX reg, PADSEL val} */
  /* DSPI_0_dSIN input func */
  {288U, 2U}, 
  /* INMUX settings for pad PORT260:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_28_Y_IN input func */
  {64U, 4U}, 
  /* GLITCH_FILTER2_INP input func */
  {508U, 3U}, 
  /* INMUX settings for pad PORT261:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_27_Y_IN input func */
  {63U, 4U}, 
  /* INMUX settings for pad PORT262:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_26_Y_IN input func */
  {62U, 4U}, 
  /* INMUX settings for pad PORT263:    {INMUX reg, PADSEL val} */
  /* EMIOS1_E1UC_25_Y_IN input func */
  {61U, 4U}
[!ENDVAR!]


[!VAR "INPUT_INMUX_"!]
  /* INMUX settings for pad not available:  */
  { NO_INPUTMUX_U16, 0U},

[!ENDVAR!]


[!VAR "INPUT_INDEX_1"!]
  /* Index to address the input settings for pad 0*/
  (uint16)1, 
  /* Index to address the input settings for pad 1*/
  (uint16)4, 
  /* Index to address the input settings for pad 2*/
  (uint16)6, 
  /* Index to address the input settings for pad 3*/
  (uint16)7, 
  /* Index to address the input settings for pad 4*/
  (uint16)10, 
  /* Index to address the input settings for pad 5*/
  (uint16)14, 
  /* Index to address the input settings for pad 6*/
  (uint16)15, 
  /* Index to address the input settings for pad 7*/
  (uint16)18, 
  /* Index to address the input settings for pad 8*/
  (uint16)21, 
  /* Index to address the input settings for pad 9*/
  (uint16)26, 
  /* Index to address the input settings for pad 10*/
  (uint16)28, 
  /* Index to address the input settings for pad 11*/
  (uint16)32, 
  /* Index to address the input settings for pad 12*/
  (uint16)37, 
  /* Index to address the input settings for pad 13*/
  (uint16)42, 
  /* Index to address the input settings for pad 14*/
  (uint16)45, 
  /* Index to address the input settings for pad 15*/
  (uint16)50, 
  /* Index to address the input settings for pad 16*/
  (uint16)55, 
  /* Index to address the input settings for pad 17*/
  (uint16)58, 
  /* Index to address the input settings for pad 18*/
  (uint16)0, 
  /* Index to address the input settings for pad 19*/
  (uint16)0, 
  /* Index to address the input settings for pad 20*/
  (uint16)0, 
  /* Index to address the input settings for pad 21*/
  (uint16)0, 
  /* Index to address the input settings for pad 22*/
  (uint16)0, 
  /* Index to address the input settings for pad 23*/
  (uint16)0, 
  /* Index to address the input settings for pad 24*/
  (uint16)0, 
  /* Index to address the input settings for pad 25*/
  (uint16)0, 
  /* Index to address the input settings for pad 26*/
  (uint16)63, 
  /* Index to address the input settings for pad 27*/
  (uint16)0, 
  /* Index to address the input settings for pad 28*/
  (uint16)0, 
  /* Index to address the input settings for pad 29*/
  (uint16)0, 
  /* Index to address the input settings for pad 30*/
  (uint16)0, 
  /* Index to address the input settings for pad 31*/
  (uint16)0, 
  /* Index to address the input settings for pad 32*/
  (uint16)0, 
  /* Index to address the input settings for pad 33*/
  (uint16)0, 
  /* Index to address the input settings for pad 34*/
  (uint16)0, 
  /* Index to address the input settings for pad 35*/
  (uint16)0, 
  /* Index to address the input settings for pad 36*/
  (uint16)0, 
  /* Index to address the input settings for pad 37*/
  (uint16)66, 
  /* Index to address the input settings for pad 38*/
  (uint16)0, 
  /* Index to address the input settings for pad 39*/
  (uint16)0, 
  /* Index to address the input settings for pad 40*/
  (uint16)0, 
  /* Index to address the input settings for pad 41*/
  (uint16)0, 
  /* Index to address the input settings for pad 42*/
  (uint16)0, 
  /* Index to address the input settings for pad 43*/
  (uint16)67, 
  /* Index to address the input settings for pad 44*/
  (uint16)0, 
  /* Index to address the input settings for pad 45*/
  (uint16)0, 
  /* Index to address the input settings for pad 46*/
  (uint16)0, 
  /* Index to address the input settings for pad 47*/
  (uint16)0, 
  /* Index to address the input settings for pad 48*/
  (uint16)0, 
  /* Index to address the input settings for pad 49*/
  (uint16)0, 
  /* Index to address the input settings for pad 50*/
  (uint16)0, 
  /* Index to address the input settings for pad 51*/
  (uint16)0, 
  /* Index to address the input settings for pad 52*/
  (uint16)0, 
  /* Index to address the input settings for pad 53*/
  (uint16)0, 
  /* Index to address the input settings for pad 54*/
  (uint16)0, 
  /* Index to address the input settings for pad 55*/
  (uint16)0, 
  /* Index to address the input settings for pad 56*/
  (uint16)0, 
  /* Index to address the input settings for pad 57*/
  (uint16)0, 
  /* Index to address the input settings for pad 58*/
  (uint16)0, 
  /* Index to address the input settings for pad 59*/
  (uint16)0, 
  /* Index to address the input settings for pad 60*/
  (uint16)0, 
  /* Index to address the input settings for pad 61*/
  (uint16)70, 
  /* Index to address the input settings for pad 62*/
  (uint16)0, 
  /* Index to address the input settings for pad 63*/
  (uint16)0, 
  /* Index to address the input settings for pad 64*/
  (uint16)0, 
  /* Index to address the input settings for pad 65*/
  (uint16)0, 
  /* Index to address the input settings for pad 66*/
  (uint16)73, 
  /* Index to address the input settings for pad 67*/
  (uint16)76, 
  /* Index to address the input settings for pad 68*/
  (uint16)0, 
  /* Index to address the input settings for pad 69*/
  (uint16)0, 
  /* Index to address the input settings for pad 70*/
  (uint16)0, 
  /* Index to address the input settings for pad 71*/
  (uint16)0, 
  /* Index to address the input settings for pad 72*/
  (uint16)78, 
  /* Index to address the input settings for pad 73*/
  (uint16)80, 
  /* Index to address the input settings for pad 74*/
  (uint16)0, 
  /* Index to address the input settings for pad 75*/
  (uint16)0, 
  /* Index to address the input settings for pad 76*/
  (uint16)0, 
  /* Index to address the input settings for pad 77*/
  (uint16)84, 
  /* Index to address the input settings for pad 78*/
  (uint16)0, 
  /* Index to address the input settings for pad 79*/
  (uint16)86, 
  /* Index to address the input settings for pad 80*/
  (uint16)89, 
  /* Index to address the input settings for pad 81*/
  (uint16)0, 
  /* Index to address the input settings for pad 82*/
  (uint16)0, 
  /* Index to address the input settings for pad 83*/
  (uint16)0, 
  /* Index to address the input settings for pad 84*/
  (uint16)0, 
  /* Index to address the input settings for pad 85*/
  (uint16)91, 
  /* Index to address the input settings for pad 86*/
  (uint16)0, 
  /* Index to address the input settings for pad 87*/
  (uint16)0, 
  /* Index to address the input settings for pad 88*/
  (uint16)94, 
  /* Index to address the input settings for pad 89*/
  (uint16)95, 
  /* Index to address the input settings for pad 90*/
  (uint16)99, 
  /* Index to address the input settings for pad 91*/
  (uint16)0, 
  /* Index to address the input settings for pad 92*/
  (uint16)0, 
  /* Index to address the input settings for pad 93*/
  (uint16)0, 
  /* Index to address the input settings for pad 94*/
  (uint16)101, 
  /* Index to address the input settings for pad 95*/
  (uint16)103, 
  /* Index to address the input settings for pad 96*/
  (uint16)108, 
  /* Index to address the input settings for pad 97*/
  (uint16)109, 
  /* Index to address the input settings for pad 98*/
  (uint16)113, 
  /* Index to address the input settings for pad 99*/
  (uint16)114, 
  /* Index to address the input settings for pad 100*/
  (uint16)0, 
  /* Index to address the input settings for pad 101*/
  (uint16)0, 
  /* Index to address the input settings for pad 102*/
  (uint16)117, 
  /* Index to address the input settings for pad 103*/
  (uint16)119, 
  /* Index to address the input settings for pad 104*/
  (uint16)0, 
  /* Index to address the input settings for pad 105*/
  (uint16)0, 
  /* Index to address the input settings for pad 106*/
  (uint16)0, 
  /* Index to address the input settings for pad 107*/
  (uint16)123, 
  /* Index to address the input settings for pad 108*/
  (uint16)126, 
  /* Index to address the input settings for pad 109*/
  (uint16)127, 
  /* Index to address the input settings for pad 110*/
  (uint16)129, 
  /* Index to address the input settings for pad 111*/
  (uint16)131, 
  /* Index to address the input settings for pad 112*/
  (uint16)133, 
  /* Index to address the input settings for pad 113*/
  (uint16)135, 
  /* Index to address the input settings for pad 114*/
  (uint16)136, 
  /* Index to address the input settings for pad 115*/
  (uint16)0, 
  /* Index to address the input settings for pad 116*/
  (uint16)0, 
  /* Index to address the input settings for pad 117*/
  (uint16)0, 
  /* Index to address the input settings for pad 118*/
  (uint16)0, 
  /* Index to address the input settings for pad 119*/
  (uint16)0, 
  /* Index to address the input settings for pad 120*/
  (uint16)0, 
  /* Index to address the input settings for pad 121*/
  (uint16)0, 
  /* Index to address the input settings for pad 122*/
  (uint16)0, 
  /* Index to address the input settings for pad 123*/
  (uint16)0, 
  /* Index to address the input settings for pad 124*/
  (uint16)138, 
  /* Index to address the input settings for pad 125*/
  (uint16)0, 
  /* Index to address the input settings for pad 126*/
  (uint16)0, 
  /* Index to address the input settings for pad 127*/
  (uint16)0, 
  /* Index to address the input settings for pad 128*/
  (uint16)140, 
  /* Index to address the input settings for pad 129*/
  (uint16)143, 
  /* Index to address the input settings for pad 130*/
  (uint16)147, 
  /* Index to address the input settings for pad 131*/
  (uint16)150, 
  /* Index to address the input settings for pad 132*/
  (uint16)0, 
  /* Index to address the input settings for pad 133*/
  (uint16)0, 
  /* Index to address the input settings for pad 134*/
  (uint16)0, 
  /* Index to address the input settings for pad 135*/
  (uint16)0, 
  /* Index to address the input settings for pad 136*/
  (uint16)0, 
  /* Index to address the input settings for pad 137*/
  (uint16)0, 
  /* Index to address the input settings for pad 138*/
  (uint16)0, 
  /* Index to address the input settings for pad 139*/
  (uint16)0, 
  /* Index to address the input settings for pad 140*/
  (uint16)0, 
  /* Index to address the input settings for pad 141*/
  (uint16)0, 
  /* Index to address the input settings for pad 142*/
  (uint16)154, 
  /* Index to address the input settings for pad 143*/
  (uint16)0, 
  /* Index to address the input settings for pad 144*/
  (uint16)156, 
  /* Index to address the input settings for pad 145*/
  (uint16)157, 
  /* Index to address the input settings for pad 146*/
  (uint16)159, 
  /* Index to address the input settings for pad 147*/
  (uint16)0, 
  /* Index to address the input settings for pad 148*/
  (uint16)0, 
  /* Index to address the input settings for pad 149*/
  (uint16)0, 
  /* Index to address the input settings for pad 150*/
  (uint16)0, 
  /* Index to address the input settings for pad 151*/
  (uint16)0, 
  /* Index to address the input settings for pad 152*/
  (uint16)0, 
  /* Index to address the input settings for pad 153*/
  (uint16)0, 
  /* Index to address the input settings for pad 154*/
  (uint16)0, 
  /* Index to address the input settings for pad 155*/
  (uint16)0, 
  /* Index to address the input settings for pad 156*/
  (uint16)0, 
  /* Index to address the input settings for pad 157*/
  (uint16)163, 
  /* Index to address the input settings for pad 158*/
  (uint16)167
[!ENDVAR!]


[!VAR "NUMBER_INDEX_1"!][!//
168[!//
[!ENDVAR!]


[!VAR "INPUT_INDEX_2"!]
  /* Index to address the input settings for pad 0*/
  (uint16)1, 
  /* Index to address the input settings for pad 1*/
  (uint16)4, 
  /* Index to address the input settings for pad 2*/
  (uint16)6, 
  /* Index to address the input settings for pad 3*/
  (uint16)7, 
  /* Index to address the input settings for pad 4*/
  (uint16)10, 
  /* Index to address the input settings for pad 5*/
  (uint16)14, 
  /* Index to address the input settings for pad 6*/
  (uint16)15, 
  /* Index to address the input settings for pad 7*/
  (uint16)18, 
  /* Index to address the input settings for pad 8*/
  (uint16)21, 
  /* Index to address the input settings for pad 9*/
  (uint16)26, 
  /* Index to address the input settings for pad 10*/
  (uint16)28, 
  /* Index to address the input settings for pad 11*/
  (uint16)32, 
  /* Index to address the input settings for pad 12*/
  (uint16)37, 
  /* Index to address the input settings for pad 13*/
  (uint16)42, 
  /* Index to address the input settings for pad 14*/
  (uint16)45, 
  /* Index to address the input settings for pad 15*/
  (uint16)50, 
  /* Index to address the input settings for pad 16*/
  (uint16)55, 
  /* Index to address the input settings for pad 17*/
  (uint16)58, 
  /* Index to address the input settings for pad 18*/
  (uint16)63, 
  /* Index to address the input settings for pad 19*/
  (uint16)66, 
  /* Index to address the input settings for pad 20*/
  (uint16)0, 
  /* Index to address the input settings for pad 21*/
  (uint16)0, 
  /* Index to address the input settings for pad 22*/
  (uint16)0, 
  /* Index to address the input settings for pad 23*/
  (uint16)0, 
  /* Index to address the input settings for pad 24*/
  (uint16)0, 
  /* Index to address the input settings for pad 25*/
  (uint16)0, 
  /* Index to address the input settings for pad 26*/
  (uint16)71, 
  /* Index to address the input settings for pad 27*/
  (uint16)74, 
  /* Index to address the input settings for pad 28*/
  (uint16)76, 
  /* Index to address the input settings for pad 29*/
  (uint16)77, 
  /* Index to address the input settings for pad 30*/
  (uint16)78, 
  /* Index to address the input settings for pad 31*/
  (uint16)79, 
  /* Index to address the input settings for pad 32*/
  (uint16)0, 
  /* Index to address the input settings for pad 33*/
  (uint16)0, 
  /* Index to address the input settings for pad 34*/
  (uint16)80, 
  /* Index to address the input settings for pad 35*/
  (uint16)82, 
  /* Index to address the input settings for pad 36*/
  (uint16)86, 
  /* Index to address the input settings for pad 37*/
  (uint16)91, 
  /* Index to address the input settings for pad 38*/
  (uint16)92, 
  /* Index to address the input settings for pad 39*/
  (uint16)95, 
  /* Index to address the input settings for pad 40*/
  (uint16)99, 
  /* Index to address the input settings for pad 41*/
  (uint16)100, 
  /* Index to address the input settings for pad 42*/
  (uint16)0, 
  /* Index to address the input settings for pad 43*/
  (uint16)102, 
  /* Index to address the input settings for pad 44*/
  (uint16)105, 
  /* Index to address the input settings for pad 45*/
  (uint16)108, 
  /* Index to address the input settings for pad 46*/
  (uint16)109, 
  /* Index to address the input settings for pad 47*/
  (uint16)112, 
  /* Index to address the input settings for pad 48*/
  (uint16)0, 
  /* Index to address the input settings for pad 49*/
  (uint16)0, 
  /* Index to address the input settings for pad 50*/
  (uint16)0, 
  /* Index to address the input settings for pad 51*/
  (uint16)0, 
  /* Index to address the input settings for pad 52*/
  (uint16)0, 
  /* Index to address the input settings for pad 53*/
  (uint16)0, 
  /* Index to address the input settings for pad 54*/
  (uint16)0, 
  /* Index to address the input settings for pad 55*/
  (uint16)0, 
  /* Index to address the input settings for pad 56*/
  (uint16)0, 
  /* Index to address the input settings for pad 57*/
  (uint16)0, 
  /* Index to address the input settings for pad 58*/
  (uint16)0, 
  /* Index to address the input settings for pad 59*/
  (uint16)0, 
  /* Index to address the input settings for pad 60*/
  (uint16)116, 
  /* Index to address the input settings for pad 61*/
  (uint16)117, 
  /* Index to address the input settings for pad 62*/
  (uint16)120, 
  /* Index to address the input settings for pad 63*/
  (uint16)121, 
  /* Index to address the input settings for pad 64*/
  (uint16)122, 
  /* Index to address the input settings for pad 65*/
  (uint16)126, 
  /* Index to address the input settings for pad 66*/
  (uint16)128, 
  /* Index to address the input settings for pad 67*/
  (uint16)131, 
  /* Index to address the input settings for pad 68*/
  (uint16)133, 
  /* Index to address the input settings for pad 69*/
  (uint16)136, 
  /* Index to address the input settings for pad 70*/
  (uint16)139, 
  /* Index to address the input settings for pad 71*/
  (uint16)141, 
  /* Index to address the input settings for pad 72*/
  (uint16)143, 
  /* Index to address the input settings for pad 73*/
  (uint16)145, 
  /* Index to address the input settings for pad 74*/
  (uint16)149, 
  /* Index to address the input settings for pad 75*/
  (uint16)153, 
  /* Index to address the input settings for pad 76*/
  (uint16)156, 
  /* Index to address the input settings for pad 77*/
  (uint16)160, 
  /* Index to address the input settings for pad 78*/
  (uint16)162, 
  /* Index to address the input settings for pad 79*/
  (uint16)165, 
  /* Index to address the input settings for pad 80*/
  (uint16)168, 
  /* Index to address the input settings for pad 81*/
  (uint16)170, 
  /* Index to address the input settings for pad 82*/
  (uint16)172, 
  /* Index to address the input settings for pad 83*/
  (uint16)176, 
  /* Index to address the input settings for pad 84*/
  (uint16)179, 
  /* Index to address the input settings for pad 85*/
  (uint16)182, 
  /* Index to address the input settings for pad 86*/
  (uint16)185, 
  /* Index to address the input settings for pad 87*/
  (uint16)188, 
  /* Index to address the input settings for pad 88*/
  (uint16)190, 
  /* Index to address the input settings for pad 89*/
  (uint16)191, 
  /* Index to address the input settings for pad 90*/
  (uint16)195, 
  /* Index to address the input settings for pad 91*/
  (uint16)197, 
  /* Index to address the input settings for pad 92*/
  (uint16)200, 
  /* Index to address the input settings for pad 93*/
  (uint16)202, 
  /* Index to address the input settings for pad 94*/
  (uint16)205, 
  /* Index to address the input settings for pad 95*/
  (uint16)207, 
  /* Index to address the input settings for pad 96*/
  (uint16)212, 
  /* Index to address the input settings for pad 97*/
  (uint16)213, 
  /* Index to address the input settings for pad 98*/
  (uint16)217, 
  /* Index to address the input settings for pad 99*/
  (uint16)218, 
  /* Index to address the input settings for pad 100*/
  (uint16)221, 
  /* Index to address the input settings for pad 101*/
  (uint16)223, 
  /* Index to address the input settings for pad 102*/
  (uint16)227, 
  /* Index to address the input settings for pad 103*/
  (uint16)229, 
  /* Index to address the input settings for pad 104*/
  (uint16)233, 
  /* Index to address the input settings for pad 105*/
  (uint16)236, 
  /* Index to address the input settings for pad 106*/
  (uint16)241, 
  /* Index to address the input settings for pad 107*/
  (uint16)245, 
  /* Index to address the input settings for pad 108*/
  (uint16)248, 
  /* Index to address the input settings for pad 109*/
  (uint16)249, 
  /* Index to address the input settings for pad 110*/
  (uint16)251, 
  /* Index to address the input settings for pad 111*/
  (uint16)253, 
  /* Index to address the input settings for pad 112*/
  (uint16)255, 
  /* Index to address the input settings for pad 113*/
  (uint16)257, 
  /* Index to address the input settings for pad 114*/
  (uint16)258, 
  /* Index to address the input settings for pad 115*/
  (uint16)260, 
  /* Index to address the input settings for pad 116*/
  (uint16)262, 
  /* Index to address the input settings for pad 117*/
  (uint16)264, 
  /* Index to address the input settings for pad 118*/
  (uint16)267, 
  /* Index to address the input settings for pad 119*/
  (uint16)269, 
  /* Index to address the input settings for pad 120*/
  (uint16)271, 
  /* Index to address the input settings for pad 121*/
  (uint16)0, 
  /* Index to address the input settings for pad 122*/
  (uint16)0, 
  /* Index to address the input settings for pad 123*/
  (uint16)272, 
  /* Index to address the input settings for pad 124*/
  (uint16)274, 
  /* Index to address the input settings for pad 125*/
  (uint16)276, 
  /* Index to address the input settings for pad 126*/
  (uint16)278, 
  /* Index to address the input settings for pad 127*/
  (uint16)281, 
  /* Index to address the input settings for pad 128*/
  (uint16)282, 
  /* Index to address the input settings for pad 129*/
  (uint16)285, 
  /* Index to address the input settings for pad 130*/
  (uint16)289, 
  /* Index to address the input settings for pad 131*/
  (uint16)292, 
  /* Index to address the input settings for pad 132*/
  (uint16)296, 
  /* Index to address the input settings for pad 133*/
  (uint16)298, 
  /* Index to address the input settings for pad 134*/
  (uint16)301, 
  /* Index to address the input settings for pad 135*/
  (uint16)306, 
  /* Index to address the input settings for pad 136*/
  (uint16)0, 
  /* Index to address the input settings for pad 137*/
  (uint16)0, 
  /* Index to address the input settings for pad 138*/
  (uint16)0, 
  /* Index to address the input settings for pad 139*/
  (uint16)308, 
  /* Index to address the input settings for pad 140*/
  (uint16)310, 
  /* Index to address the input settings for pad 141*/
  (uint16)0, 
  /* Index to address the input settings for pad 142*/
  (uint16)312, 
  /* Index to address the input settings for pad 143*/
  (uint16)314, 
  /* Index to address the input settings for pad 144*/
  (uint16)316, 
  /* Index to address the input settings for pad 145*/
  (uint16)317, 
  /* Index to address the input settings for pad 146*/
  (uint16)319, 
  /* Index to address the input settings for pad 147*/
  (uint16)323, 
  /* Index to address the input settings for pad 148*/
  (uint16)324
[!ENDVAR!]


[!VAR "NUMBER_INDEX_2"!][!//
327[!//
[!ENDVAR!]


[!VAR "INPUT_INDEX_3"!]
  /* Index to address the input settings for pad 0*/
  (uint16)1, 
  /* Index to address the input settings for pad 1*/
  (uint16)4, 
  /* Index to address the input settings for pad 2*/
  (uint16)6, 
  /* Index to address the input settings for pad 3*/
  (uint16)7, 
  /* Index to address the input settings for pad 4*/
  (uint16)10, 
  /* Index to address the input settings for pad 5*/
  (uint16)14, 
  /* Index to address the input settings for pad 6*/
  (uint16)15, 
  /* Index to address the input settings for pad 7*/
  (uint16)18, 
  /* Index to address the input settings for pad 8*/
  (uint16)21, 
  /* Index to address the input settings for pad 9*/
  (uint16)26, 
  /* Index to address the input settings for pad 10*/
  (uint16)28, 
  /* Index to address the input settings for pad 11*/
  (uint16)32, 
  /* Index to address the input settings for pad 12*/
  (uint16)37, 
  /* Index to address the input settings for pad 13*/
  (uint16)42, 
  /* Index to address the input settings for pad 14*/
  (uint16)45, 
  /* Index to address the input settings for pad 15*/
  (uint16)50, 
  /* Index to address the input settings for pad 16*/
  (uint16)55, 
  /* Index to address the input settings for pad 17*/
  (uint16)58, 
  /* Index to address the input settings for pad 18*/
  (uint16)63, 
  /* Index to address the input settings for pad 19*/
  (uint16)66, 
  /* Index to address the input settings for pad 20*/
  (uint16)0, 
  /* Index to address the input settings for pad 21*/
  (uint16)0, 
  /* Index to address the input settings for pad 22*/
  (uint16)0, 
  /* Index to address the input settings for pad 23*/
  (uint16)0, 
  /* Index to address the input settings for pad 24*/
  (uint16)0, 
  /* Index to address the input settings for pad 25*/
  (uint16)0, 
  /* Index to address the input settings for pad 26*/
  (uint16)71, 
  /* Index to address the input settings for pad 27*/
  (uint16)74, 
  /* Index to address the input settings for pad 28*/
  (uint16)76, 
  /* Index to address the input settings for pad 29*/
  (uint16)77, 
  /* Index to address the input settings for pad 30*/
  (uint16)78, 
  /* Index to address the input settings for pad 31*/
  (uint16)79, 
  /* Index to address the input settings for pad 32*/
  (uint16)0, 
  /* Index to address the input settings for pad 33*/
  (uint16)0, 
  /* Index to address the input settings for pad 34*/
  (uint16)80, 
  /* Index to address the input settings for pad 35*/
  (uint16)82, 
  /* Index to address the input settings for pad 36*/
  (uint16)86, 
  /* Index to address the input settings for pad 37*/
  (uint16)91, 
  /* Index to address the input settings for pad 38*/
  (uint16)92, 
  /* Index to address the input settings for pad 39*/
  (uint16)95, 
  /* Index to address the input settings for pad 40*/
  (uint16)99, 
  /* Index to address the input settings for pad 41*/
  (uint16)100, 
  /* Index to address the input settings for pad 42*/
  (uint16)0, 
  /* Index to address the input settings for pad 43*/
  (uint16)102, 
  /* Index to address the input settings for pad 44*/
  (uint16)105, 
  /* Index to address the input settings for pad 45*/
  (uint16)108, 
  /* Index to address the input settings for pad 46*/
  (uint16)109, 
  /* Index to address the input settings for pad 47*/
  (uint16)112, 
  /* Index to address the input settings for pad 48*/
  (uint16)0, 
  /* Index to address the input settings for pad 49*/
  (uint16)0, 
  /* Index to address the input settings for pad 50*/
  (uint16)0, 
  /* Index to address the input settings for pad 51*/
  (uint16)0, 
  /* Index to address the input settings for pad 52*/
  (uint16)0, 
  /* Index to address the input settings for pad 53*/
  (uint16)0, 
  /* Index to address the input settings for pad 54*/
  (uint16)0, 
  /* Index to address the input settings for pad 55*/
  (uint16)0, 
  /* Index to address the input settings for pad 56*/
  (uint16)0, 
  /* Index to address the input settings for pad 57*/
  (uint16)0, 
  /* Index to address the input settings for pad 58*/
  (uint16)0, 
  /* Index to address the input settings for pad 59*/
  (uint16)0, 
  /* Index to address the input settings for pad 60*/
  (uint16)116, 
  /* Index to address the input settings for pad 61*/
  (uint16)117, 
  /* Index to address the input settings for pad 62*/
  (uint16)120, 
  /* Index to address the input settings for pad 63*/
  (uint16)121, 
  /* Index to address the input settings for pad 64*/
  (uint16)122, 
  /* Index to address the input settings for pad 65*/
  (uint16)126, 
  /* Index to address the input settings for pad 66*/
  (uint16)128, 
  /* Index to address the input settings for pad 67*/
  (uint16)131, 
  /* Index to address the input settings for pad 68*/
  (uint16)133, 
  /* Index to address the input settings for pad 69*/
  (uint16)136, 
  /* Index to address the input settings for pad 70*/
  (uint16)139, 
  /* Index to address the input settings for pad 71*/
  (uint16)141, 
  /* Index to address the input settings for pad 72*/
  (uint16)143, 
  /* Index to address the input settings for pad 73*/
  (uint16)145, 
  /* Index to address the input settings for pad 74*/
  (uint16)149, 
  /* Index to address the input settings for pad 75*/
  (uint16)153, 
  /* Index to address the input settings for pad 76*/
  (uint16)156, 
  /* Index to address the input settings for pad 77*/
  (uint16)160, 
  /* Index to address the input settings for pad 78*/
  (uint16)162, 
  /* Index to address the input settings for pad 79*/
  (uint16)165, 
  /* Index to address the input settings for pad 80*/
  (uint16)168, 
  /* Index to address the input settings for pad 81*/
  (uint16)170, 
  /* Index to address the input settings for pad 82*/
  (uint16)172, 
  /* Index to address the input settings for pad 83*/
  (uint16)176, 
  /* Index to address the input settings for pad 84*/
  (uint16)179, 
  /* Index to address the input settings for pad 85*/
  (uint16)182, 
  /* Index to address the input settings for pad 86*/
  (uint16)185, 
  /* Index to address the input settings for pad 87*/
  (uint16)188, 
  /* Index to address the input settings for pad 88*/
  (uint16)190, 
  /* Index to address the input settings for pad 89*/
  (uint16)191, 
  /* Index to address the input settings for pad 90*/
  (uint16)195, 
  /* Index to address the input settings for pad 91*/
  (uint16)197, 
  /* Index to address the input settings for pad 92*/
  (uint16)200, 
  /* Index to address the input settings for pad 93*/
  (uint16)202, 
  /* Index to address the input settings for pad 94*/
  (uint16)205, 
  /* Index to address the input settings for pad 95*/
  (uint16)207, 
  /* Index to address the input settings for pad 96*/
  (uint16)212, 
  /* Index to address the input settings for pad 97*/
  (uint16)213, 
  /* Index to address the input settings for pad 98*/
  (uint16)217, 
  /* Index to address the input settings for pad 99*/
  (uint16)218, 
  /* Index to address the input settings for pad 100*/
  (uint16)221, 
  /* Index to address the input settings for pad 101*/
  (uint16)223, 
  /* Index to address the input settings for pad 102*/
  (uint16)227, 
  /* Index to address the input settings for pad 103*/
  (uint16)229, 
  /* Index to address the input settings for pad 104*/
  (uint16)233, 
  /* Index to address the input settings for pad 105*/
  (uint16)236, 
  /* Index to address the input settings for pad 106*/
  (uint16)241, 
  /* Index to address the input settings for pad 107*/
  (uint16)245, 
  /* Index to address the input settings for pad 108*/
  (uint16)248, 
  /* Index to address the input settings for pad 109*/
  (uint16)249, 
  /* Index to address the input settings for pad 110*/
  (uint16)251, 
  /* Index to address the input settings for pad 111*/
  (uint16)253, 
  /* Index to address the input settings for pad 112*/
  (uint16)255, 
  /* Index to address the input settings for pad 113*/
  (uint16)257, 
  /* Index to address the input settings for pad 114*/
  (uint16)258, 
  /* Index to address the input settings for pad 115*/
  (uint16)260, 
  /* Index to address the input settings for pad 116*/
  (uint16)262, 
  /* Index to address the input settings for pad 117*/
  (uint16)264, 
  /* Index to address the input settings for pad 118*/
  (uint16)267, 
  /* Index to address the input settings for pad 119*/
  (uint16)269, 
  /* Index to address the input settings for pad 120*/
  (uint16)271, 
  /* Index to address the input settings for pad 121*/
  (uint16)0, 
  /* Index to address the input settings for pad 122*/
  (uint16)0, 
  /* Index to address the input settings for pad 123*/
  (uint16)272, 
  /* Index to address the input settings for pad 124*/
  (uint16)274, 
  /* Index to address the input settings for pad 125*/
  (uint16)276, 
  /* Index to address the input settings for pad 126*/
  (uint16)278, 
  /* Index to address the input settings for pad 127*/
  (uint16)281, 
  /* Index to address the input settings for pad 128*/
  (uint16)282, 
  /* Index to address the input settings for pad 129*/
  (uint16)285, 
  /* Index to address the input settings for pad 130*/
  (uint16)289, 
  /* Index to address the input settings for pad 131*/
  (uint16)292, 
  /* Index to address the input settings for pad 132*/
  (uint16)296, 
  /* Index to address the input settings for pad 133*/
  (uint16)298, 
  /* Index to address the input settings for pad 134*/
  (uint16)301, 
  /* Index to address the input settings for pad 135*/
  (uint16)306, 
  /* Index to address the input settings for pad 136*/
  (uint16)0, 
  /* Index to address the input settings for pad 137*/
  (uint16)0, 
  /* Index to address the input settings for pad 138*/
  (uint16)0, 
  /* Index to address the input settings for pad 139*/
  (uint16)308, 
  /* Index to address the input settings for pad 140*/
  (uint16)310, 
  /* Index to address the input settings for pad 141*/
  (uint16)0, 
  /* Index to address the input settings for pad 142*/
  (uint16)312, 
  /* Index to address the input settings for pad 143*/
  (uint16)314, 
  /* Index to address the input settings for pad 144*/
  (uint16)316, 
  /* Index to address the input settings for pad 145*/
  (uint16)317, 
  /* Index to address the input settings for pad 146*/
  (uint16)319, 
  /* Index to address the input settings for pad 147*/
  (uint16)323, 
  /* Index to address the input settings for pad 148*/
  (uint16)324, 
  /* Index to address the input settings for pad 149*/
  (uint16)327, 
  /* Index to address the input settings for pad 150*/
  (uint16)328, 
  /* Index to address the input settings for pad 151*/
  (uint16)329, 
  /* Index to address the input settings for pad 152*/
  (uint16)330, 
  /* Index to address the input settings for pad 153*/
  (uint16)331, 
  /* Index to address the input settings for pad 154*/
  (uint16)332, 
  /* Index to address the input settings for pad 155*/
  (uint16)334, 
  /* Index to address the input settings for pad 156*/
  (uint16)335, 
  /* Index to address the input settings for pad 157*/
  (uint16)337, 
  /* Index to address the input settings for pad 158*/
  (uint16)341, 
  /* Index to address the input settings for pad 159*/
  (uint16)342, 
  /* Index to address the input settings for pad 160*/
  (uint16)345, 
  /* Index to address the input settings for pad 161*/
  (uint16)346, 
  /* Index to address the input settings for pad 162*/
  (uint16)349, 
  /* Index to address the input settings for pad 163*/
  (uint16)350, 
  /* Index to address the input settings for pad 164*/
  (uint16)355, 
  /* Index to address the input settings for pad 165*/
  (uint16)357, 
  /* Index to address the input settings for pad 166*/
  (uint16)361, 
  /* Index to address the input settings for pad 167*/
  (uint16)363, 
  /* Index to address the input settings for pad 168*/
  (uint16)367, 
  /* Index to address the input settings for pad 169*/
  (uint16)369, 
  /* Index to address the input settings for pad 170*/
  (uint16)373, 
  /* Index to address the input settings for pad 171*/
  (uint16)375, 
  /* Index to address the input settings for pad 172*/
  (uint16)378, 
  /* Index to address the input settings for pad 173*/
  (uint16)381, 
  /* Index to address the input settings for pad 174*/
  (uint16)384, 
  /* Index to address the input settings for pad 175*/
  (uint16)386, 
  /* Index to address the input settings for pad 176*/
  (uint16)389, 
  /* Index to address the input settings for pad 177*/
  (uint16)391, 
  /* Index to address the input settings for pad 178*/
  (uint16)0, 
  /* Index to address the input settings for pad 179*/
  (uint16)0, 
  /* Index to address the input settings for pad 180*/
  (uint16)0, 
  /* Index to address the input settings for pad 181*/
  (uint16)0, 
  /* Index to address the input settings for pad 182*/
  (uint16)0, 
  /* Index to address the input settings for pad 183*/
  (uint16)0, 
  /* Index to address the input settings for pad 184*/
  (uint16)0, 
  /* Index to address the input settings for pad 185*/
  (uint16)0, 
  /* Index to address the input settings for pad 186*/
  (uint16)0, 
  /* Index to address the input settings for pad 187*/
  (uint16)0, 
  /* Index to address the input settings for pad 188*/
  (uint16)0, 
  /* Index to address the input settings for pad 189*/
  (uint16)0, 
  /* Index to address the input settings for pad 190*/
  (uint16)0, 
  /* Index to address the input settings for pad 191*/
  (uint16)0, 
  /* Index to address the input settings for pad 192*/
  (uint16)0, 
  /* Index to address the input settings for pad 193*/
  (uint16)0, 
  /* Index to address the input settings for pad 194*/
  (uint16)0, 
  /* Index to address the input settings for pad 195*/
  (uint16)392, 
  /* Index to address the input settings for pad 196*/
  (uint16)394, 
  /* Index to address the input settings for pad 197*/
  (uint16)395, 
  /* Index to address the input settings for pad 198*/
  (uint16)0, 
  /* Index to address the input settings for pad 199*/
  (uint16)0, 
  /* Index to address the input settings for pad 200*/
  (uint16)0, 
  /* Index to address the input settings for pad 201*/
  (uint16)0, 
  /* Index to address the input settings for pad 202*/
  (uint16)0, 
  /* Index to address the input settings for pad 203*/
  (uint16)0, 
  /* Index to address the input settings for pad 204*/
  (uint16)0, 
  /* Index to address the input settings for pad 205*/
  (uint16)0, 
  /* Index to address the input settings for pad 206*/
  (uint16)396, 
  /* Index to address the input settings for pad 207*/
  (uint16)0, 
  /* Index to address the input settings for pad 208*/
  (uint16)0, 
  /* Index to address the input settings for pad 209*/
  (uint16)0, 
  /* Index to address the input settings for pad 210*/
  (uint16)0, 
  /* Index to address the input settings for pad 211*/
  (uint16)0, 
  /* Index to address the input settings for pad 212*/
  (uint16)0, 
  /* Index to address the input settings for pad 213*/
  (uint16)0, 
  /* Index to address the input settings for pad 214*/
  (uint16)0, 
  /* Index to address the input settings for pad 215*/
  (uint16)0, 
  /* Index to address the input settings for pad 216*/
  (uint16)0, 
  /* Index to address the input settings for pad 217*/
  (uint16)0, 
  /* Index to address the input settings for pad 218*/
  (uint16)0, 
  /* Index to address the input settings for pad 219*/
  (uint16)0, 
  /* Index to address the input settings for pad 220*/
  (uint16)0, 
  /* Index to address the input settings for pad 221*/
  (uint16)0, 
  /* Index to address the input settings for pad 222*/
  (uint16)0, 
  /* Index to address the input settings for pad 223*/
  (uint16)0, 
  /* Index to address the input settings for pad 224*/
  (uint16)397, 
  /* Index to address the input settings for pad 225*/
  (uint16)398, 
  /* Index to address the input settings for pad 226*/
  (uint16)0, 
  /* Index to address the input settings for pad 227*/
  (uint16)0, 
  /* Index to address the input settings for pad 228*/
  (uint16)0, 
  /* Index to address the input settings for pad 229*/
  (uint16)0, 
  /* Index to address the input settings for pad 230*/
  (uint16)0, 
  /* Index to address the input settings for pad 231*/
  (uint16)0, 
  /* Index to address the input settings for pad 232*/
  (uint16)0, 
  /* Index to address the input settings for pad 233*/
  (uint16)0, 
  /* Index to address the input settings for pad 234*/
  (uint16)0, 
  /* Index to address the input settings for pad 235*/
  (uint16)0, 
  /* Index to address the input settings for pad 236*/
  (uint16)0, 
  /* Index to address the input settings for pad 237*/
  (uint16)0, 
  /* Index to address the input settings for pad 238*/
  (uint16)0, 
  /* Index to address the input settings for pad 239*/
  (uint16)0, 
  /* Index to address the input settings for pad 240*/
  (uint16)0, 
  /* Index to address the input settings for pad 241*/
  (uint16)0, 
  /* Index to address the input settings for pad 242*/
  (uint16)0, 
  /* Index to address the input settings for pad 243*/
  (uint16)0, 
  /* Index to address the input settings for pad 244*/
  (uint16)0, 
  /* Index to address the input settings for pad 245*/
  (uint16)0, 
  /* Index to address the input settings for pad 246*/
  (uint16)0, 
  /* Index to address the input settings for pad 247*/
  (uint16)0, 
  /* Index to address the input settings for pad 248*/
  (uint16)0, 
  /* Index to address the input settings for pad 249*/
  (uint16)0, 
  /* Index to address the input settings for pad 250*/
  (uint16)0, 
  /* Index to address the input settings for pad 251*/
  (uint16)0, 
  /* Index to address the input settings for pad 252*/
  (uint16)400, 
  /* Index to address the input settings for pad 253*/
  (uint16)402, 
  /* Index to address the input settings for pad 254*/
  (uint16)403, 
  /* Index to address the input settings for pad 255*/
  (uint16)405, 
  /* Index to address the input settings for pad 256*/
  (uint16)0, 
  /* Index to address the input settings for pad 257*/
  (uint16)407, 
  /* Index to address the input settings for pad 258*/
  (uint16)408, 
  /* Index to address the input settings for pad 259*/
  (uint16)409, 
  /* Index to address the input settings for pad 260*/
  (uint16)410, 
  /* Index to address the input settings for pad 261*/
  (uint16)412, 
  /* Index to address the input settings for pad 262*/
  (uint16)413, 
  /* Index to address the input settings for pad 263*/
  (uint16)414
[!ENDVAR!]


[!VAR "NUMBER_INDEX_3"!][!//
415[!//
[!ENDVAR!]


[!VAR "INPUT_INDEX_4"!]
  /* Index to address the input settings for pad 0*/
  (uint16)1, 
  /* Index to address the input settings for pad 1*/
  (uint16)4, 
  /* Index to address the input settings for pad 2*/
  (uint16)6, 
  /* Index to address the input settings for pad 3*/
  (uint16)7, 
  /* Index to address the input settings for pad 4*/
  (uint16)10, 
  /* Index to address the input settings for pad 5*/
  (uint16)14, 
  /* Index to address the input settings for pad 6*/
  (uint16)15, 
  /* Index to address the input settings for pad 7*/
  (uint16)18, 
  /* Index to address the input settings for pad 8*/
  (uint16)21, 
  /* Index to address the input settings for pad 9*/
  (uint16)26, 
  /* Index to address the input settings for pad 10*/
  (uint16)28, 
  /* Index to address the input settings for pad 11*/
  (uint16)32, 
  /* Index to address the input settings for pad 12*/
  (uint16)37, 
  /* Index to address the input settings for pad 13*/
  (uint16)42, 
  /* Index to address the input settings for pad 14*/
  (uint16)45, 
  /* Index to address the input settings for pad 15*/
  (uint16)50, 
  /* Index to address the input settings for pad 16*/
  (uint16)55, 
  /* Index to address the input settings for pad 17*/
  (uint16)58, 
  /* Index to address the input settings for pad 18*/
  (uint16)63, 
  /* Index to address the input settings for pad 19*/
  (uint16)66, 
  /* Index to address the input settings for pad 20*/
  (uint16)0, 
  /* Index to address the input settings for pad 21*/
  (uint16)0, 
  /* Index to address the input settings for pad 22*/
  (uint16)0, 
  /* Index to address the input settings for pad 23*/
  (uint16)0, 
  /* Index to address the input settings for pad 24*/
  (uint16)0, 
  /* Index to address the input settings for pad 25*/
  (uint16)0, 
  /* Index to address the input settings for pad 26*/
  (uint16)71, 
  /* Index to address the input settings for pad 27*/
  (uint16)74, 
  /* Index to address the input settings for pad 28*/
  (uint16)76, 
  /* Index to address the input settings for pad 29*/
  (uint16)77, 
  /* Index to address the input settings for pad 30*/
  (uint16)78, 
  /* Index to address the input settings for pad 31*/
  (uint16)79, 
  /* Index to address the input settings for pad 32*/
  (uint16)0, 
  /* Index to address the input settings for pad 33*/
  (uint16)0, 
  /* Index to address the input settings for pad 34*/
  (uint16)80, 
  /* Index to address the input settings for pad 35*/
  (uint16)82, 
  /* Index to address the input settings for pad 36*/
  (uint16)86, 
  /* Index to address the input settings for pad 37*/
  (uint16)91, 
  /* Index to address the input settings for pad 38*/
  (uint16)92, 
  /* Index to address the input settings for pad 39*/
  (uint16)95, 
  /* Index to address the input settings for pad 40*/
  (uint16)99, 
  /* Index to address the input settings for pad 41*/
  (uint16)100, 
  /* Index to address the input settings for pad 42*/
  (uint16)0, 
  /* Index to address the input settings for pad 43*/
  (uint16)102, 
  /* Index to address the input settings for pad 44*/
  (uint16)105, 
  /* Index to address the input settings for pad 45*/
  (uint16)108, 
  /* Index to address the input settings for pad 46*/
  (uint16)109, 
  /* Index to address the input settings for pad 47*/
  (uint16)112, 
  /* Index to address the input settings for pad 48*/
  (uint16)0, 
  /* Index to address the input settings for pad 49*/
  (uint16)0, 
  /* Index to address the input settings for pad 50*/
  (uint16)0, 
  /* Index to address the input settings for pad 51*/
  (uint16)0, 
  /* Index to address the input settings for pad 52*/
  (uint16)0, 
  /* Index to address the input settings for pad 53*/
  (uint16)0, 
  /* Index to address the input settings for pad 54*/
  (uint16)0, 
  /* Index to address the input settings for pad 55*/
  (uint16)0, 
  /* Index to address the input settings for pad 56*/
  (uint16)0, 
  /* Index to address the input settings for pad 57*/
  (uint16)0, 
  /* Index to address the input settings for pad 58*/
  (uint16)0, 
  /* Index to address the input settings for pad 59*/
  (uint16)0, 
  /* Index to address the input settings for pad 60*/
  (uint16)116, 
  /* Index to address the input settings for pad 61*/
  (uint16)117, 
  /* Index to address the input settings for pad 62*/
  (uint16)120, 
  /* Index to address the input settings for pad 63*/
  (uint16)121, 
  /* Index to address the input settings for pad 64*/
  (uint16)122, 
  /* Index to address the input settings for pad 65*/
  (uint16)126, 
  /* Index to address the input settings for pad 66*/
  (uint16)128, 
  /* Index to address the input settings for pad 67*/
  (uint16)131, 
  /* Index to address the input settings for pad 68*/
  (uint16)133, 
  /* Index to address the input settings for pad 69*/
  (uint16)136, 
  /* Index to address the input settings for pad 70*/
  (uint16)139, 
  /* Index to address the input settings for pad 71*/
  (uint16)141, 
  /* Index to address the input settings for pad 72*/
  (uint16)143, 
  /* Index to address the input settings for pad 73*/
  (uint16)145, 
  /* Index to address the input settings for pad 74*/
  (uint16)149, 
  /* Index to address the input settings for pad 75*/
  (uint16)153, 
  /* Index to address the input settings for pad 76*/
  (uint16)156, 
  /* Index to address the input settings for pad 77*/
  (uint16)160, 
  /* Index to address the input settings for pad 78*/
  (uint16)162, 
  /* Index to address the input settings for pad 79*/
  (uint16)165, 
  /* Index to address the input settings for pad 80*/
  (uint16)168, 
  /* Index to address the input settings for pad 81*/
  (uint16)170, 
  /* Index to address the input settings for pad 82*/
  (uint16)172, 
  /* Index to address the input settings for pad 83*/
  (uint16)176, 
  /* Index to address the input settings for pad 84*/
  (uint16)179, 
  /* Index to address the input settings for pad 85*/
  (uint16)182, 
  /* Index to address the input settings for pad 86*/
  (uint16)185, 
  /* Index to address the input settings for pad 87*/
  (uint16)188, 
  /* Index to address the input settings for pad 88*/
  (uint16)190, 
  /* Index to address the input settings for pad 89*/
  (uint16)191, 
  /* Index to address the input settings for pad 90*/
  (uint16)195, 
  /* Index to address the input settings for pad 91*/
  (uint16)197, 
  /* Index to address the input settings for pad 92*/
  (uint16)200, 
  /* Index to address the input settings for pad 93*/
  (uint16)202, 
  /* Index to address the input settings for pad 94*/
  (uint16)205, 
  /* Index to address the input settings for pad 95*/
  (uint16)207, 
  /* Index to address the input settings for pad 96*/
  (uint16)212, 
  /* Index to address the input settings for pad 97*/
  (uint16)213, 
  /* Index to address the input settings for pad 98*/
  (uint16)217, 
  /* Index to address the input settings for pad 99*/
  (uint16)218, 
  /* Index to address the input settings for pad 100*/
  (uint16)221, 
  /* Index to address the input settings for pad 101*/
  (uint16)223, 
  /* Index to address the input settings for pad 102*/
  (uint16)227, 
  /* Index to address the input settings for pad 103*/
  (uint16)229, 
  /* Index to address the input settings for pad 104*/
  (uint16)233, 
  /* Index to address the input settings for pad 105*/
  (uint16)236, 
  /* Index to address the input settings for pad 106*/
  (uint16)241, 
  /* Index to address the input settings for pad 107*/
  (uint16)245, 
  /* Index to address the input settings for pad 108*/
  (uint16)248, 
  /* Index to address the input settings for pad 109*/
  (uint16)249, 
  /* Index to address the input settings for pad 110*/
  (uint16)251, 
  /* Index to address the input settings for pad 111*/
  (uint16)253, 
  /* Index to address the input settings for pad 112*/
  (uint16)255, 
  /* Index to address the input settings for pad 113*/
  (uint16)257, 
  /* Index to address the input settings for pad 114*/
  (uint16)258, 
  /* Index to address the input settings for pad 115*/
  (uint16)260, 
  /* Index to address the input settings for pad 116*/
  (uint16)262, 
  /* Index to address the input settings for pad 117*/
  (uint16)264, 
  /* Index to address the input settings for pad 118*/
  (uint16)267, 
  /* Index to address the input settings for pad 119*/
  (uint16)269, 
  /* Index to address the input settings for pad 120*/
  (uint16)271, 
  /* Index to address the input settings for pad 121*/
  (uint16)0, 
  /* Index to address the input settings for pad 122*/
  (uint16)0, 
  /* Index to address the input settings for pad 123*/
  (uint16)272, 
  /* Index to address the input settings for pad 124*/
  (uint16)274, 
  /* Index to address the input settings for pad 125*/
  (uint16)276, 
  /* Index to address the input settings for pad 126*/
  (uint16)278, 
  /* Index to address the input settings for pad 127*/
  (uint16)281, 
  /* Index to address the input settings for pad 128*/
  (uint16)282, 
  /* Index to address the input settings for pad 129*/
  (uint16)285, 
  /* Index to address the input settings for pad 130*/
  (uint16)289, 
  /* Index to address the input settings for pad 131*/
  (uint16)292, 
  /* Index to address the input settings for pad 132*/
  (uint16)296, 
  /* Index to address the input settings for pad 133*/
  (uint16)298, 
  /* Index to address the input settings for pad 134*/
  (uint16)301, 
  /* Index to address the input settings for pad 135*/
  (uint16)306, 
  /* Index to address the input settings for pad 136*/
  (uint16)0, 
  /* Index to address the input settings for pad 137*/
  (uint16)0, 
  /* Index to address the input settings for pad 138*/
  (uint16)0, 
  /* Index to address the input settings for pad 139*/
  (uint16)308, 
  /* Index to address the input settings for pad 140*/
  (uint16)310, 
  /* Index to address the input settings for pad 141*/
  (uint16)0, 
  /* Index to address the input settings for pad 142*/
  (uint16)312, 
  /* Index to address the input settings for pad 143*/
  (uint16)314, 
  /* Index to address the input settings for pad 144*/
  (uint16)316, 
  /* Index to address the input settings for pad 145*/
  (uint16)317, 
  /* Index to address the input settings for pad 146*/
  (uint16)319, 
  /* Index to address the input settings for pad 147*/
  (uint16)323, 
  /* Index to address the input settings for pad 148*/
  (uint16)324, 
  /* Index to address the input settings for pad 149*/
  (uint16)327, 
  /* Index to address the input settings for pad 150*/
  (uint16)328, 
  /* Index to address the input settings for pad 151*/
  (uint16)329, 
  /* Index to address the input settings for pad 152*/
  (uint16)330, 
  /* Index to address the input settings for pad 153*/
  (uint16)331, 
  /* Index to address the input settings for pad 154*/
  (uint16)332, 
  /* Index to address the input settings for pad 155*/
  (uint16)334, 
  /* Index to address the input settings for pad 156*/
  (uint16)335, 
  /* Index to address the input settings for pad 157*/
  (uint16)337, 
  /* Index to address the input settings for pad 158*/
  (uint16)341, 
  /* Index to address the input settings for pad 159*/
  (uint16)342, 
  /* Index to address the input settings for pad 160*/
  (uint16)345, 
  /* Index to address the input settings for pad 161*/
  (uint16)346, 
  /* Index to address the input settings for pad 162*/
  (uint16)349, 
  /* Index to address the input settings for pad 163*/
  (uint16)350, 
  /* Index to address the input settings for pad 164*/
  (uint16)355, 
  /* Index to address the input settings for pad 165*/
  (uint16)357, 
  /* Index to address the input settings for pad 166*/
  (uint16)361, 
  /* Index to address the input settings for pad 167*/
  (uint16)363, 
  /* Index to address the input settings for pad 168*/
  (uint16)367, 
  /* Index to address the input settings for pad 169*/
  (uint16)369, 
  /* Index to address the input settings for pad 170*/
  (uint16)373, 
  /* Index to address the input settings for pad 171*/
  (uint16)375, 
  /* Index to address the input settings for pad 172*/
  (uint16)378, 
  /* Index to address the input settings for pad 173*/
  (uint16)381, 
  /* Index to address the input settings for pad 174*/
  (uint16)384, 
  /* Index to address the input settings for pad 175*/
  (uint16)386, 
  /* Index to address the input settings for pad 176*/
  (uint16)389, 
  /* Index to address the input settings for pad 177*/
  (uint16)391, 
  /* Index to address the input settings for pad 178*/
  (uint16)0, 
  /* Index to address the input settings for pad 179*/
  (uint16)0, 
  /* Index to address the input settings for pad 180*/
  (uint16)0, 
  /* Index to address the input settings for pad 181*/
  (uint16)0, 
  /* Index to address the input settings for pad 182*/
  (uint16)0, 
  /* Index to address the input settings for pad 183*/
  (uint16)0, 
  /* Index to address the input settings for pad 184*/
  (uint16)0, 
  /* Index to address the input settings for pad 185*/
  (uint16)0, 
  /* Index to address the input settings for pad 186*/
  (uint16)0, 
  /* Index to address the input settings for pad 187*/
  (uint16)0, 
  /* Index to address the input settings for pad 188*/
  (uint16)0, 
  /* Index to address the input settings for pad 189*/
  (uint16)0, 
  /* Index to address the input settings for pad 190*/
  (uint16)0, 
  /* Index to address the input settings for pad 191*/
  (uint16)0, 
  /* Index to address the input settings for pad 192*/
  (uint16)0, 
  /* Index to address the input settings for pad 193*/
  (uint16)0, 
  /* Index to address the input settings for pad 194*/
  (uint16)0, 
  /* Index to address the input settings for pad 195*/
  (uint16)392, 
  /* Index to address the input settings for pad 196*/
  (uint16)394, 
  /* Index to address the input settings for pad 197*/
  (uint16)395, 
  /* Index to address the input settings for pad 198*/
  (uint16)0, 
  /* Index to address the input settings for pad 199*/
  (uint16)0, 
  /* Index to address the input settings for pad 200*/
  (uint16)0, 
  /* Index to address the input settings for pad 201*/
  (uint16)0, 
  /* Index to address the input settings for pad 202*/
  (uint16)0, 
  /* Index to address the input settings for pad 203*/
  (uint16)0, 
  /* Index to address the input settings for pad 204*/
  (uint16)0, 
  /* Index to address the input settings for pad 205*/
  (uint16)0, 
  /* Index to address the input settings for pad 206*/
  (uint16)396, 
  /* Index to address the input settings for pad 207*/
  (uint16)0, 
  /* Index to address the input settings for pad 208*/
  (uint16)0, 
  /* Index to address the input settings for pad 209*/
  (uint16)0, 
  /* Index to address the input settings for pad 210*/
  (uint16)0, 
  /* Index to address the input settings for pad 211*/
  (uint16)0, 
  /* Index to address the input settings for pad 212*/
  (uint16)0, 
  /* Index to address the input settings for pad 213*/
  (uint16)0, 
  /* Index to address the input settings for pad 214*/
  (uint16)0, 
  /* Index to address the input settings for pad 215*/
  (uint16)0, 
  /* Index to address the input settings for pad 216*/
  (uint16)0, 
  /* Index to address the input settings for pad 217*/
  (uint16)0, 
  /* Index to address the input settings for pad 218*/
  (uint16)0, 
  /* Index to address the input settings for pad 219*/
  (uint16)0, 
  /* Index to address the input settings for pad 220*/
  (uint16)0, 
  /* Index to address the input settings for pad 221*/
  (uint16)0, 
  /* Index to address the input settings for pad 222*/
  (uint16)0, 
  /* Index to address the input settings for pad 223*/
  (uint16)0, 
  /* Index to address the input settings for pad 224*/
  (uint16)397, 
  /* Index to address the input settings for pad 225*/
  (uint16)398, 
  /* Index to address the input settings for pad 226*/
  (uint16)0, 
  /* Index to address the input settings for pad 227*/
  (uint16)0, 
  /* Index to address the input settings for pad 228*/
  (uint16)0, 
  /* Index to address the input settings for pad 229*/
  (uint16)0, 
  /* Index to address the input settings for pad 230*/
  (uint16)0, 
  /* Index to address the input settings for pad 231*/
  (uint16)0, 
  /* Index to address the input settings for pad 232*/
  (uint16)0, 
  /* Index to address the input settings for pad 233*/
  (uint16)0, 
  /* Index to address the input settings for pad 234*/
  (uint16)0, 
  /* Index to address the input settings for pad 235*/
  (uint16)0, 
  /* Index to address the input settings for pad 236*/
  (uint16)0, 
  /* Index to address the input settings for pad 237*/
  (uint16)0, 
  /* Index to address the input settings for pad 238*/
  (uint16)0, 
  /* Index to address the input settings for pad 239*/
  (uint16)0, 
  /* Index to address the input settings for pad 240*/
  (uint16)0, 
  /* Index to address the input settings for pad 241*/
  (uint16)0, 
  /* Index to address the input settings for pad 242*/
  (uint16)0, 
  /* Index to address the input settings for pad 243*/
  (uint16)0, 
  /* Index to address the input settings for pad 244*/
  (uint16)0, 
  /* Index to address the input settings for pad 245*/
  (uint16)0, 
  /* Index to address the input settings for pad 246*/
  (uint16)0, 
  /* Index to address the input settings for pad 247*/
  (uint16)0, 
  /* Index to address the input settings for pad 248*/
  (uint16)0, 
  /* Index to address the input settings for pad 249*/
  (uint16)0, 
  /* Index to address the input settings for pad 250*/
  (uint16)0, 
  /* Index to address the input settings for pad 251*/
  (uint16)0, 
  /* Index to address the input settings for pad 252*/
  (uint16)400, 
  /* Index to address the input settings for pad 253*/
  (uint16)402, 
  /* Index to address the input settings for pad 254*/
  (uint16)403, 
  /* Index to address the input settings for pad 255*/
  (uint16)405, 
  /* Index to address the input settings for pad 256*/
  (uint16)0, 
  /* Index to address the input settings for pad 257*/
  (uint16)407, 
  /* Index to address the input settings for pad 258*/
  (uint16)408, 
  /* Index to address the input settings for pad 259*/
  (uint16)409, 
  /* Index to address the input settings for pad 260*/
  (uint16)410, 
  /* Index to address the input settings for pad 261*/
  (uint16)412, 
  /* Index to address the input settings for pad 262*/
  (uint16)413, 
  /* Index to address the input settings for pad 263*/
  (uint16)414
[!ENDVAR!]


[!VAR "NUMBER_INDEX_4"!][!//
415[!//
[!ENDVAR!]


[!VAR "INPUT_INDEX_"!]

[!ENDVAR!]


[!VAR "NUMBER_INDEX_"!][!//
1[!//
[!ENDVAR!]

[!ENDIF!][!//avoid multiple inclusion
